From nobody Thu Dec 25 16:01:46 2025 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C671F9E4 for ; Mon, 15 Jan 2024 10:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="I2GjGhO7" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-6d9bba6d773so7563006b3a.1 for ; Mon, 15 Jan 2024 02:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1705313471; x=1705918271; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eFE4MaRUUDjQZfE2dmgya8wKXtM/DMaoZewAWiQUHuY=; b=I2GjGhO797yGThuRfk9JtlKXqOcpieEOVfZTeYJYeZR+Y71OpmThwJv5Vqvm6T3Xge enJwJUWRIwUE8rSIMuLpeBeNCPGf6iXyWXQrhhnj6+hpfQKsjRz0TbTmdCBjtmqm+jNB td/RbLxRM2xUB8NMH4NmAxrbLmZX6kD6mXBcJzHlrM7Xd4rZiWeg2BdKZg2nNmDPAcqO iRoVLwT0vrNnif+ygtbM7dynaRyecCN6QpIAjyMw8NjtxujDx0jRW88ceXQoNzmdar3f j/RNIwT5DSywGk0GS5cwE+kl4QwY3P3poDZXG1tFCzIr/B+DLmJZrlblVMvd4GLnLK4f XM1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705313471; x=1705918271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eFE4MaRUUDjQZfE2dmgya8wKXtM/DMaoZewAWiQUHuY=; b=cPlpSnbbRigVIGx4orBbk2ZzXj9mECrlFwW/sYE4bj2MdwpEou0i+7f2LXyk5n3Pyi DCsHT1JRV6gMkWCn44WjsKUXL3skYpxkZa5ktihaUFXMfgJxoA26FWLF4zL1SZBH0KQH fVu1cLI8FZVqUnsSMlpU87MX8p7TJ/PFn4LbxxBr5zQoqTPvqHI8IBVqkEBh4d1Oa1NP iq88TTuKsz5yyoIbUcwMnGzOrqbymBw14Klhj5i0+lp5mnNsf0QqQZZpQk/uYCZoHAcA zlLYBeJadaEHBO+NLJ7v6HIR1lZTswugrkqseBCB/LmII/8NXFLje+8FNi0XkIf4hVtu 6sIg== X-Gm-Message-State: AOJu0YyngU1iEh5yc1fyHsX9zwilSULIQxJ0K2JyucO1CYZLO4rj2OAj wD+ncCSJ007ax06E4ogeuOhvm0VOmYvVTw== X-Google-Smtp-Source: AGHT+IGwU6QEd/xe6D6PNl/zIoj9NPbivgiVZqhkEXmbNsIyplJguIzU6puQpGtsO9MGyB06M5Jzrg== X-Received: by 2002:a05:6a00:ace:b0:6da:c623:f054 with SMTP id c14-20020a056a000ace00b006dac623f054mr7200673pfl.15.1705313471628; Mon, 15 Jan 2024 02:11:11 -0800 (PST) Received: from localhost.localdomain ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id u5-20020aa78385000000b006d9b8572e77sm7348256pfm.120.2024.01.15.02.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 02:11:11 -0800 (PST) From: Sunil V L To: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: "Rafael J . Wysocki" , Len Brown , Anup Patel , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Andrew Jones , Atish Kumar Patra , Pavel Machek , Sunil V L Subject: [PATCH v2 -next 1/3] cpuidle: RISC-V: Move few functions to arch/riscv Date: Mon, 15 Jan 2024 15:40:54 +0530 Message-Id: <20240115101056.429471-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115101056.429471-1-sunilvl@ventanamicro.com> References: <20240115101056.429471-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To support ACPI Low Power Idle (LPI), few functions are required which are currently static functions in the DT based cpuidle driver. Hence, move them under arch/riscv so that ACPI driver also can use them. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/include/asm/suspend.h | 3 ++ arch/riscv/kernel/suspend.c | 47 +++++++++++++++++++++++++++++ drivers/cpuidle/cpuidle-riscv-sbi.c | 41 +------------------------ 3 files changed, 51 insertions(+), 40 deletions(-) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/susp= end.h index 02f87867389a..5c7df5ab7a16 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -55,4 +55,7 @@ int hibernate_resume_nonboot_cpu_disable(void); asmlinkage void hibernate_restore_image(unsigned long resume_satp, unsigne= d long satp_temp, unsigned long cpu_resume); asmlinkage int hibernate_core_restore_code(void); +bool is_sbi_hsm_supported(void); +bool sbi_suspend_state_is_valid(u32 state); +int sbi_suspend(u32 state); #endif diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..a3b2e7e16a98 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -128,4 +128,51 @@ static int __init sbi_system_suspend_init(void) } =20 arch_initcall(sbi_system_suspend_init); + +static int sbi_suspend_finisher(unsigned long suspend_type, + unsigned long resume_addr, + unsigned long opaque) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND, + suspend_type, resume_addr, opaque, 0, 0, 0); + + return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0; +} + +int sbi_suspend(u32 state) +{ + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return cpu_suspend(state, sbi_suspend_finisher); + else + return sbi_suspend_finisher(state, 0, 0); +} + +bool sbi_suspend_state_is_valid(u32 state) +{ + if (state > SBI_HSM_SUSPEND_RET_DEFAULT && + state < SBI_HSM_SUSPEND_RET_PLATFORM) + return false; + if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT && + state < SBI_HSM_SUSPEND_NON_RET_PLATFORM) + return false; + return true; +} + +bool is_sbi_hsm_supported(void) +{ + /* + * The SBI HSM suspend function is only available when: + * 1) SBI version is 0.3 or higher + * 2) SBI HSM extension is available + */ + if (sbi_spec_version < sbi_mk_version(0, 3) || + !sbi_probe_extension(SBI_EXT_HSM)) { + pr_info("HSM suspend not available\n"); + return false; + } + + return true; +} #endif /* CONFIG_RISCV_SBI */ diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.c b/drivers/cpuidle/cpuidle-= riscv-sbi.c index e8094fc92491..a7f06242f67b 100644 --- a/drivers/cpuidle/cpuidle-riscv-sbi.c +++ b/drivers/cpuidle/cpuidle-riscv-sbi.c @@ -73,26 +73,6 @@ static inline bool sbi_is_domain_state_available(void) return data->available; } =20 -static int sbi_suspend_finisher(unsigned long suspend_type, - unsigned long resume_addr, - unsigned long opaque) -{ - struct sbiret ret; - - ret =3D sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND, - suspend_type, resume_addr, opaque, 0, 0, 0); - - return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0; -} - -static int sbi_suspend(u32 state) -{ - if (state & SBI_HSM_SUSP_NON_RET_BIT) - return cpu_suspend(state, sbi_suspend_finisher); - else - return sbi_suspend_finisher(state, 0, 0); -} - static __cpuidle int sbi_cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, int idx) { @@ -206,17 +186,6 @@ static const struct of_device_id sbi_cpuidle_state_mat= ch[] =3D { { }, }; =20 -static bool sbi_suspend_state_is_valid(u32 state) -{ - if (state > SBI_HSM_SUSPEND_RET_DEFAULT && - state < SBI_HSM_SUSPEND_RET_PLATFORM) - return false; - if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT && - state < SBI_HSM_SUSPEND_NON_RET_PLATFORM) - return false; - return true; -} - static int sbi_dt_parse_state_node(struct device_node *np, u32 *state) { int err =3D of_property_read_u32(np, "riscv,sbi-suspend-param", state); @@ -607,16 +576,8 @@ static int __init sbi_cpuidle_init(void) int ret; struct platform_device *pdev; =20 - /* - * The SBI HSM suspend function is only available when: - * 1) SBI version is 0.3 or higher - * 2) SBI HSM extension is available - */ - if ((sbi_spec_version < sbi_mk_version(0, 3)) || - !sbi_probe_extension(SBI_EXT_HSM)) { - pr_info("HSM suspend not available\n"); + if (!is_sbi_hsm_supported()) return 0; - } =20 ret =3D platform_driver_register(&sbi_cpuidle_driver); if (ret) --=20 2.34.1 From nobody Thu Dec 25 16:01:46 2025 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 905002BAEC for ; Mon, 15 Jan 2024 10:11:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="prIktfAD" Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-3bd6dc05690so1349277b6e.1 for ; Mon, 15 Jan 2024 02:11:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1705313476; x=1705918276; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FKR76xvkppExc7Ae5ic+6mPrVpT9dqve2Cn1Oe/qHYw=; b=prIktfADJjqu2qTrlGHTj0KZKU1jxS860clskcF1Pr1QeeiBEXNZRJYwQbqp4Cvkso Qjv4u0grDYKbx9Xz/aUWKBbOSaLI4Bc0MIv4daelSETymYEMg+/s1hOMfpRO5OVmgAy/ Hb0VVH4QQVIu6+k/PIqPEhTi687kFdYycz/DjOMf1hUXxajCvhV1kNDjlgzh0PI3kqlZ PDNNVWXnY9o/kNazmIWRTGEJJO1Nrts1NpYdPBjyutUQQwT5W0Lz3A4aNfGDWa0dkAkv xJ6uxubXVI+NGAlPqG5qrQyfWiPAmVTVKE8cZlS4MTuqWuS5Sn4GGtkpyjBF21VIa1Hx MgMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705313476; x=1705918276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FKR76xvkppExc7Ae5ic+6mPrVpT9dqve2Cn1Oe/qHYw=; b=eC1EHGd3Z8LG0cxwqFix/Z3P5yYxWUvnGJqGzcGNclMwWzoJxkDzSsRHnXm28WaBro sp22lHtDaPLei8MDVNIRMgWvn+KJplSH7Omd406T1rIR5p3FSUI6zj8S3BwSlMouxZkl uWCBg04yJ3k3rQhjkwtGQ73s0SL6ezYqjNostq0L8j5uH+jOfwimKWwxeNAOtV4G4+tQ LxYgkqacR8OvDNg1BIdC1TwJi6gTR2z79WGi8xojibiWzevYNkkDuEIQowjTdBO3kEXg nrvjj90QIgvbc+L2yMc4v4Yun9D6AxB703CiYBaWRV9SI9o/lh2cVQr9aMpCXHWROC6x cFTQ== X-Gm-Message-State: AOJu0YymFcGQMw9TGyqRyA30h4B1LXGHhuGE/7jc5+EsT5OEtjzEuEBv NoxfmRloV4kewCwm4BPSLVM6WK6uUgkq5Q== X-Google-Smtp-Source: AGHT+IGWojS8RsJT/iDe5Ctvj5HBEJFzGZS/l46ZI7pdhdk1JBFy+CjL4CsRK1CYjAHvPpRJ4by1hw== X-Received: by 2002:a05:6808:152b:b0:3bb:edf8:c497 with SMTP id u43-20020a056808152b00b003bbedf8c497mr7585343oiw.71.1705313476617; Mon, 15 Jan 2024 02:11:16 -0800 (PST) Received: from localhost.localdomain ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id u5-20020aa78385000000b006d9b8572e77sm7348256pfm.120.2024.01.15.02.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 02:11:16 -0800 (PST) From: Sunil V L To: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: "Rafael J . Wysocki" , Len Brown , Anup Patel , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Andrew Jones , Atish Kumar Patra , Pavel Machek , Sunil V L Subject: [PATCH v2 -next 2/3] ACPI: RISC-V: Add LPI driver Date: Mon, 15 Jan 2024 15:40:55 +0530 Message-Id: <20240115101056.429471-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115101056.429471-1-sunilvl@ventanamicro.com> References: <20240115101056.429471-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable Low Power Idle (LPI) based cpuidle driver for RISC-V platforms. It depends on SBI HSM calls for idle state transitions. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- drivers/acpi/riscv/Makefile | 3 +- drivers/acpi/riscv/cpuidle.c | 81 ++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/cpuidle.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b3b126e0b94..7309d92dd477 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o +obj-y +=3D rhct.o +obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o diff --git a/drivers/acpi/riscv/cpuidle.c b/drivers/acpi/riscv/cpuidle.c new file mode 100644 index 000000000000..052ec3942902 --- /dev/null +++ b/drivers/acpi/riscv/cpuidle.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RISCV_FFH_LPI_TYPE_MASK GENMASK_ULL(63, 60) +#define RISCV_FFH_LPI_RSVD_MASK GENMASK_ULL(59, 32) + +#define RISCV_FFH_LPI_TYPE_SBI BIT_ULL(60) + +static int acpi_cpu_init_idle(unsigned int cpu) +{ + int i; + struct acpi_lpi_state *lpi; + struct acpi_processor *pr =3D per_cpu(processors, cpu); + + if (unlikely(!pr || !pr->flags.has_lpi)) + return -EINVAL; + + if (!is_sbi_hsm_supported()) + return -ENODEV; + + if (pr->power.count <=3D 1) + return -ENODEV; + + for (i =3D 1; i < pr->power.count; i++) { + u32 state; + + lpi =3D &pr->power.lpi_states[i]; + + /* + * Validate Entry Method as per FFH spec. + * bits[63:60] should be 0x1 + * bits[59:32] should be 0x0 + * bits[31:0] represent a SBI power_state + */ + if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) !=3D RISCV_FFH_LPI_TYPE_SB= I) || + (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) { + pr_warn("Invalid LPI entry method %#llx\n", lpi->address); + return -EINVAL; + } + + state =3D lpi->address; + if (!sbi_suspend_state_is_valid(state)) { + pr_warn("Invalid SBI power state %#x\n", state); + return -EINVAL; + } + } + + return 0; +} + +int acpi_processor_ffh_lpi_probe(unsigned int cpu) +{ + return acpi_cpu_init_idle(cpu); +} + +int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) +{ + u32 state =3D lpi->address; + + if (state & SBI_HSM_SUSP_NON_RET_BIT) + return CPU_PM_CPU_IDLE_ENTER_PARAM(sbi_suspend, + lpi->index, + state); + else + return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(sbi_suspend, + lpi->index, + state); +} --=20 2.34.1 From nobody Thu Dec 25 16:01:46 2025 Received: from mail-oo1-f53.google.com (mail-oo1-f53.google.com [209.85.161.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B782C684 for ; Mon, 15 Jan 2024 10:11:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="bZKZ5RwK" Received: by mail-oo1-f53.google.com with SMTP id 006d021491bc7-59612e4a21eso2759712eaf.3 for ; Mon, 15 Jan 2024 02:11:22 -0800 (PST) DKIM-Signature: v=1; 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Mon, 15 Jan 2024 02:11:21 -0800 (PST) Received: from localhost.localdomain ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id u5-20020aa78385000000b006d9b8572e77sm7348256pfm.120.2024.01.15.02.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 02:11:20 -0800 (PST) From: Sunil V L To: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org Cc: "Rafael J . Wysocki" , Len Brown , Anup Patel , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Andrew Jones , Atish Kumar Patra , Pavel Machek , Sunil V L Subject: [PATCH v2 -next 3/3] ACPI: Enable ACPI_PROCESSOR for RISC-V Date: Mon, 15 Jan 2024 15:40:56 +0530 Message-Id: <20240115101056.429471-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115101056.429471-1-sunilvl@ventanamicro.com> References: <20240115101056.429471-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ACPI processor driver is not currently enabled for RISC-V. This is required to enable CPU related functionalities like LPI and CPPC. Hence, enable ACPI_PROCESSOR for RISC-V. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- drivers/acpi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index f819e760ff19..9a920752171c 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -282,7 +282,7 @@ config ACPI_CPPC_LIB =20 config ACPI_PROCESSOR tristate "Processor" - depends on X86 || ARM64 || LOONGARCH + depends on X86 || ARM64 || LOONGARCH || RISCV select ACPI_PROCESSOR_IDLE select ACPI_CPU_FREQ_PSS if X86 || LOONGARCH select THERMAL --=20 2.34.1