From nobody Fri Sep 20 06:34:24 2024 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6CD41B971; Sat, 13 Jan 2024 10:26:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="bbCpXq0a" Received: by mail.gandi.net (Postfix) with ESMTPSA id EDA8160007; Sat, 13 Jan 2024 10:26:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1705141575; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=woi1aJhgxN/YqRBXLbFxEW/CiZM+RsFUK1nA6ZMsXGU=; b=bbCpXq0aUsb3NuYrqWDV1IQwcgJcAAHxx0ndZBah+bDvllmtXSLv2XNSey98h9TnNVjPo3 PjQZ2bHowg53uBegrDI0wVT9FuXR+IswAd7dK80hUA4eyfv6GK2UvbBmqMgPJhDfu+/0f+ iYa0cM0up+fQPfNwVn5CHZaZMYQqrBFpd8CSnzjqt7n4zJyJlgOJavTVqFAQOyA6BKZsAx l3PPs2RoysC+3/grWaXZndJfkFkSd+zIBOaq1bIR++ZMwaSKD1d0aqx5IJ9/H3wMo2hjxp OpwQQrOmPKzUbnfcisRkcKHa/NQqfOS+hrBOqj5/VKpzGbwJ6QY4OqQec040/A== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com, Luiz Angelo Daros de Luca , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 7/8] net: dsa: mt7530: correct port capabilities of MT7988 Date: Sat, 13 Jan 2024 13:25:28 +0300 Message-Id: <20240113102529.80371-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240113102529.80371-1-arinc.unal@arinc9.com> References: <20240113102529.80371-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3. Set the internal phy cases to '0 ... 3'. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 3a02308763ca..e7e7e89d8eca 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2562,7 +2562,7 @@ static void mt7988_mac_port_get_caps(struct dsa_switc= h *ds, int port, =20 switch (port) { /* Internal PHY */ - case 0 ... 4: + case 0 ... 3: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; --=20 2.40.1