From nobody Thu Dec 25 23:24:30 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87E8215E95; Thu, 11 Jan 2024 10:43:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="sC1KaRxS" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40B9LK7c002030; Thu, 11 Jan 2024 11:42:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Zzq4sr5HL0Ty2CrxFtUdwdQvorVCV4080Uc+mKEc8cQ=; b=sC 1KaRxS/B3SJBzu+DZ9IBA1mOSrrtCsf4TaAQhDy8yRKeD9bRA4rse+XK2GDWBnfa HW134c4e2AfsOdoRAPeL3zyByCW24GwC9PuMEZoEb94pyFS5R7RnxpGvHqUgRYov tmBHGUabNh9Nl8vydGoR15LuTDJTkomk9riJwCm4zoZHz37jv8/t7/CDOa81Nh8+ HBeo4r4wMVUFCCVoTvP0OKV7VCA645H7UHJWlfFrH5JZm5NkXLNu5qOWNW39YIGG K2n2w4vfVBXL2/GQ+wptfJqcmMxSOnmW3f0Vo0jl4Vtqa9WZptgsYrVycMSDiCl8 xtzSVSTk0xWmPIVERLkg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vexmfmmax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Jan 2024 11:42:31 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6491B100049; Thu, 11 Jan 2024 11:42:31 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5C483231507; Thu, 11 Jan 2024 11:42:31 +0100 (CET) Received: from localhost (10.252.29.122) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 11 Jan 2024 11:42:30 +0100 From: Raphael Gallais-Pou To: Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel CC: , , , , Subject: [PATCH v2 5/6] arm64: dts: st: add lvds support on stm32mp255 Date: Thu, 11 Jan 2024 11:40:48 +0100 Message-ID: <20240111104049.38695-6-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240111104049.38695-1-raphael.gallais-pou@foss.st.com> References: <20240111104049.38695-1-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" This patch adds LVDS support on stm32mp255. The LVDS is used on STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC input clock. Signed-off-by: Raphael Gallais-Pou --- Changes in v2: - Move patch to stm32mp255.dtsi after internal discussions --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index e6fa596211f5..ac46a7dbed2d 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -7,3 +7,20 @@ =20 / { }; + +<dc { + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>; + clock-names =3D "bus", "lcd", "lvds"; +}; + +&rifsc { + lvds: lvds@48060000 { + #clock-cells =3D <0>; + compatible =3D "st,stm32-lvds"; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + status =3D "disabled"; + }; +}; --=20 2.25.1