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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id d14-20020a170906c20e00b00a298e2f6b3csm407179ejz.213.2024.01.11.02.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 02:39:36 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Arnd Bergmann , Olof Johansson , Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Golle , Hsin-Yi Wang , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , jason-ch chen , Macpaul Lin , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, soc@kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Conor Dooley Subject: [PATCH V2 1/2] dt-bindings: arm64: mediatek: Add MT7981B and Xiaomi AX3000T Date: Thu, 11 Jan 2024 11:39:27 +0100 Message-Id: <20240111103928.721-2-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240111103928.721-1-zajec5@gmail.com> References: <20240111103928.721-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki MT7981B (AKA Filogic 820) is MediaTek's dual-core ARM Cortex-A53 SoC. One of market devices using this SoC is Xiaomi AX3000T. Signed-off-by: Rafa=C5=82 Mi=C5=82ecki Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 92dbfb862757..12cf02b30967 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -82,6 +82,10 @@ properties: - enum: - mediatek,mt7629-rfb - const: mediatek,mt7629 + - items: + - enum: + - xiaomi,ax3000t + - const: mediatek,mt7981b - items: - enum: - bananapi,bpi-r3 --=20 2.35.3 From nobody Fri Sep 20 04:07:13 2024 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF1AC14F89; Thu, 11 Jan 2024 10:39:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iRl1AhQO" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-5588a83e0d0so633480a12.3; Thu, 11 Jan 2024 02:39:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704969580; x=1705574380; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zVgpAQw5lxERHkBicfugIDRBRVx5HBt1tQZLZuFr6Ec=; b=iRl1AhQOUm2eRYMzIRo4dic80Ng9Hz5nVX3h78/w0WqVsJt56Fi60sgEjWF0wW3IiC nc60n7Ljw2Mb7/qS2b5nG8kMWHQVHNwlJgNTIY+wCYnhwB+TxuLMFH0I94yJlIeV12WA DtNPBdfkaFO0zhxjaCaQ2vDdHX8bisj66/Yig2N+jPPeDATUBOf9mIzkQUOk0/8RucVC uclw2qTKIzegc4YhBz1h15teYK9Lf0PyHDeNXNAtDS+ejp/wuUkr8pfryz0l1uvLZqKG J4IFYpwxgn3A1JMdIkJMKriS8ZuZkh5ghYLibbNCBZBf283q6Jv4ZEhcH8AfQTrLMFHW E8VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704969580; x=1705574380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zVgpAQw5lxERHkBicfugIDRBRVx5HBt1tQZLZuFr6Ec=; b=D9B6RIgwztwDdlaGvyz2PI9DMBShoAmee/w4h5p60faDGlfGrO4sOB1umwZNL39z6X xSkd3zuxzzQ22KwtKU7dtI1S5hGsK8ZCOerig//UrU65ABbab1cOsk8jp2FEoIyWT2+L DFAaSGm3bnjhntcPE1qGURzBJ6rJ+9V7cODdv0ISKzndjtrM7OGOVgOXlf8WlsODPgV1 0t09wmcmRhwsvae1ne9SIH6s8l9t7SnPi6AWh7YehExV4vNC6QuDF5gKLNTkoffnFdce 99QmLAMnKWMdir8J0hpLCfjqAJ74OZB5zn3Bdo8y6zCyjBnRLHGWIicG57IU7AmgHXpw spKw== X-Gm-Message-State: AOJu0YxxoA5w4OlJ7/TGgw0yoYuiezzf+PZ6QoD7QGvSP/zgyf34WLUK GdORPsJYal3HsrzTns0tsjA= X-Google-Smtp-Source: AGHT+IGCI51BT0950v+o0UYQLAUBlFB/Hr7Uxq7pBrhSwMwN7fwM/Q56+vSPKOF47X5RNjaJJco2wg== X-Received: by 2002:a17:906:a28f:b0:a28:b170:5504 with SMTP id i15-20020a170906a28f00b00a28b1705504mr454038ejz.76.1704969579904; Thu, 11 Jan 2024 02:39:39 -0800 (PST) Received: from localhost.lan (031011218106.poznan.vectranet.pl. [31.11.218.106]) by smtp.gmail.com with ESMTPSA id d14-20020a170906c20e00b00a298e2f6b3csm407179ejz.213.2024.01.11.02.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 02:39:39 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Arnd Bergmann , Olof Johansson , Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Golle , Hsin-Yi Wang , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , jason-ch chen , Macpaul Lin , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, soc@kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH V2 2/2] arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T Date: Thu, 11 Jan 2024 11:39:28 +0100 Message-Id: <20240111103928.721-3-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240111103928.721-1-zajec5@gmail.com> References: <20240111103928.721-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki MT7981B (AKA MediaTek Filogic 820) is a dual-core ARM Cortex-A53 SoC. One of market devices using this SoC is Xiaomi AX3000T. This is initial contribution with basic SoC support. More hardware block will get added later. Some will need their bindings (like auxadc). Signed-off-by: Rafa=C5=82 Mi=C5=82ecki Reviewed-by: AngeloGioacchino Del Regno --- V2: Fix psci version Fix gic regs arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt7981b-xiaomi-ax3000t.dts | 15 +++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 105 ++++++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 0a189d5d8006..8bff11acfe1f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-nand.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts b/arch= /arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts new file mode 100644 index 000000000000..a314c3e05e50 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-xiaomi-ax3000t.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible =3D "xiaomi,ax3000t", "mediatek,mt7981b"; + model =3D "Xiaomi AX3000T"; + + memory@40000000 { + reg =3D <0 0x40000000 0 0x10000000>; + device_type =3D "memory"; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7981b.dtsi new file mode 100644 index 000000000000..4feff3d1c5f4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include +#include + +/ { + compatible =3D "mediatek,mt7981b"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + }; + + oscillator-40m { + compatible =3D "fixed-clock"; + clock-frequency =3D <40000000>; + clock-output-names =3D "clkxtal"; + #clock-cells =3D <0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>; /* GICR */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + infracfg: clock-controller@10001000 { + compatible =3D "mediatek,mt7981-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1001b000 { + compatible =3D "mediatek,mt7981-topckgen", "syscon"; + reg =3D <0 0x1001b000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1001e000 { + compatible =3D "mediatek,mt7981-apmixedsys"; + reg =3D <0 0x1001e000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pwm@10048000 { + compatible =3D "mediatek,mt7981-pwm"; + reg =3D <0 0x10048000 0 0x1000>; + clocks =3D <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + #pwm-cells =3D <2>; + }; + + clock-controller@15000000 { + compatible =3D "mediatek,mt7981-ethsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.35.3