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Thu, 11 Jan 2024 02:15:12 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:55f:21e0:9e19:4376:dea6:dbfa]) by smtp.gmail.com with ESMTPSA id j7-20020a05600c190700b0040e52cac976sm5157758wmq.29.2024.01.11.02.15.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 02:15:12 -0800 (PST) From: Julien Stephan To: Cc: Florian Sylvestre , Julien Stephan , Rob Herring , Andy Hsieh , AngeloGioacchino Del Regno , Chunfeng Yun , Chun-Kuang Hu , Conor Dooley , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Matthias Brugger , Philipp Zabel , Rob Herring , Vinod Koul Subject: [PATCH v5 1/2] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 Date: Thu, 11 Jan 2024 11:14:50 +0100 Message-ID: <20240111101504.468169-2-jstephan@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240111101504.468169-1-jstephan@baylibre.com> References: <20240111101504.468169-1-jstephan@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Florian Sylvestre This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in some Mediatek soc, such as the mt8365 Signed-off-by: Florian Sylvestre Signed-off-by: Julien Stephan Reviewed-by: Rob Herring --- .../bindings/phy/mediatek,mt8365-csi-rx.yaml | 79 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-c= si-rx.yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.y= aml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml new file mode 100644 index 000000000000..2127a5732f73 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Sensor Interface MIPI CSI CD-PHY + +maintainers: + - Julien Stephan + - Andy Hsieh + +description: + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2 + receivers. The number of PHYs depends on the SoC model. + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only + capable. + +properties: + compatible: + enum: + - mediatek,mt8365-csi-rx + + reg: + maxItems: 1 + + num-lanes: + enum: [2, 3, 4] + + '#phy-cells': + enum: [0, 1] + description: | + If the PHY doesn't support mode selection then #phy-cells must be 0 = and + PHY mode is described using phy-type property. + If the PHY supports mode selection, then #phy-cells must be 1 and mo= de + is set in the PHY cells. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + phy-type: + description: + If the PHY doesn't support mode selection then this set the operatin= g mode. + See include/dt-bindings/phy/phy.h for constants. + const: 10 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - num-lanes + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + csi0_rx: phy@11c10000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c10000 0 0x2000>; + num-lanes =3D <2>; + #phy-cells =3D <1>; + }; + + csi1_rx: phy@11c12000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c12000 0 0x2000>; + phy-type =3D ; + num-lanes =3D <2>; + #phy-cells =3D <0>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index cc92b10a4cad..37dfa99b0eb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13569,6 +13569,12 @@ F: Documentation/devicetree/bindings/media/mediate= k-vpu.txt F: drivers/media/platform/mediatek/vcodec/ F: drivers/media/platform/mediatek/vpu/ =20 +MEDIATEK MIPI-CSI CDPHY DRIVER +M: Julien Stephan +M: Andy Hsieh +S: Supported +F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml + MEDIATEK MMC/SD/SDIO DRIVER M: Chaotian Jing S: Maintained --=20 2.43.0