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Thu, 11 Jan 2024 17:19:28 +0800 (CST) From: XueBing Chen To: daniel@ffwll.ch, Xinhui.Pan@amd.com, alexander.deucher@amd.com, airlied@gmail.com, christian.koenig@amd.com Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, XueBing Chen Subject: [PATCH] drm/radeon: Clean up errors in atombios.h Date: Thu, 11 Jan 2024 09:19:27 +0000 Message-Id: <20240111091927.13653-1-chenxb_99091@126.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: _____wD3v+6gsp9lfGWlAA--.23421S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfJr48trWrAF18Kw1xGry8Xwb_yoW8Wr4fXo W7GF9xJr47Gw15Jr4Utry8ta45KrsIqw1UGr13Gryj9rWDGr1DJr1DA3WUJr1fKF17Zw1D Zry2q34DXry8A3W5n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RRJPiDUUUU X-CM-SenderInfo: hfkh05lebzmiizr6ij2wof0z/1tbiGAFixWVLZWkxpgAAsL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: space required after that close brace '}' Signed-off-by: XueBing Chen --- drivers/gpu/drm/radeon/atombios.h | 135 ++++++++++++------------------ 1 file changed, 54 insertions(+), 81 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/ato= mbios.h index 2db40789235c..141dc17ba632 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -197,19 +197,17 @@ Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.=20 And the pointer actually points to this header. */ =20 -typedef struct _ATOM_COMMON_TABLE_HEADER -{ +typedef struct _ATOM_COMMON_TABLE_HEADER { USHORT usStructureSize; UCHAR ucTableFormatRevision; /*Change it when the Parser is not backw= ard compatible */ UCHAR ucTableContentRevision; /*Change it only when the table needs to= change but the firmware */ /*Image can't be updated, while Driver n= eeds to carry the new table! */ -}ATOM_COMMON_TABLE_HEADER; +} ATOM_COMMON_TABLE_HEADER; =20 /*************************************************************************= ***/=09 // Structure stores the ROM header. /*************************************************************************= ***/=09 -typedef struct _ATOM_ROM_HEADER -{ +typedef struct _ATOM_ROM_HEADER { ATOM_COMMON_TABLE_HEADER sHeader; UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Ato= mbios and non-atombios,=20 atombios should init it as "ATOM", d= on't change the position */ @@ -228,7 +226,7 @@ typedef struct _ATOM_ROM_HEADER USHORT usMasterDataTableOffset; /*Offset for SW to get all data table = offsets, Don't change the position */ UCHAR ucExtendedFunctionCode; UCHAR ucReserved; -}ATOM_ROM_HEADER; +} ATOM_ROM_HEADER; =20 /*=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3DCommand Table Portion=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 @@ -342,17 +340,15 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ #define LCD1OutputControl HW_Misc_Operation #define TV1OutputControl Gfx_Harvesting =20 -typedef struct _ATOM_MASTER_COMMAND_TABLE -{ +typedef struct _ATOM_MASTER_COMMAND_TABLE { ATOM_COMMON_TABLE_HEADER sHeader; ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; -}ATOM_MASTER_COMMAND_TABLE; +} ATOM_MASTER_COMMAND_TABLE; =20 /*************************************************************************= ***/=09 // Structures used in every command table /*************************************************************************= ***/=09 -typedef struct _ATOM_TABLE_ATTRIBUTE -{ +typedef struct _ATOM_TABLE_ATTRIBUTE { #if ATOM_BIG_ENDIAN USHORT UpdatedByUtility:1; //[15]=3DTable updated by utility fl= ag USHORT PS_SizeInBytes:7; //[14:8]=3DSize of parameter space i= n Bytes (multiple of a dword),=20 @@ -362,24 +358,22 @@ typedef struct _ATOM_TABLE_ATTRIBUTE USHORT PS_SizeInBytes:7; //[14:8]=3DSize of parameter space i= n Bytes (multiple of a dword),=20 USHORT UpdatedByUtility:1; //[15]=3DTable updated by utility fl= ag #endif -}ATOM_TABLE_ATTRIBUTE; +} ATOM_TABLE_ATTRIBUTE; =20 -typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS -{ +typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS { ATOM_TABLE_ATTRIBUTE sbfAccess; USHORT susAccess; -}ATOM_TABLE_ATTRIBUTE_ACCESS; +} ATOM_TABLE_ATTRIBUTE_ACCESS; =20 /*************************************************************************= ***/=09 // Common header for all command tables. // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common heade= r.=20 // And the pointer actually points to this header. /*************************************************************************= ***/=09 -typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER -{ +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { ATOM_COMMON_TABLE_HEADER CommonHeader; ATOM_TABLE_ATTRIBUTE TableAttribute;=09 -}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; +} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; =20 /*************************************************************************= ***/=09 // Structures used by ComputeMemoryEnginePLLTable @@ -391,8 +385,7 @@ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER /*************************************************************************= ***/=09 // Structures used by AdjustMemoryControllerTable /*************************************************************************= ***/=09 -typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ -{ +typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ { #if ATOM_BIG_ENDIAN ULONG ulPointerReturnFlag:1; // BYTE_3[7]=3D1 - Return the pointer = to the right Data Block; BYTE_3[7]=3D0 - Program the right Data Block=20 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] @@ -402,25 +395,23 @@ typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] ULONG ulPointerReturnFlag:1; // BYTE_3[7]=3D1 - Return the pointer = to the right Data Block; BYTE_3[7]=3D0 - Program the right Data Block=20 #endif -}ATOM_ADJUST_MEMORY_CLOCK_FREQ; +} ATOM_ADJUST_MEMORY_CLOCK_FREQ; #define POINTER_RETURN_FLAG 0x80 =20 -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS -{ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { ULONG ulClock; //When returen, it's the re-calculated clock bas= ed on given Fb_div Post_Div and ref_div UCHAR ucAction; //0:reserved //1:Memory //2:Engine =20 UCHAR ucReserved; //may expand to return larger Fbdiv later UCHAR ucFbDiv; //return value UCHAR ucPostDiv; //return value -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; =20 -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 -{ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { ULONG ulClock; //When return, [23:0] return real clock=20 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COM= PUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register USHORT usFbDiv; //return Feedback value to be written to register UCHAR ucPostDiv; //return post div to be written to register -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMOR= Y_ENGINE_PLL_PARAMETERS =20 =20 @@ -438,8 +429,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both = memory and engine clock change,when set, it means this is 1st time to chang= e clock after ASIC bootup #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memor= y and engine clock change, when set, it means the table will not program SP= LL/MPLL =20 -typedef struct _ATOM_COMPUTE_CLOCK_FREQ -{ +typedef struct _ATOM_COMPUTE_CLOCK_FREQ { #if ATOM_BIG_ENDIAN ULONG ulComputeClockFlag:8; // =3D1: COMPUTE_MEMORY_PLL_= PARAM, =3D2: COMPUTE_ENGINE_PLL_PARAM ULONG ulClockFreq:24; // in unit of 10kHz @@ -447,16 +437,14 @@ typedef struct _ATOM_COMPUTE_CLOCK_FREQ ULONG ulClockFreq:24; // in unit of 10kHz ULONG ulComputeClockFlag:8; // =3D1: COMPUTE_MEMORY_PLL_= PARAM, =3D2: COMPUTE_ENGINE_PLL_PARAM #endif -}ATOM_COMPUTE_CLOCK_FREQ; +} ATOM_COMPUTE_CLOCK_FREQ; =20 -typedef struct _ATOM_S_MPLL_FB_DIVIDER -{ +typedef struct _ATOM_S_MPLL_FB_DIVIDER { USHORT usFbDivFrac; =20 USHORT usFbDiv; =20 -}ATOM_S_MPLL_FB_DIVIDER; +} ATOM_S_MPLL_FB_DIVIDER; =20 -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 -{ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 { union { ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter @@ -467,7 +455,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 UCHAR ucPostDiv; //Output Parameter =20 UCHAR ucCntlFlag; //Output Parameter =20 UCHAR ucReserved; -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; =20 // ucCntlFlag #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 @@ -477,8 +465,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 =20 =20 // V4 are only used for APU which PLL outside GPU -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 -{ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 { #if ATOM_BIG_ENDIAN ULONG ucPostDiv:8; //return parameter: post divider which is use= d to program to register directly ULONG ulClock:24; //Input=3D target clock, output =3D actual cl= ock=20 @@ -486,10 +473,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ULONG ulClock:24; //Input=3D target clock, output =3D actual cl= ock=20 ULONG ucPostDiv:8; //return parameter: post divider which is use= d to program to register directly #endif -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; =20 -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 -{ +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 { union { ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter @@ -504,29 +490,27 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_= V5 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0= ] - Strobe(1)/Performance(0) mode }; UCHAR ucReserved; =20 -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; +} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; =20 =20 -typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 -{ +typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 { ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter ULONG ulReserved[2]; -}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; +} COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; =20 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 =20 -typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 -{ +typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 { COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Param= eter: ucPostDiv=3DDFS divider ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB div= ider UCHAR ucPllRefDiv; //Output Parameter: PLL ref di= vider =20 UCHAR ucPllPostDiv; //Output Parameter: PLL post d= ivider =20 UCHAR ucPllCntlFlag; //Output Flags: control flag UCHAR ucReserved; =20 -}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; +} COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; =20 //ucPllCntlFlag #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03=20 @@ -536,8 +520,7 @@ typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-Per= formanceMode =20 // use for ComputeMemoryClockParamTable -typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 -{ +typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 { union { ULONG ulClock; =20 @@ -550,7 +533,7 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V= 2_1 UCHAR ucPllCntlFlag; //Output:=20 }; UCHAR ucBWCntl; =20 -}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; +} COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; =20 // definition of ucInputFlag #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 @@ -563,81 +546,71 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS= _V2_1 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 =20 -typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER -{ +typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { ATOM_COMPUTE_CLOCK_FREQ ulClock; ULONG ulReserved[2]; -}DYNAMICE_MEMORY_SETTINGS_PARAMETER; +} DYNAMICE_MEMORY_SETTINGS_PARAMETER; =20 -typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER -{ +typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { ATOM_COMPUTE_CLOCK_FREQ ulClock; ULONG ulMemoryClock; ULONG ulReserved; -}DYNAMICE_ENGINE_SETTINGS_PARAMETER; +} DYNAMICE_ENGINE_SETTINGS_PARAMETER; =20 /*************************************************************************= ***/=09 // Structures used by SetEngineClockTable /*************************************************************************= ***/=09 -typedef struct _SET_ENGINE_CLOCK_PARAMETERS -{ +typedef struct _SET_ENGINE_CLOCK_PARAMETERS { ULONG ulTargetEngineClock; //In 10Khz unit -}SET_ENGINE_CLOCK_PARAMETERS; +} SET_ENGINE_CLOCK_PARAMETERS; =20 -typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION -{ +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION { ULONG ulTargetEngineClock; //In 10Khz unit COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_ENGINE_CLOCK_PS_ALLOCATION; +} SET_ENGINE_CLOCK_PS_ALLOCATION; =20 /*************************************************************************= ***/=09 // Structures used by SetMemoryClockTable /*************************************************************************= ***/=09 -typedef struct _SET_MEMORY_CLOCK_PARAMETERS -{ +typedef struct _SET_MEMORY_CLOCK_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit -}SET_MEMORY_CLOCK_PARAMETERS; +} SET_MEMORY_CLOCK_PARAMETERS; =20 -typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION -{ +typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION { ULONG ulTargetMemoryClock; //In 10Khz unit COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_MEMORY_CLOCK_PS_ALLOCATION; +} SET_MEMORY_CLOCK_PS_ALLOCATION; =20 /*************************************************************************= ***/=09 // Structures used by ASIC_Init.ctb /*************************************************************************= ***/=09 -typedef struct _ASIC_INIT_PARAMETERS -{ +typedef struct _ASIC_INIT_PARAMETERS { ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit -}ASIC_INIT_PARAMETERS; +} ASIC_INIT_PARAMETERS; =20 -typedef struct _ASIC_INIT_PS_ALLOCATION -{ +typedef struct _ASIC_INIT_PS_ALLOCATION { ASIC_INIT_PARAMETERS sASICInitClocks; SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init = this structure -}ASIC_INIT_PS_ALLOCATION; +} ASIC_INIT_PS_ALLOCATION; =20 /*************************************************************************= ***/=09 // Structure used by DynamicClockGatingTable.ctb /*************************************************************************= ***/=09 -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS=20 -{ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[3]; -}DYNAMIC_CLOCK_GATING_PARAMETERS; +} DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETE= RS =20 /*************************************************************************= ***/=09 // Structure used by EnableDispPowerGatingTable.ctb /*************************************************************************= ***/=09 -typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1=20 -{ +typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 { UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[2]; -}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; +} ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; =20 /*************************************************************************= ***/=09 // Structure used by EnableASIC_StaticPwrMgtTable.ctb --=20 2.17.1