From nobody Thu Dec 25 21:52:04 2025 Received: from m16.mail.163.com (m15.mail.163.com [45.254.50.220]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACECFDDA6 for ; Thu, 11 Jan 2024 07:59:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="m2qMZ9WY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id; bh=CtQllylb5rBy8xA4pm EMdjJuK4Xkx/RYOeVF0Un8bi0=; b=m2qMZ9WYQ8y6fIYNLa6VLyMFQzYCv7a1JA M5R28m+zOSwNChTRuDX4zFhOxLguxNytXtYDsquX5j2tDfCznoRYucaNjbiqudDj cR1zPgGMCxUGUz2lybSoBWfeEWrFBAKEkIEPIcCqxohEIOPWNCMwlGJnyyL8LCT3 0GuXKLiIs= Received: from localhost.localdomain (unknown [182.148.14.173]) by gzga-smtp-mta-g0-1 (Coremail) with SMTP id _____wDH9wPAn59lXj0QAA--.3875S2; Thu, 11 Jan 2024 15:58:56 +0800 (CST) From: GuoHua Chen To: daniel@ffwll.ch, Xinhui.Pan@amd.com, airlied@gmail.com, christian.koenig@amd.com, alexander.deucher@amd.com Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, GuoHua Chen Subject: [PATCH] drm/radeon: Clean up errors in smu7_discrete.h Date: Thu, 11 Jan 2024 07:58:54 +0000 Message-Id: <20240111075854.11116-1-chenguohua_716@163.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: _____wDH9wPAn59lXj0QAA--.3875S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxKw4fur17XrWfKr17Zr13urg_yoW7CryUpF WUKw4IgFZ5Ar13W345AwsYvr4agry5tr1UGr9ruw4Fqw42yrW2kF12ka1UCrWaqws3C393 JFsxtF12grWxAFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UwFxUUUUUU= X-CM-SenderInfo: xfkh0w5xrk3tbbxrlqqrwthudrp/xtbBEBRi1mVOBk7vVQABso Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: GuoHua Chen --- drivers/gpu/drm/radeon/smu7_discrete.h | 51 +++++++++----------------- 1 file changed, 17 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/radeon/smu7_discrete.h b/drivers/gpu/drm/radeo= n/smu7_discrete.h index 0b0b404ff091..1f63cbbd6515 100644 --- a/drivers/gpu/drm/radeon/smu7_discrete.h +++ b/drivers/gpu/drm/radeon/smu7_discrete.h @@ -35,8 +35,7 @@ #define SMU7_NUM_GPU_TES 1 #define SMU7_NUM_NON_TES 2 =20 -struct SMU7_SoftRegisters -{ +struct SMU7_SoftRegisters { uint32_t RefClockFrequency; uint32_t PmTimerP; uint32_t FeatureEnables; @@ -89,8 +88,7 @@ struct SMU7_SoftRegisters =20 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; =20 -struct SMU7_Discrete_VoltageLevel -{ +struct SMU7_Discrete_VoltageLevel { uint16_t Voltage; uint16_t StdVoltageHiSidd; uint16_t StdVoltageLoSidd; @@ -100,8 +98,7 @@ struct SMU7_Discrete_VoltageLevel =20 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; =20 -struct SMU7_Discrete_GraphicsLevel -{ +struct SMU7_Discrete_GraphicsLevel { uint32_t Flags; uint32_t MinVddc; uint32_t MinVddcPhases; @@ -131,8 +128,7 @@ struct SMU7_Discrete_GraphicsLevel =20 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; =20 -struct SMU7_Discrete_ACPILevel -{ +struct SMU7_Discrete_ACPILevel { uint32_t Flags; uint32_t MinVddc; uint32_t MinVddcPhases; @@ -153,8 +149,7 @@ struct SMU7_Discrete_ACPILevel =20 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; =20 -struct SMU7_Discrete_Ulv -{ +struct SMU7_Discrete_Ulv { uint32_t CcPwrDynRm; uint32_t CcPwrDynRm1; uint16_t VddcOffset; @@ -165,8 +160,7 @@ struct SMU7_Discrete_Ulv =20 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; =20 -struct SMU7_Discrete_MemoryLevel -{ +struct SMU7_Discrete_MemoryLevel { uint32_t MinVddc; uint32_t MinVddcPhases; uint32_t MinVddci; @@ -206,8 +200,7 @@ struct SMU7_Discrete_MemoryLevel =20 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; =20 -struct SMU7_Discrete_LinkLevel -{ +struct SMU7_Discrete_LinkLevel { uint8_t PcieGenSpeed; uint8_t PcieLaneCount; uint8_t EnabledForActivity; @@ -220,8 +213,7 @@ struct SMU7_Discrete_LinkLevel typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; =20 =20 -struct SMU7_Discrete_MCArbDramTimingTableEntry -{ +struct SMU7_Discrete_MCArbDramTimingTableEntry { uint32_t McArbDramTiming; uint32_t McArbDramTiming2; uint8_t McArbBurstTime; @@ -230,15 +222,13 @@ struct SMU7_Discrete_MCArbDramTimingTableEntry =20 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArb= DramTimingTableEntry; =20 -struct SMU7_Discrete_MCArbDramTimingTable -{ +struct SMU7_Discrete_MCArbDramTimingTable { SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STAT= E][SMU__NUM_MCLK_DPM_LEVELS]; }; =20 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramT= imingTable; =20 -struct SMU7_Discrete_UvdLevel -{ +struct SMU7_Discrete_UvdLevel { uint32_t VclkFrequency; uint32_t DclkFrequency; uint16_t MinVddc; @@ -250,8 +240,7 @@ struct SMU7_Discrete_UvdLevel =20 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; =20 -struct SMU7_Discrete_ExtClkLevel -{ +struct SMU7_Discrete_ExtClkLevel { uint32_t Frequency; uint16_t MinVoltage; uint8_t MinPhases; @@ -260,8 +249,7 @@ struct SMU7_Discrete_ExtClkLevel =20 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; =20 -struct SMU7_Discrete_StateInfo -{ +struct SMU7_Discrete_StateInfo { uint32_t SclkFrequency; uint32_t MclkFrequency; uint32_t VclkFrequency; @@ -285,8 +273,7 @@ struct SMU7_Discrete_StateInfo typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; =20 =20 -struct SMU7_Discrete_DpmTable -{ +struct SMU7_Discrete_DpmTable { SMU7_PIDController GraphicsPIDController; SMU7_PIDController MemoryPIDController; SMU7_PIDController LinkPIDController; @@ -406,23 +393,20 @@ typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_D= pmTable; #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY =20 -struct SMU7_Discrete_MCRegisterAddress -{ +struct SMU7_Discrete_MCRegisterAddress { uint16_t s0; uint16_t s1; }; =20 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAdd= ress; =20 -struct SMU7_Discrete_MCRegisterSet -{ +struct SMU7_Discrete_MCRegisterSet { uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; }; =20 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; =20 -struct SMU7_Discrete_MCRegisters -{ +struct SMU7_Discrete_MCRegisters { uint8_t last; uint8_t reserved[3]; SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_= ARRAY_SIZE]; @@ -431,8 +415,7 @@ struct SMU7_Discrete_MCRegisters =20 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; =20 -struct SMU7_Discrete_FanTable -{ +struct SMU7_Discrete_FanTable { uint16_t FdoMode; int16_t TempMin; int16_t TempMed; --=20 2.17.1