From nobody Fri Dec 26 05:27:48 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 716033FB36; Wed, 10 Jan 2024 10:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jFgJZZ2G" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1704882394; x=1736418394; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PalD82ak/I8XOLyg3wSse6AzSuqcL6BJlR3VoACVMNM=; b=jFgJZZ2GqR5KkOPU/M8YNeGRAnoruoEutu6BU8GXKNAp9KANBszYooLp z9bMch6Lz/e4sHUgWafVW0yWQQfFsr7ABGEIkdOvclKh0+/+W0MVldYJ/ +Vo/JwqFv+3UZhXvJ9gjrxwO3i7tm/BFM46fqPYi+Cc89uQDXDDfpX4r2 nGIHD8SdoCdh7epiIb2Qr9uC19E5TByjgU0xkPKphyhDB8+2jbZonDphT wKYD2l3u2nK7Nqu+BE1/nv2XJaL1hUwDVqQq7rcqzyxiLcD8KzkfgA+WH My0BagJ66dL5L5RWaVRYMQHEFd21/vjvhQ3/t1rzi2MbQYFvcjMIGhAK/ g==; X-CSE-ConnectionGUID: 4FLeVdXIRtGRQjBQXLr/AA== X-CSE-MsgGUID: rQWy3AwvQpWYwOWWi+XTOw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="181745211" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jan 2024 03:26:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 10 Jan 2024 03:26:09 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 10 Jan 2024 03:26:01 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , CC: Dharma Balasubiramani Subject: [PATCH 1/3] dt-bindings: display: convert Atmel's HLCDC to DT schema Date: Wed, 10 Jan 2024 15:55:33 +0530 Message-ID: <20240110102535.246177-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110102535.246177-1-dharma.b@microchip.com> References: <20240110102535.246177-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the existing DT binding to DT schema of the Atmel's HLCDC display controller. Signed-off-by: Dharma Balasubiramani --- .../display/atmel/atmel,hlcdc-dc.yaml | 133 ++++++++++++++++++ .../bindings/display/atmel/hlcdc-dc.txt | 75 ---------- 2 files changed, 133 insertions(+), 75 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/atmel/atmel,h= lcdc-dc.yaml delete mode 100644 Documentation/devicetree/bindings/display/atmel/hlcdc-d= c.txt diff --git a/Documentation/devicetree/bindings/display/atmel/atmel,hlcdc-dc= .yaml b/Documentation/devicetree/bindings/display/atmel/atmel,hlcdc-dc.yaml new file mode 100644 index 000000000000..49ef28646c48 --- /dev/null +++ b/Documentation/devicetree/bindings/display/atmel/atmel,hlcdc-dc.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC (High LCD Controller) DRM driver + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: | + Device-Tree bindings for Atmel's HLCDC DRM driver. The Atmel HLCDC Displ= ay + Controller is a subdevice of the HLCDC MFD device. + # See ../../mfd/atmel,hlcdc.yaml for more details. + +properties: + compatible: + const: atmel,hlcdc-display-controller + + pinctrl-names: + const: default + + pinctrl-0: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output endpoint of the controller, connecting the LCD panel signals. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + description: + Endpoint connecting the LCD panel signals. + + properties: + bus-width: + description: | + Any endpoint grandchild node may specify a desired video int= erface according to + ../../media/video-interfaces.yaml, specifically "bus-width" = whose recognized + values are <12>, <16>, <18> and <24>, and override any outpu= t mode selection + heuristic, forcing "rgb444","rgb565", "rgb666" and "rgb888" = respectively. + enum: [ 12, 16, 18, 24 ] + +additionalProperties: false + +required: + - '#address-cells' + - '#size-cells' + - compatible + - pinctrl-names + - pinctrl-0 + - port@0 + +examples: + - | + #include + #include + #include + //Example 1 + hlcdc: hlcdc@f0030000 { + compatible =3D "atmel,sama5d3-hlcdc"; + reg =3D <0xf0030000 0x2000>; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names =3D "periph_clk","sys_clk", "slow_clk"; + + hlcdc-display-controller { + compatible =3D "atmel,hlcdc-display-controller"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + hlcdc_panel_output: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_input>; + }; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible =3D "atmel,hlcdc-pwm"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_pwm>; + #pwm-cells =3D <3>; + }; + }; + - | + //Example 2 With a video interface override to force rgb565 + hlcdc-display-controller { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hlcdc_panel_output2: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_input>; + bus-width =3D <16>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt b= /Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt deleted file mode 100644 index 923aea25344c..000000000000 --- a/Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt +++ /dev/null @@ -1,75 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver - -The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. -See ../../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be "atmel,hlcdc-display-controller" - - pinctrl-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the default pinctrl states. - - #address-cells: should be set to 1. - - #size-cells: should be set to 0. - -Required children nodes: - Children nodes are encoding available output ports and their connections - to external devices using the OF graph representation (see ../graph.txt). - At least one port node is required. - -Optional properties in grandchild nodes: - Any endpoint grandchild node may specify a desired video interface - according to ../../media/video-interfaces.txt, specifically - - bus-width: recognized values are <12>, <16>, <18> and <24>, and - override any output mode selection heuristic, forcing "rgb444", - "rgb565", "rgb666" and "rgb888" respectively. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible =3D "atmel,sama5d3-hlcdc"; - reg =3D <0xf0030000 0x2000>; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names =3D "periph_clk","sys_clk", "slow_clk"; - - hlcdc-display-controller { - compatible =3D "atmel,hlcdc-display-controller"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - - hlcdc_panel_output: endpoint@0 { - reg =3D <0>; - remote-endpoint =3D <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible =3D "atmel,hlcdc-pwm"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_pwm>; - #pwm-cells =3D <3>; - }; - }; - -Example 2: With a video interface override to force rgb565; as above -but with these changes/additions: - - &hlcdc { - hlcdc-display-controller { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - bus-width =3D <16>; - }; - }; - }; - }; --=20 2.25.1 From nobody Fri Dec 26 05:27:48 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1967C46542; Wed, 10 Jan 2024 10:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tjLrnvZR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1704882395; x=1736418395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LYsjHYtHaBkUuX+2LUIzRbM0YfDq4JHV7BpIPFp0O/4=; b=tjLrnvZR7VurD0lvPScJg/0hMs9vn6dRxnJZpGKFHp92FGJOmdKrthRd 1FRO/Xa3Y/A6UjWSCfOWLXL/yXSsOGMDyS3T3bVO82Dry9AjtbgoQ3zCu LecVrXO2e0f+PalsQZmGd/nGmYgy0e2+IZXxlmZzBtWmrJzFtAjx7f4/Z PlIhwynWDSyrV99KxAfQbqANTxuS5OCWSEpW5BxenVkqgkn2EDWu3W+dj Oxm/Mtrihpyfp1EH4mVY3d0dBiI/i4f+vuX948IbcZrPfj2UnyyNzMaiC M5A9/g6vfv2rJGhWeE520ZrEJZprEHlL6nRD537NL+QCTn8DVwQOF9KS7 Q==; X-CSE-ConnectionGUID: 4FLeVdXIRtGRQjBQXLr/AA== X-CSE-MsgGUID: DStoH7nbR4K88ZHWQVETCw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="181745214" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jan 2024 03:26:26 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 10 Jan 2024 03:26:17 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 10 Jan 2024 03:26:09 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , CC: Dharma Balasubiramani Subject: [PATCH 2/3] dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format Date: Wed, 10 Jan 2024 15:55:34 +0530 Message-ID: <20240110102535.246177-3-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110102535.246177-1-dharma.b@microchip.com> References: <20240110102535.246177-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the atmel,hlcdc binding to DT schema format. Signed-off-by: Dharma Balasubiramani --- .../devicetree/bindings/mfd/atmel,hlcdc.yaml | 106 ++++++++++++++++++ .../devicetree/bindings/mfd/atmel-hlcdc.txt | 56 --------- 2 files changed, 106 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml b/Docum= entation/devicetree/bindings/mfd/atmel,hlcdc.yaml new file mode 100644 index 000000000000..555d6faa9104 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC (High LCD Controller) MFD driver + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: | + Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver. + The HLCDC IP exposes two subdevices: + # a PWM chip: see ../pwm/atmel,hlcdc-pwm.yaml + # a Display Controller: see ../display/atmel/atmel,hlcdc-dc.yaml + +properties: + compatible: + enum: + - atmel,at91sam9n12-hlcdc + - atmel,at91sam9x5-hlcdc + - atmel,sama5d2-hlcdc + - atmel,sama5d3-hlcdc + - atmel,sama5d4-hlcdc + - microchip,sam9x60-hlcdc + - microchip,sam9x75-xlcdc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + anyOf: + - items: + - enum: + - sys_clk + - lvds_pll_clk + - contains: + const: periph_clk + - contains: + const: slow_clk + maxItems: 3 + + hlcdc-display-controller: + $ref: /schemas/display/atmel/atmel,hlcdc-dc.yaml + + hlcdc-pwm: + $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + + hlcdc: hlcdc@f0030000 { + compatible =3D "atmel,sama5d3-hlcdc"; + reg =3D <0xf0030000 0x2000>; + clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names =3D "periph_clk","sys_clk", "slow_clk"; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; + + hlcdc-display-controller { + compatible =3D "atmel,hlcdc-display-controller"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + hlcdc_panel_output: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_input>; + }; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible =3D "atmel,hlcdc-pwm"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_pwm>; + #pwm-cells =3D <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Docume= ntation/devicetree/bindings/mfd/atmel-hlcdc.txt deleted file mode 100644 index 7de696eefaed..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt +++ /dev/null @@ -1,56 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver - -Required properties: - - compatible: value should be one of the following: - "atmel,at91sam9n12-hlcdc" - "atmel,at91sam9x5-hlcdc" - "atmel,sama5d2-hlcdc" - "atmel,sama5d3-hlcdc" - "atmel,sama5d4-hlcdc" - "microchip,sam9x60-hlcdc" - "microchip,sam9x75-xlcdc" - - reg: base address and size of the HLCDC device registers. - - clock-names: the name of the 3 clocks requested by the HLCDC device. - Should contain "periph_clk", "sys_clk" and "slow_clk". - - clocks: should contain the 3 clocks requested by the HLCDC device. - - interrupts: should contain the description of the HLCDC interrupt line - -The HLCDC IP exposes two subdevices: - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt - - a Display Controller: see ../display/atmel/hlcdc-dc.txt - -Example: - - hlcdc: hlcdc@f0030000 { - compatible =3D "atmel,sama5d3-hlcdc"; - reg =3D <0xf0030000 0x2000>; - clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names =3D "periph_clk","sys_clk", "slow_clk"; - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; - - hlcdc-display-controller { - compatible =3D "atmel,hlcdc-display-controller"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0>; - - hlcdc_panel_output: endpoint@0 { - reg =3D <0>; - remote-endpoint =3D <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible =3D "atmel,hlcdc-pwm"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_pwm>; - #pwm-cells =3D <3>; - }; - }; --=20 2.25.1 From nobody Fri Dec 26 05:27:48 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB2C046BA6; Wed, 10 Jan 2024 10:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QMRWzH1e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1704882399; x=1736418399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5WUd7zZW6vaz2VFpcySRfwde2JHnsfcvgGymaZA0H0s=; b=QMRWzH1e9gW+jYSuJIF5GsdSF5RBrlor7KuSCb0kOw6fIqNq8uSVkzSu 1Y/90fiPzybFg++BmPNYwWkFlmNzmrBIY98uCXc4dFXrPlpGQDyK8ZAqD URLReSa7ZeG2AUSbczMvjmsb2PM6Eomr7k4ge3FIYTfGbxvO+GLcYLshb pxoHJpZSeuDLdiNUie/M4qswfkkX/b/OjSzfyTlvqII6yytoFXvW6ROPk 3x6sS8Sql1A5kGo8/g4hNQUYkDAKjNCHqAjZxW7rx2J2LTBrjtjc8TA3P yrtMOPgIq5At0KhdnYHa+C6mGI9hOg1FXQTyWk33DV4YHI4LWWEulQuVK w==; X-CSE-ConnectionGUID: 5D2eo3saR72tqfGaKhDyVQ== X-CSE-MsgGUID: P1+T+hWdTWqrrzrBB18h6g== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,184,1695711600"; d="scan'208";a="14511322" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jan 2024 03:26:35 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 10 Jan 2024 03:26:25 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 10 Jan 2024 03:26:17 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , CC: Dharma Balasubiramani Subject: [PATCH 3/3] dt-bindings: atmel,hlcdc: convert pwm bindings to json-schema Date: Wed, 10 Jan 2024 15:55:35 +0530 Message-ID: <20240110102535.246177-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110102535.246177-1-dharma.b@microchip.com> References: <20240110102535.246177-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert device tree bindings for Atmel's HLCDC PWM controller to YAML format. Signed-off-by: Dharma Balasubiramani --- .../bindings/pwm/atmel,hlcdc-pwm.yaml | 62 +++++++++++++++++++ .../bindings/pwm/atmel-hlcdc-pwm.txt | 29 --------- 2 files changed, 62 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.y= aml delete mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.t= xt diff --git a/Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml b/D= ocumentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml new file mode 100644 index 000000000000..99eaad55ccb3 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel,hlcdc-pwm.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC (High-end LCD Controller) PWM driver + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: | + Device-Tree bindings for Atmel's HLCDC PWM driver. The Atmel HLCDC PWM i= s a + subdevice of the HLCDC MFD device. + # See ../mfd/atmel,hlcdc.yaml for more details. + +properties: + compatible: + const: atmel,hlcdc-pwm + + pinctrl-names: + const: default + + pinctrl-0: true + + "#pwm-cells": + const: 3 + description: | + This PWM chip uses the default 3 cells bindings defined in pwm.yaml = in + this directory. + +required: + - compatible + - pinctrl-names + - pinctrl-0 + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + hlcdc: hlcdc@f0030000 { + compatible =3D "atmel,sama5d3-hlcdc"; + reg =3D <0xf0030000 0x2000>; + clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names =3D "periph_clk","sys_clk", "slow_clk"; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; + + hlcdc_pwm: hlcdc-pwm { + compatible =3D "atmel,hlcdc-pwm"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_pwm>; + #pwm-cells =3D <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Do= cumentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt deleted file mode 100644 index afa501bf7f94..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver - -The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. -See ../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be one of the following: - "atmel,hlcdc-pwm" - - pinctr-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the pinctrl states described by pinctrl - default. - - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.yaml in this directory. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible =3D "atmel,sama5d3-hlcdc"; - reg =3D <0xf0030000 0x2000>; - clocks =3D <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names =3D "periph_clk","sys_clk", "slow_clk"; - - hlcdc_pwm: hlcdc-pwm { - compatible =3D "atmel,hlcdc-pwm"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_lcd_pwm>; - #pwm-cells =3D <3>; - }; - }; --=20 2.25.1