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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Subject: [PATCH v7 09/16] dt-bindings: riscv: Add T-Head PMU extension
 description
Date: Wed, 10 Jan 2024 15:39:10 +0800
Message-ID: <20240110073917.2398826-10-peterlin@andestech.com>
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Document the ISA string for T-Head performance monitor extension
which provides counter overflow interrupt mechanism.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v2 -> v3:
  - New patch
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Guo's Reviewed-by
  - Include Inochi's Reviewed-by
  - Update to C910 documentation with its commit hash
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu=
mentation/devicetree/bindings/riscv/extensions.yaml
index 27beedb98198..ee0747f29d6d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,11 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
=20
+        - const: xtheadpmu
+          description:
+            The T-Head performance monitor extension for counter overflow,=
 as ratified
+            in commit 4c4981 ("Initial commit") of Xuantie C910 user manua=
l.
+            https://github.com/T-head-Semi/openc910/tree/main/doc
+
 additionalProperties: true
 ...
--=20
2.34.1