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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:17 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:08 +0100 Subject: [PATCH v2 1/4] dt-bindings: display: panel: Add Himax HX83112A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-fp4-panel-v2-1-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss , Krzysztof Kozlowski X-Mailer: b4 0.12.4 Himax HX83112A is a display driver IC used to drive LCD DSI panels. Describe it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss --- .../bindings/display/panel/himax,hx83112a.yaml | 75 ++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83112a= .yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83112a.yaml new file mode 100644 index 000000000000..22f58f1da9fd --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83112a.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX83112A-based DSI display panels + +maintainers: + - Luca Weiss + +description: + The Himax HX83112A is a generic DSI Panel IC used to control + LCD panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: fairphone,fp4-hx83112a-djn + - const: himax,hx83112a + + vdd1-supply: + description: Digital voltage rail + + vsn-supply: + description: Positive source voltage rail + + vsp-supply: + description: Negative source voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd1-supply + - vsn-supply + - vsp-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "fairphone,fp4-hx83112a-djn", "himax,hx83112a"; + reg =3D <0>; + + backlight =3D <&pm6150l_wled>; + reset-gpios =3D <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply =3D <&vreg_l1e>; + vsn-supply =3D <&pm6150l_lcdb_ncp>; + vsp-supply =3D <&pm6150l_lcdb_ldo>; + + port { + panel_in_0: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + +... --=20 2.43.0 From nobody Fri Dec 26 01:25:09 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 985654BAA3 for ; Wed, 10 Jan 2024 15:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="IQQviqyU" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a277339dcf4so468560966b.2 for ; Wed, 10 Jan 2024 07:14:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1704899659; x=1705504459; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+N0oNnhvefANzwE/C/9ajXYuBkvvv0LTVUo1X3IIYTw=; b=IQQviqyURB0X47eJCsq3sZPKnI1C+LzVWc16hpNqiyTQ1Zs4RxYVGjAMJlCbNvEc0C hWKOob0fxpJEAw0uQ2vEcwdwZmvHvmK4osw4absuU5y54Q6se44Nx7sgJ6S8x0+10j/0 1EKjyX4xyH0mdHBgfnZurc1TpftTHo4L3+1s4e6Oy26tQ0NSHD2dymfZ5v8C+D9+Boxy 41GPTGEfqQgN4pgE18+tpXplEz1mcBW9e7iSu38ML53EbwDK0+3SlgR21YDLCR/d+ojK TznFe96f+EDkK6/+rZzBViNp2GnZXU4QAQUmHrDgVUAt6JUpvol/8mvLo+MhqLiTEqxd VFNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704899659; x=1705504459; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+N0oNnhvefANzwE/C/9ajXYuBkvvv0LTVUo1X3IIYTw=; b=xMyAMFdzn6JWo+Ivn2+rx7X+T4kMDct4FXXqvYIyxNME6XUCkM9K5Og1vT03zcBiiT BC/xIhcV6JfvtgmSesT5VgI1JZTDACbzka4V9G1qqSnyGvlc6lhaunfj8RiRCUF3BRxP VeSw0aTW/1myFyWoAgH8rE091MxafPVRBQXW4rPVX3JM7pjiuuxT8lzY4khCy+CrlVIe H5P+egReZuAsPcGBZmXXzCv8vVHZtScTaEzJeG1y3uU1P5vpSVFQdNpqh19H+LV5PPa6 kXE1h5eEI0Fa3aX8EgNPd3lAUoydD/Rp1LJ4NgZM33O2Gao56DJoMV5tvbufubS1dBeI tr+g== X-Gm-Message-State: AOJu0YyJNQOLPVGhsnvczu7TBPVAkWia++Mz88YOSijDVXwV7+yvR78G aldbJ2nXFZN2BdNxx8bJ+wCNLusJI2KSLw== X-Google-Smtp-Source: AGHT+IFLjqu91jpqL55jGv8OLP9mSGJfnFlj+Y6cBx9H4VoxXnBetq/EK0J9pN05w/NSdMhyxnKPIQ== X-Received: by 2002:a17:906:6802:b0:a27:6d9c:8194 with SMTP id k2-20020a170906680200b00a276d9c8194mr651100ejr.119.1704899658827; Wed, 10 Jan 2024 07:14:18 -0800 (PST) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:17 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:09 +0100 Subject: [PATCH v2 2/4] drm/panel: Add driver for DJN HX83112A LCD panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-fp4-panel-v2-2-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 Add support for the 2340x1080 LCD DJN panel bundled with a HX83112A driver IC, as found on the Fairphone 4 smartphone. Signed-off-by: Luca Weiss --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-himax-hx83112a.c | 352 +++++++++++++++++++++++= ++++ 3 files changed, 363 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 99e14dc212ec..3379b13df4b8 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -162,6 +162,16 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D Say Y if you want to enable support for panels based on the Feiyang FY07024DI26A30-D MIPI-DSI interface. =20 +config DRM_PANEL_HIMAX_HX83112A + tristate "Himax HX83112A-based DSI panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select DRM_KMS_HELPER + help + Say Y here if you want to enable support for Himax HX83112A-based + display panels, such as the one found in the Fairphone 4 smartphone. + config DRM_PANEL_HIMAX_HX8394 tristate "HIMAX HX8394 MIPI-DSI LCD panels" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d10c3de51c6d..c2fc4c8c8340 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) +=3D panel-ebbg-ft871= 9.o obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) +=3D panel-elida-kd35t133.o obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) +=3D panel-feixin-k101-im2ba02= .o obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) +=3D panel-feiyang-fy07024= di26a30d.o +obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) +=3D panel-himax-hx83112a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) +=3D panel-himax-hx8394.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) +=3D panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) +=3D panel-ilitek-ili9341.o diff --git a/drivers/gpu/drm/panel/panel-himax-hx83112a.c b/drivers/gpu/drm= /panel/panel-himax-hx83112a.c new file mode 100644 index 000000000000..cccc6075fd8e --- /dev/null +++ b/drivers/gpu/drm/panel/panel-himax-hx83112a.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device= tree. + * Copyright (c) 2024 Luca Weiss + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct hx83112a_panel { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data supplies[3]; + struct gpio_desc *reset_gpio; +}; + +static inline struct hx83112a_panel *to_hx83112a_panel(struct drm_panel *p= anel) +{ + return container_of(panel, struct hx83112a_panel, panel); +} + +static void hx83112a_reset(struct hx83112a_panel *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(50); +} + +static int hx83112a_on(struct hx83112a_panel *ctx) +{ + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x83, 0x11, 0x2a); + mipi_dsi_dcs_write_seq(dsi, 0xb1, + 0x08, 0x28, 0x28, 0x83, 0x83, 0x4c, 0x4f, 0x33); + mipi_dsi_dcs_write_seq(dsi, 0xb2, + 0x00, 0x02, 0x00, 0x90, 0x24, 0x00, 0x08, 0x19, + 0xea, 0x11, 0x11, 0x00, 0x11, 0xa3); + mipi_dsi_dcs_write_seq(dsi, 0xb4, + 0x58, 0x68, 0x58, 0x68, 0x0f, 0xef, 0x0b, 0xc0, + 0x0b, 0xc0, 0x0b, 0xc0, 0x00, 0xff, 0x00, 0xff, + 0x00, 0x00, 0x14, 0x15, 0x00, 0x29, 0x11, 0x07, + 0x12, 0x00, 0x29); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xb4, + 0x00, 0x12, 0x12, 0x11, 0x88, 0x12, 0x12, 0x00, + 0x53); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x03); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xc1, + 0xff, 0xfe, 0xfb, 0xf8, 0xf4, 0xf1, 0xed, 0xe6, + 0xe2, 0xde, 0xdb, 0xd6, 0xd3, 0xcf, 0xca, 0xc6, + 0xc2, 0xbe, 0xb9, 0xb0, 0xa7, 0x9e, 0x96, 0x8d, + 0x84, 0x7c, 0x74, 0x6b, 0x62, 0x5a, 0x51, 0x49, + 0x41, 0x39, 0x31, 0x29, 0x21, 0x19, 0x12, 0x0a, + 0x06, 0x05, 0x02, 0x01, 0x00, 0x00, 0xc9, 0xb3, + 0x08, 0x0e, 0xf2, 0xe1, 0x59, 0xf4, 0x22, 0xad, + 0x40); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xc7, 0x70, 0x00, 0x04, 0xe0, 0x33, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x08); + mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x2b, 0x2b); + mipi_dsi_dcs_write_seq(dsi, 0xd3, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, + 0x08, 0x03, 0x03, 0x22, 0x18, 0x07, 0x07, 0x07, + 0x07, 0x32, 0x10, 0x06, 0x00, 0x06, 0x32, 0x10, + 0x07, 0x00, 0x07, 0x32, 0x19, 0x31, 0x09, 0x31, + 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x09, 0x30, 0x00, 0x00, 0x00, 0x06, 0x0d, 0x00, + 0x0f); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xd3, + 0x00, 0x00, 0x19, 0x10, 0x00, 0x0a, 0x00, 0x81); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xd5, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0xc0, 0xc0, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, + 0x28, 0x28, 0x24, 0x24, 0x02, 0x03, 0x02, 0x03, + 0x00, 0x01, 0x00, 0x01, 0x31, 0x31, 0x31, 0x31, + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); + mipi_dsi_dcs_write_seq(dsi, 0xd6, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x3f, 0x3f, + 0x24, 0x24, 0x28, 0x28, 0x01, 0x00, 0x01, 0x00, + 0x03, 0x02, 0x03, 0x02, 0x31, 0x31, 0x31, 0x31, + 0x30, 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, + 0xaa, 0xaa, 0xaa, 0xea, 0xab, 0xaa, 0xaa, 0xaa); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0x2e, 0x28, 0x00, 0x00, 0x00, 0xaa, 0x2e, + 0x28, 0x00, 0x00, 0x00, 0xaa, 0xee, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xee, 0xaa, 0xaa, 0xaa, 0xaa); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xff, + 0xff, 0xff, 0xff, 0xff); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x03); + mipi_dsi_dcs_write_seq(dsi, 0xd8, + 0xaa, 0xaa, 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xea, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x0e, 0x0e, 0x1e, 0x65, 0x1c, 0x65, 0x00, 0x50, + 0x20, 0x20, 0x00, 0x00, 0x02, 0x02, 0x02, 0x05, + 0x14, 0x14, 0x32, 0xb9, 0x23, 0xb9, 0x08); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x02, 0x00, 0xa8, 0x01, 0xa8, 0x0d, 0xa4, 0x0e); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x02); + mipi_dsi_dcs_write_seq(dsi, 0xe7, + 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0xc3); + mipi_dsi_dcs_write_seq(dsi, 0xcb, 0xd1, 0xd6); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x3f); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0xc6); + mipi_dsi_dcs_write_seq(dsi, 0xbf, 0x37); + mipi_dsi_dcs_write_seq(dsi, 0xe9, 0x3f); + + ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(150); + + ret =3D mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + msleep(50); + + return 0; +} + +static int hx83112a_disable(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx =3D to_hx83112a_panel(panel); + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; + + ret =3D mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(20); + + ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int hx83112a_prepare(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx =3D to_hx83112a_panel(panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + + hx83112a_reset(ctx); + + ret =3D hx83112a_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + return ret; + } + + return 0; +} + +static int hx83112a_unprepare(struct drm_panel *panel) +{ + struct hx83112a_panel *ctx =3D to_hx83112a_panel(panel); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + + return 0; +} + +static const struct drm_display_mode hx83112a_mode =3D { + .clock =3D (1080 + 28 + 8 + 8) * (2340 + 27 + 5 + 5) * 60 / 1000, + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 28, + .hsync_end =3D 1080 + 28 + 8, + .htotal =3D 1080 + 28 + 8 + 8, + .vdisplay =3D 2340, + .vsync_start =3D 2340 + 27, + .vsync_end =3D 2340 + 27 + 5, + .vtotal =3D 2340 + 27 + 5 + 5, + .width_mm =3D 67, + .height_mm =3D 145, + .type =3D DRM_MODE_TYPE_DRIVER, +}; + +static int hx83112a_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &hx83112a_mode); +} + +static const struct drm_panel_funcs hx83112a_panel_funcs =3D { + .prepare =3D hx83112a_prepare, + .unprepare =3D hx83112a_unprepare, + .disable =3D hx83112a_disable, + .get_modes =3D hx83112a_get_modes, +}; + +static int hx83112a_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev =3D &dsi->dev; + struct hx83112a_panel *ctx; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->supplies[0].supply =3D "vdd1"; + ctx->supplies[1].supply =3D "vsn"; + ctx->supplies[2].supply =3D "vsp"; + ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi =3D dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes =3D 4; + dsi->format =3D MIPI_DSI_FMT_RGB888; + dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HSE | + MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &hx83112a_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first =3D true; + + ret =3D drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + ret =3D mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void hx83112a_remove(struct mipi_dsi_device *dsi) +{ + struct hx83112a_panel *ctx =3D mipi_dsi_get_drvdata(dsi); + int ret; + + ret =3D mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id hx83112a_of_match[] =3D { + { .compatible =3D "fairphone,fp4-hx83112a-djn" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, hx83112a_of_match); + +static struct mipi_dsi_driver hx83112a_driver =3D { + .probe =3D hx83112a_probe, + .remove =3D hx83112a_remove, + .driver =3D { + .name =3D "panel-himax-hx83112a", + .of_match_table =3D hx83112a_of_match, + }, +}; +module_mipi_dsi_driver(hx83112a_driver); + +MODULE_DESCRIPTION("DRM driver for hx83112a-equipped DSI panels"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Fri Dec 26 01:25:09 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3B24C3D4 for ; Wed, 10 Jan 2024 15:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="hl53Ro7I" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a2814fa68eeso346761466b.1 for ; Wed, 10 Jan 2024 07:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:19 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:10 +0100 Subject: [PATCH v2 3/4] arm64: dts: qcom: sm6350: Remove "disabled" state of GMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-fp4-panel-v2-3-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 The GMU won't probe without GPU being enabled, so we can remove the disabled status so we don't have to explicitly enable the GMU in all the devices that enable GPU. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 8fd6f4d03490..29008e155d62 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1449,8 +1449,6 @@ gmu: gmu@3d6a000 { =20 operating-points-v2 =3D <&gmu_opp_table>; =20 - status =3D "disabled"; - gmu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 --=20 2.43.0 From nobody Fri Dec 26 01:25:09 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 014174C626 for ; Wed, 10 Jan 2024 15:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="Ipaq+TrH" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a2adc52f213so354189766b.0 for ; Wed, 10 Jan 2024 07:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1704899660; x=1705504460; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HyZi4i2h3MjcAe8ui93Zy0Le6mb9DZJuyAuhhBalDgU=; b=Ipaq+TrHlyo8JhRvpslcYdL5sdEK7+gbKk1iUkeja1kJ8mqwNxVwDIuyDzHBbTU4fe oHj7YRcvhBpPtUotCNmyNYJ5UpVsWZzBBPoKeBqwksfQF16Yurmj4WgNghTH9lFviisB d5/ufz72VDACVYAKhenX5Day7EQ151pr2e74LqfP0zx5weTo5/XUHWmzx8LWbElotkDt LHNMkA+oehoOz7gkOpNbFUG3kcTxCUIPCJFuudrRTwus8Y8K9emCYnh+Q47tlcaa5oqF RSE6cFeEEWyiO4HbwiTLOTy/QgYSq5pSHok1fL94RoMePr4l6uVqGa/ZXgJdyFTAQJKL eYIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704899660; x=1705504460; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HyZi4i2h3MjcAe8ui93Zy0Le6mb9DZJuyAuhhBalDgU=; b=SxdoDNaMWeCjcUkjme5BUSLXNb7dRngZ3FMqEcaeqzOwSYhcSNoZ75lxlGYAFInvCl sqDgHZIOdYv8gF0m5GnFv8mEOU1lA1U/J7oVHwdyXioX3eIFpNRjdKVrZcM4TzsGOZb4 OjrscgOpt66CuyBqgSI9ET9K4M9/6iLs5+2NeXtyc74bE85KC4i4Gf4doddl8GQPAbso wOgBc0L7wWyUcyurqM+xkOMHh7BsDTh5eoSQEEBj0SHlPGF3w5HAtbT3WV6u4C/X15Rq OdMvyJyp9ZU5DPxHPwW4IBTw3TtZzLpxDuUYQrlP/FVCWpnTs025wyqeAUKsefWO68cd meCQ== X-Gm-Message-State: AOJu0YyZ7GCsVLEPHXnBWrPElc00I7HSqh4P21PmB9CiPaWykasXjo8a RXcXKMNkkZ1Ud0KFWsc59C/m6ciwVIfdRcDPGlYrW+gmTRikjg== X-Google-Smtp-Source: AGHT+IEYJKfcjt/Uh/leQB0jE1RBU9OXgRCgowWKHDrfkGCNM/8gBFRQG+CXa8s/tv8EwQ60+U7qKg== X-Received: by 2002:a17:907:b9cc:b0:a28:e870:97b1 with SMTP id xa12-20020a170907b9cc00b00a28e87097b1mr701936ejc.131.1704899660405; Wed, 10 Jan 2024 07:14:20 -0800 (PST) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id jx22-20020a170906ca5600b00a27a25afaf2sm2174517ejb.98.2024.01.10.07.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 07:14:20 -0800 (PST) From: Luca Weiss Date: Wed, 10 Jan 2024 16:14:11 +0100 Subject: [PATCH v2 4/4] arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-fp4-panel-v2-4-8ad11174f65b@fairphone.com> References: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> In-Reply-To: <20240110-fp4-panel-v2-0-8ad11174f65b@fairphone.com> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 Add the description for the display panel found on this phone. Unfortunately the LCDB module on PM6150L isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 53 +++++++++++++++++++= ++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 29008e155d62..b9f4b6be7da9 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1338,7 +1338,7 @@ gpu: gpu@3d00000 { =20 status =3D "disabled"; =20 - zap-shader { + gpu_zap_shader: zap-shader { memory-region =3D <&pil_gpu_mem>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64= /boot/dts/qcom/sm7225-fairphone-fp4.dts index ade619805519..9a7d0448fb68 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -68,6 +68,14 @@ key-volume-up { }; }; =20 + /* Dummy regulator until PM6150L has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcdb_dummy"; + regulator-min-microvolt =3D <5500000>; + regulator-max-microvolt =3D <5500000>; + }; + reserved-memory { /* * The rmtfs memory region in downstream is 'dynamically allocated' @@ -373,6 +381,14 @@ &gpi_dma1 { status =3D "okay"; }; =20 +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm7225/fairphone4/a615_zap.mbn"; +}; + &i2c0 { clock-frequency =3D <400000>; status =3D "okay"; @@ -404,6 +420,43 @@ &ipa { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l22a>; + status =3D "okay"; + + panel@0 { + compatible =3D "fairphone,fp4-hx83112a-djn", "himax,hx83112a"; + reg =3D <0>; + + backlight =3D <&pm6150l_wled>; + reset-gpios =3D <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply =3D <&vreg_l1e>; + vsn-supply =3D <&lcdb_dummy>; + vsp-supply =3D <&lcdb_dummy>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l18a>; + status =3D "okay"; +}; + &mpss { firmware-name =3D "qcom/sm7225/fairphone4/modem.mdt"; status =3D "okay"; --=20 2.43.0