From nobody Fri Dec 26 01:03:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B468C4D107 for ; Wed, 10 Jan 2024 17:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jqsKVvY6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 221ACC43399; Wed, 10 Jan 2024 17:29:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1704907791; bh=7wbCjMM7tjumNzK49XR6Y/BSBSyJJnYiOaEyOvr+9gs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jqsKVvY6TAox8wLuIntNXB+DGU9AJBF/cBVBK9ErMZqAggEfYeZKFW5jQ2BLMU3QH 9LicJocbmgS90Jtww5IXQWt7iUmEnDQJIQul2uKxgNNXO3T3Ikl1/wf5t7RAlA4JfA 4ZORrA9D6xj5cd+0r9HwNdQtRkiYwNblmg+W50AJ29aFG5Yr11DNbnFQaI9VQfKr2r TiSCnURh8Tdur0KavaCN7Q5AIvo117S9/OHOHc518dPhKlrVLroZX5d1SBJ/vyLOB4 +Ocu5ah2Qtr5Uek7bltuR6mjBFhbXL1mBwH95GKUL4yrfOAM381dygWRlY9ljpwaLB F1iYvqYzg4wlg== Received: (nullmailer pid 2134037 invoked by uid 1000); Wed, 10 Jan 2024 17:29:48 -0000 From: Rob Herring Date: Wed, 10 Jan 2024 11:29:20 -0600 Subject: [PATCH 1/2] arm64: Rename ARM64_WORKAROUND_2966298 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-arm-errata-a510-v1-1-d02bc51aeeee@kernel.org> References: <20240110-arm-errata-a510-v1-0-d02bc51aeeee@kernel.org> In-Reply-To: <20240110-arm-errata-a510-v1-0-d02bc51aeeee@kernel.org> To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev In preparation to apply ARM64_WORKAROUND_2966298 for multiple errata, rename the kconfig and capability. No functional change. Cc: stable@vger.kernel.org Signed-off-by: Rob Herring Reviewed-by: Mark Rutland --- arch/arm64/Kconfig | 4 ++++ arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/arm64/kernel/entry.S | 2 +- arch/arm64/tools/cpucaps | 2 +- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 7b071a00425d..ba9f6ceddbbe 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1037,8 +1037,12 @@ config ARM64_ERRATUM_2645198 =20 If unsure, say Y. =20 +config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD + bool + config ARM64_ERRATUM_2966298 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivi= leged load" + select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD default y help This option adds the workaround for ARM Cortex-A520 erratum 2966298. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e29e0fea63fb..cb5e0622168d 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -713,10 +713,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = =3D { MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), }, #endif -#ifdef CONFIG_ARM64_ERRATUM_2966298 +#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD { .desc =3D "ARM erratum 2966298", - .capability =3D ARM64_WORKAROUND_2966298, + .capability =3D ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, /* Cortex-A520 r0p0 - r0p1 */ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), }, diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index a6030913cd58..544ab46649f3 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -428,7 +428,7 @@ alternative_else_nop_endif ldp x28, x29, [sp, #16 * 14] =20 .if \el =3D=3D 0 -alternative_if ARM64_WORKAROUND_2966298 +alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD tlbi vale1, xzr dsb nsh alternative_else_nop_endif diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index b98c38288a9d..3781ad1d0b26 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -84,7 +84,6 @@ WORKAROUND_2077057 WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 -WORKAROUND_2966298 WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TSB_FLUSH_FAILURE @@ -100,3 +99,4 @@ WORKAROUND_NVIDIA_CARMEL_CNP WORKAROUND_QCOM_FALKOR_E1003 WORKAROUND_REPEAT_TLBI WORKAROUND_SPECULATIVE_AT +WORKAROUND_SPECULATIVE_UNPRIV_LOAD --=20 2.43.0 From nobody Fri Dec 26 01:03:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B6E54D13A for ; Wed, 10 Jan 2024 17:29:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pT9o55Ok" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5D72C43390; Wed, 10 Jan 2024 17:29:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1704907793; bh=AJZkoacuvTqj7CsGQGGZ0bokVfCXFoFKdeLY3g2raZw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pT9o55Ok/y+vgFZ3idR8CFkBTvazmrJG+4G4EkiZa6IXF2apa7hrpA1GKpvlC8fkF c5dGuGIAr/Z3SAfRcuhmTZtGzOVnwPo3gMWYYt2WjBseiU2qdSE9rp2tZCAxzqtoPa mMAIU4MGBDSmi60Clv3AF+ed2V3Xit0Dnpn/SFvoa0uT6XnGULjB6qpdKtSdtfCPp3 DJfht+a2Qe0g+Qej5h5UxM7YKcGaLdvNBKMWH0GIHn8LBzjf84fv3ujp7iq/KI2cMI v7dDDYErSNds+Y6ApSeWdHihdBR3Q4MyM9aKxyERo+B5mZjlHar/QOJBfOpyJJJFOM 5xRBV3TH7LAPA== Received: (nullmailer pid 2134039 invoked by uid 1000); Wed, 10 Jan 2024 17:29:48 -0000 From: Rob Herring Date: Wed, 10 Jan 2024 11:29:21 -0600 Subject: [PATCH 2/2] arm64: errata: Add Cortex-A510 speculative unprivileged load workaround Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240110-arm-errata-a510-v1-2-d02bc51aeeee@kernel.org> References: <20240110-arm-errata-a510-v1-0-d02bc51aeeee@kernel.org> In-Reply-To: <20240110-arm-errata-a510-v1-0-d02bc51aeeee@kernel.org> To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev Implement the workaround for ARM Cortex-A510 erratum 3117295. On an affected Cortex-A510 core, a speculatively executed unprivileged load might leak data from a privileged load via a cache side channel. The issue only exists for loads within a translation regime with the same translation (e.g. same ASID and VMID). Therefore, the issue only affects the return to EL0. The erratum and workaround are the same as ARM Cortex-A520 erratum 2966298, so reuse the existing workaround. Cc: stable@vger.kernel.org Signed-off-by: Rob Herring Reviewed-by: Mark Rutland --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/kernel/cpu_errata.c | 17 +++++++++++++++-- 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index f47f63bcf67c..7acd64c61f50 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -71,6 +71,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_26584= 17 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Cortex-A510 | #3117295 | ARM64_ERRATUM_31172= 95 | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A520 | #2966298 | ARM64_ERRATUM_29662= 98 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_82631= 9 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index ba9f6ceddbbe..456e8680e16e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1054,6 +1054,20 @@ config ARM64_ERRATUM_2966298 =20 If unsure, say Y. =20 +config ARM64_ERRATUM_3117295 + bool "Cortex-A510: 3117295: workaround for speculatively executed unprivi= leged load" + select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD + default y + help + This option adds the workaround for ARM Cortex-A510 erratum 3117295. + + On an affected Cortex-A510 core, a speculatively executed unprivileged + load might leak data from a privileged level via a cache side channel. + + Work around this problem by executing a TLBI before returning to EL0. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index cb5e0622168d..8b69fa296470 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -416,6 +416,19 @@ static struct midr_range broken_aarch32_aes[] =3D { }; #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ =20 +#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD +static const struct midr_range erratum_spec_unpriv_load_list[] =3D { +#ifdef CONFIG_ARM64_ERRATUM_3117295 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), +#endif +#ifdef CONFIG_ARM64_ERRATUM_2966298 + /* Cortex-A520 r0p0 to r0p1 */ + MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), +#endif + {}, +}; +#endif + const struct arm64_cpu_capabilities arm64_errata[] =3D { #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE { @@ -715,10 +728,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = =3D { #endif #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD { - .desc =3D "ARM erratum 2966298", + .desc =3D "ARM erratum 2966298 and 3117295", .capability =3D ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, /* Cortex-A520 r0p0 - r0p1 */ - ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), + ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list), }, #endif #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 --=20 2.43.0