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([87.200.95.144]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c0a0a00b0040e486bc0dfsm54021wmp.27.2024.01.09.15.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 15:07:09 -0800 (PST) From: Christian Hewitt To: Neil Armstrong , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Christian Hewitt Subject: [PATCH] drm/meson: vclk: fix calculation of 59.94 fractional rates Date: Tue, 9 Jan 2024 23:07:04 +0000 Message-Id: <20240109230704.4120561-1-christianshewitt@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Playing 4K media with 59.94 fractional rate (typically VP9) causes the scre= en to lose sync with the following error reported in the system log: [ 89.610280] Fatal Error, invalid HDMI vclk freq 593406 Modetest shows the following: 3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: xxxx,= xxxx, drm calculated value -------------------------------------^ Change the fractional rate calculation to stop DIV_ROUND_CLOSEST rounding d= own which results in vclk freq failing to match correctly. Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong --- I'm unable to give a better mathematical description of the fix as I can ba= rely read code. The change was inspired by [0] which I chanced upon while looking at = how other dw-hdmi drivers handle fractional rates. [0] https://github.com/torvalds/linux/commit/4f510aa10468954b1da4e94689c38a= c6ea8d3627 drivers/gpu/drm/meson/meson_vclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/mes= on_vclk.c index 2a82119eb58e..2a942dc6a6dc 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -790,13 +790,13 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv,= unsigned int phy_freq, FREQ_1000_1001(params[i].pixel_freq)); DRM_DEBUG_DRIVER("i =3D %d phy_freq =3D %d alt =3D %d\n", i, params[i].phy_freq, - FREQ_1000_1001(params[i].phy_freq/10)*10); + FREQ_1000_1001(params[i].phy_freq/1000)*1000); /* Match strict frequency */ if (phy_freq =3D=3D params[i].phy_freq && vclk_freq =3D=3D params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (phy_freq =3D=3D (FREQ_1000_1001(params[i].phy_freq/10)*10) && + if (phy_freq =3D=3D (FREQ_1000_1001(params[i].phy_freq/1000)*1000) && vclk_freq =3D=3D FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; } @@ -1070,7 +1070,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigne= d int target, =20 for (freq =3D 0 ; params[freq].pixel_freq ; ++freq) { if ((phy_freq =3D=3D params[freq].phy_freq || - phy_freq =3D=3D FREQ_1000_1001(params[freq].phy_freq/10)*10) && + phy_freq =3D=3D FREQ_1000_1001(params[freq].phy_freq/1000)*1000) && (vclk_freq =3D=3D params[freq].vclk_freq || vclk_freq =3D=3D FREQ_1000_1001(params[freq].vclk_freq))) { if (vclk_freq !=3D params[freq].vclk_freq) --=20 2.34.1