From nobody Thu Dec 18 15:55:37 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74A003F8F7 for ; Tue, 9 Jan 2024 23:03:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="CZ3HgNV0" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-5f6c12872fbso53384427b3.1 for ; Tue, 09 Jan 2024 15:03:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1704841380; x=1705446180; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=LadkSkOnespq7J+bb9MybmOp6ANC4ZDI49MV81r/bQE=; b=CZ3HgNV0hOupopA4+p9nuwDSscAzTLrKVCboN3zZ9Ces+bq4Yf0/QzkcD3ttrkV5MM 2y6OaV39QPEddBuLGlL12i5bp+/iWgReVsWx2SLD7z6OyNR9Ejpng7U+toBExEjL0cSQ 5dXrBHZRWgJZfIMZCflX9ARKwLo3BbeDbTCXpoYNILFLM6qSL5AMuvlvSUO1RhGrCTrk TuvXAIo+6Z1oRBdfqO4JY3kn65kmtHEjsL6L4BqIkCat/W+87EhryPAeVrGb11x54LqE AyXDLNmP/GYcARXi6YPM2kACkcOw/lk8xxLzpIQlMEswMMB87oYQJn58J/HAhF2rPiZr CLYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704841380; x=1705446180; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LadkSkOnespq7J+bb9MybmOp6ANC4ZDI49MV81r/bQE=; b=vOiYhrrjFseGzIbFIAwxsAynJ5ZMpHi8JJC8Cfz1A8Hve5PEr2LMyX1mkK/2Q+WVKP G9gtmsHf+wGnfPefW87+44eBiL2+2Kqp7Zmv6YSjm/KQHZZo5ip+kqgS05sHmRmObp9N QIn9hybCS9KHazuJJPsXsG7MsRFqNkn6gbpT8k8gXfSbQDRs1xgGz3fepTFDDHmg8v5n KfAs1kgSyE+0hslV9An8bQMZhQrMLbGcGXG6LM7CQSv5aOcbvd/VEF/tUdRVMlthbzNw FLSKHZ+caFEujf+QRv0/SpQaz8RxqtalWz9Cdmrz4UksZF1erAhGa9ex1SaLXb55Vo5v alDw== X-Gm-Message-State: AOJu0YwhAbsQsZM+MElx6SZIBgU7She7klGTxy36+Zq2BcGUFruW3Fdp eeSojNjO/SnbDarbqummIKA/UTjGNnS2xjli2w== X-Google-Smtp-Source: AGHT+IH+wwm+B9UodY/w3WuN8h1tNmWmYi6IBiza4wg28y9Lz6PYElcilIEWQr8f7lQ/uZg7EHBE+DknZNE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:690c:a9a:b0:5f6:f1ec:2da5 with SMTP id ci26-20020a05690c0a9a00b005f6f1ec2da5mr104412ywb.9.1704841380561; Tue, 09 Jan 2024 15:03:00 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 9 Jan 2024 15:02:24 -0800 In-Reply-To: <20240109230250.424295-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240109230250.424295-1-seanjc@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20240109230250.424295-5-seanjc@google.com> Subject: [PATCH v10 04/29] KVM: x86/pmu: Setup fixed counters' eventsel during PMU initialization From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set the eventsel for all fixed counters during PMU initialization, the eventsel is hardcoded and consumed if and only if the counter is supported, i.e. there is no reason to redo the setup every time the PMU is refreshed. Configuring all KVM-supported fixed counter also eliminates a potential pitfall if/when KVM supports discontiguous fixed counters, in which case configuring only nr_arch_fixed_counters will be insufficient (ignoring the fact that KVM will need many other changes to support discontiguous fixed counters). Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index f3c44ddc09f8..98e92b9ece09 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -407,27 +407,21 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) * Note, reference cycles is counted using a perf-defined "psuedo-encoding= ", * as there is no architectural general purpose encoding for reference cyc= les. */ -static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu) +static u64 intel_get_fixed_pmc_eventsel(int index) { const struct { - u8 eventsel; + u8 event; u8 unit_mask; } fixed_pmc_events[] =3D { [0] =3D { 0xc0, 0x00 }, /* Instruction Retired / PERF_COUNT_HW_INSTRUCTI= ONS. */ [1] =3D { 0x3c, 0x00 }, /* CPU Cycles/ PERF_COUNT_HW_CPU_CYCLES. */ [2] =3D { 0x00, 0x03 }, /* Reference Cycles / PERF_COUNT_HW_REF_CPU_CYCL= ES*/ }; - int i; =20 BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_events) !=3D KVM_PMC_MAX_FIXED); =20 - for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) { - int index =3D array_index_nospec(i, KVM_PMC_MAX_FIXED); - struct kvm_pmc *pmc =3D &pmu->fixed_counters[index]; - - pmc->eventsel =3D (fixed_pmc_events[index].unit_mask << 8) | - fixed_pmc_events[index].eventsel; - } + return (fixed_pmc_events[index].unit_mask << 8) | + fixed_pmc_events[index].event; } =20 static void intel_pmu_refresh(struct kvm_vcpu *vcpu) @@ -493,7 +487,6 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) kvm_pmu_cap.bit_width_fixed); pmu->counter_bitmask[KVM_PMC_FIXED] =3D ((u64)1 << edx.split.bit_width_fixed) - 1; - setup_fixed_pmc_eventsel(pmu); } =20 for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) @@ -571,6 +564,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) pmu->fixed_counters[i].vcpu =3D vcpu; pmu->fixed_counters[i].idx =3D i + INTEL_PMC_IDX_FIXED; pmu->fixed_counters[i].current_config =3D 0; + pmu->fixed_counters[i].eventsel =3D intel_get_fixed_pmc_eventsel(i); } =20 lbr_desc->records.nr =3D 0; --=20 2.43.0.472.g3155946c3a-goog