From nobody Thu Dec 18 15:54:50 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B89C3EA8D for ; Tue, 9 Jan 2024 23:02:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="2YPrExjc" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-5f0fd486b9aso48666517b3.2 for ; Tue, 09 Jan 2024 15:02:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1704841378; x=1705446178; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=1/GLluKzm5a7vgNb0LnAfQGRD4+bEom3jW+vTNfr4Fk=; b=2YPrExjc0KRY4jq/g4YhkL3pTS0rNd2lp6AtaNvDsvzVsL01wQZVxHAOSMi0brOHqN JILYPzCgJWmtk5O+Te5miinhQHwtnhPy3XF50DfR4vl/n3nXvzhOMYRT0EgFvhucVAcY PUpkH3iwEyEYSQZw89Ye18BatmB7m0AHIcHesN9arSwm0tW6frJtBM4jXux6/6+CLfEu Kc1sZuJc7JUl98yaBIRu7UOaqC2LbQfBd/EA3HWxLfIuKYCPygEjUBoOy7/mOZbire6r 1tEAk2aeKdo+2Yaa+ax8fnaA46qf97gqejOIS643304Jh0Qe4k/g2RENrsdvqCia+3JY 6EWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704841378; x=1705446178; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1/GLluKzm5a7vgNb0LnAfQGRD4+bEom3jW+vTNfr4Fk=; b=Ehpkq0UQaB+IiVW6FUiBJR9LpiaHDOWrfn2MTC/sbhR0B66TnbJMF/GgxRFtFfdAVE o8Q0UyNMOwu9BT/cU6U4PViPuA4N7AS10bKED/1lpvGO10XaHgWZvxpaANdfgV2IGp3f 6UbjLY5J93I5zk7ZoOwwyMEmXuFnqAdtimnxF5lwWFs8mPcXeLbvIF4TUxMs3DEQpJZ3 FAmKDBBqesvF9Ic3pqBQiZvEQuMkRqS1CimoMEMnKIbeTDvZql77xRiiJBBUoD/Vm+O9 Bxpxq6rwS4IO+wAcwgLGPVdRfxMI/6hMcU2ocCqczyMNRoYeHMmvw4I5KrIKrcwEID96 ODfw== X-Gm-Message-State: AOJu0YxAqzP9bb/QEtT+iVitqEA55moBOTl3g/0nHwVv82JGeyC6LyFg z59Zs3tKu0ZoiFoY4DQM0UqLd7kBnlTFzcY/gA== X-Google-Smtp-Source: AGHT+IGR1EJFsaKKNBR9ZRETsC1K9eaDazqI2WQD8Rld/XIBOTiC416sUQsUkB7ZDC3FYrVyCzUaLLFlZS8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:d44b:0:b0:5fa:2d2e:a5c0 with SMTP id w72-20020a0dd44b000000b005fa2d2ea5c0mr78683ywd.3.1704841378532; Tue, 09 Jan 2024 15:02:58 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 9 Jan 2024 15:02:23 -0800 In-Reply-To: <20240109230250.424295-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240109230250.424295-1-seanjc@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20240109230250.424295-4-seanjc@google.com> Subject: [PATCH v10 03/29] KVM: x86/pmu: Remove KVM's enumeration of Intel's architectural encodings From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop KVM's enumeration of Intel's architectural event encodings, and instead open code the three encodings (of which only two are real) that KVM uses to emulate fixed counters. Now that KVM doesn't incorrectly enforce the availability of architectural encodings, there is no reason for KVM to ever care about the encodings themselves, at least not in the current format of an array indexed by the encoding's position in CPUID. Opportunistically add a comment to explain why KVM cares about eventsel values for fixed counters. Suggested-by: Jim Mattson Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 72 ++++++++++++------------------------ 1 file changed, 23 insertions(+), 49 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 1a7d021a6c7b..f3c44ddc09f8 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -22,52 +22,6 @@ =20 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) =20 -enum intel_pmu_architectural_events { - /* - * The order of the architectural events matters as support for each - * event is enumerated via CPUID using the index of the event. - */ - INTEL_ARCH_CPU_CYCLES, - INTEL_ARCH_INSTRUCTIONS_RETIRED, - INTEL_ARCH_REFERENCE_CYCLES, - INTEL_ARCH_LLC_REFERENCES, - INTEL_ARCH_LLC_MISSES, - INTEL_ARCH_BRANCHES_RETIRED, - INTEL_ARCH_BRANCHES_MISPREDICTED, - - NR_REAL_INTEL_ARCH_EVENTS, - - /* - * Pseudo-architectural event used to implement IA32_FIXED_CTR2, a.k.a. - * TSC reference cycles. The architectural reference cycles event may - * or may not actually use the TSC as the reference, e.g. might use the - * core crystal clock or the bus clock (yeah, "architectural"). - */ - PSEUDO_ARCH_REFERENCE_CYCLES =3D NR_REAL_INTEL_ARCH_EVENTS, - NR_INTEL_ARCH_EVENTS, -}; - -static struct { - u8 eventsel; - u8 unit_mask; -} const intel_arch_events[] =3D { - [INTEL_ARCH_CPU_CYCLES] =3D { 0x3c, 0x00 }, - [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D { 0xc0, 0x00 }, - [INTEL_ARCH_REFERENCE_CYCLES] =3D { 0x3c, 0x01 }, - [INTEL_ARCH_LLC_REFERENCES] =3D { 0x2e, 0x4f }, - [INTEL_ARCH_LLC_MISSES] =3D { 0x2e, 0x41 }, - [INTEL_ARCH_BRANCHES_RETIRED] =3D { 0xc4, 0x00 }, - [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D { 0xc5, 0x00 }, - [PSEUDO_ARCH_REFERENCE_CYCLES] =3D { 0x00, 0x03 }, -}; - -/* mapping between fixed pmc index and intel_arch_events array */ -static int fixed_pmc_events[] =3D { - [0] =3D INTEL_ARCH_INSTRUCTIONS_RETIRED, - [1] =3D INTEL_ARCH_CPU_CYCLES, - [2] =3D PSEUDO_ARCH_REFERENCE_CYCLES, -}; - static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) { struct kvm_pmc *pmc; @@ -440,8 +394,29 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) return 0; } =20 +/* + * Map fixed counter events to architectural general purpose event encodin= gs. + * Perf doesn't provide APIs to allow KVM to directly program a fixed coun= ter, + * and so KVM instead programs the architectural event to effectively requ= est + * the fixed counter. Perf isn't guaranteed to use a fixed counter and may + * instead program the encoding into a general purpose counter, e.g. if a + * different perf_event is already utilizing the requested counter, but th= e end + * result is the same (ignoring the fact that using a general purpose coun= ter + * will likely exacerbate counter contention). + * + * Note, reference cycles is counted using a perf-defined "psuedo-encoding= ", + * as there is no architectural general purpose encoding for reference cyc= les. + */ static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu) { + const struct { + u8 eventsel; + u8 unit_mask; + } fixed_pmc_events[] =3D { + [0] =3D { 0xc0, 0x00 }, /* Instruction Retired / PERF_COUNT_HW_INSTRUCTI= ONS. */ + [1] =3D { 0x3c, 0x00 }, /* CPU Cycles/ PERF_COUNT_HW_CPU_CYCLES. */ + [2] =3D { 0x00, 0x03 }, /* Reference Cycles / PERF_COUNT_HW_REF_CPU_CYCL= ES*/ + }; int i; =20 BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_events) !=3D KVM_PMC_MAX_FIXED); @@ -449,10 +424,9 @@ static void setup_fixed_pmc_eventsel(struct kvm_pmu *p= mu) for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) { int index =3D array_index_nospec(i, KVM_PMC_MAX_FIXED); struct kvm_pmc *pmc =3D &pmu->fixed_counters[index]; - u32 event =3D fixed_pmc_events[index]; =20 - pmc->eventsel =3D (intel_arch_events[event].unit_mask << 8) | - intel_arch_events[event].eventsel; + pmc->eventsel =3D (fixed_pmc_events[index].unit_mask << 8) | + fixed_pmc_events[index].eventsel; } } =20 --=20 2.43.0.472.g3155946c3a-goog