From nobody Fri Dec 19 00:19:50 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5254B48CEC for ; Tue, 9 Jan 2024 23:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="PNBGrC20" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-5f240ace2efso48088047b3.1 for ; Tue, 09 Jan 2024 15:03:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1704841412; x=1705446212; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=UmbwugfbZjx9BroAj5L+ZfHrFa8HDb/zVhEfTcoxtfc=; b=PNBGrC20KjTlNRwSmRKglaBQjnWMvV2NhhcSeGpSO/eGbavokHb/tkfZE+BEBoEKrA +NR40h+6MmYuAfYNBdv9VpTE/UthS6U7sGharyAphHCgt3Wz+6OwkpMyiE5DTMXYr0i5 n56s+CvBO7pmwLu0fTzrlTpWdbqnocEml/qNodSZ9oZY6+3uXZ690PMwR9OdnZS/x6WD lUugeQDOiA5BaAP0WZiSjKl6iODsx6uvSwyoqFjF0QFnpi53j+Wa3WK4wcUcFqzHLukF 7wGmDxp/etNP3oiaAkore0cHA2YxrTV2NNjsUsJHx/X4QU3EdPCYA4FuhdpFgT3Ia6oj RWzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704841412; x=1705446212; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UmbwugfbZjx9BroAj5L+ZfHrFa8HDb/zVhEfTcoxtfc=; b=GeG2HVKIJzQJGc6R8BW4nOhMaRnnwVahK3L/zt+JbD2g4wzq3IjqZLuU62NdE/MsYQ 0Qyyh3gcXqL8H2cwMvtZywDsemsUTjKc5g64Nptp+PRtK0p3Rl4CWEbQGsjVg/gHsFu5 7PjPrSx1DKxOsqYMXkxDYeOx/xb+e9+LtBfnrouEIBSzXLaK5sZRV75Ghng3Dj9DKUt1 I5gtYhf81yT7bC/vV8J2a3dveW+ouEhJvHducUGFt1pgEtz/+dc7Nxe9ohbBHWJNzBBc fN5+LyYwkVQaun3PY+Bhdcv+EWrk7RubJLWkJ+IIzM3wus/EfxomTyHZmPpTzZ+nWTi1 zAJQ== X-Gm-Message-State: AOJu0YzuKWoYoFQ5c/yWnNCK0iRTMaTuaxIU2KJrBkR8YYsUmnLDuiZm jMG8rwMDtjE/uCNc2TCuIeMxKlSDmOq4U6ruPg== X-Google-Smtp-Source: AGHT+IH55KoAefoSAgaGx1KUdGWyk7jVjq0nl1o93I+EEXhXygMCZvACNTy+k9279E6nOb8jlXDG24cKxK0= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:690c:b03:b0:5e3:2a36:b4d with SMTP id cj3-20020a05690c0b0300b005e32a360b4dmr88378ywb.1.1704841412585; Tue, 09 Jan 2024 15:03:32 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 9 Jan 2024 15:02:40 -0800 In-Reply-To: <20240109230250.424295-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240109230250.424295-1-seanjc@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20240109230250.424295-21-seanjc@google.com> Subject: [PATCH v10 20/29] KVM: selftests: Add functional test for Intel's fixed PMU counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Extend the fixed counters test to verify that supported counters can actually be enabled in the control MSRs, that unsupported counters cannot, and that enabled counters actually count. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang [sean: fold into the rd/wr access test, massage changelog] Reviewed-by: Dapeng Mi Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index b07294af71a3..f5dedd112471 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -332,7 +332,6 @@ static void guest_rd_wr_counters(uint32_t base_msr, uin= t8_t nr_possible_counters vector =3D wrmsr_safe(msr, 0); GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); } - GUEST_DONE(); } =20 static void guest_test_gp_counters(void) @@ -350,6 +349,7 @@ static void guest_test_gp_counters(void) base_msr =3D MSR_IA32_PERFCTR0; =20 guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters, 0); + GUEST_DONE(); } =20 static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, @@ -373,6 +373,7 @@ static void guest_test_fixed_counters(void) { uint64_t supported_bitmask =3D 0; uint8_t nr_fixed_counters =3D 0; + uint8_t i; =20 /* Fixed counters require Architectural vPMU Version 2+. */ if (guest_get_pmu_version() >=3D 2) @@ -387,6 +388,34 @@ static void guest_test_fixed_counters(void) =20 guest_rd_wr_counters(MSR_CORE_PERF_FIXED_CTR0, MAX_NR_FIXED_COUNTERS, nr_fixed_counters, supported_bitmask); + + for (i =3D 0; i < MAX_NR_FIXED_COUNTERS; i++) { + uint8_t vector; + uint64_t val; + + if (i >=3D nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) { + vector =3D wrmsr_safe(MSR_CORE_PERF_FIXED_CTR_CTRL, + FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL)); + __GUEST_ASSERT(vector =3D=3D GP_VECTOR, + "Expected #GP for counter %u in FIXED_CTR_CTRL", i); + + vector =3D wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, + FIXED_PMC_GLOBAL_CTRL_ENABLE(i)); + __GUEST_ASSERT(vector =3D=3D GP_VECTOR, + "Expected #GP for counter %u in PERF_GLOBAL_CTRL", i); + continue; + } + + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(i, FIXED_PMC_KERNEL)); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, FIXED_PMC_GLOBAL_CTRL_ENABLE(i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + val =3D rdmsr(MSR_CORE_PERF_FIXED_CTR0 + i); + + GUEST_ASSERT_NE(val, 0); + } + GUEST_DONE(); } =20 static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabil= ities, --=20 2.43.0.472.g3155946c3a-goog