From nobody Fri Dec 19 00:19:50 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 808DB48CC8 for ; Tue, 9 Jan 2024 23:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="RpgR6PX/" Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-dbcdf587bd6so4824438276.0 for ; Tue, 09 Jan 2024 15:03:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1704841410; x=1705446210; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=V3HBLKV9dLG9W0FGZjUnOV/dOoWVZS8lhx6QyuIwmfg=; b=RpgR6PX/Qf72r8uGhy98Ac5N5AZpzPmrsOy6e/FcSAORupfDMZ3k9ZVugwn3Wa983O gzp/FVwIf8maT8wzwz3F4vNn/xgRz/CsTxAtsHv+wv9ZNlQj+6eobNV2s4nHQA4+tYit 6DyBqzFehobGxu+MfvmdIjiAjyKbqqohK9DXoQdp3xl7TGpPDYh7PjHIBjvdMb4NZiBb svOshw0bIsgobRmJ61l6J4PbJ8x++DROVLcQWJ4d2lHje7AKFX1YBAodTzzh1w24wAf6 V4Ml4ajF0Wfpk0DyG/dNtsAOHCAOGMwtY3vlvciFEkWbNHiwaAwiPsr1DWqEG7SCu3lf rB9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704841410; x=1705446210; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=V3HBLKV9dLG9W0FGZjUnOV/dOoWVZS8lhx6QyuIwmfg=; b=thKlP9EzNfNhm/B22G+4k7Vv4zx2MBkMpR3fNpgAYf2A5Y7ewbwodOEcYkzasi0R6P n+nJmHUKTHEDTHtEMk2hUuG6bScJgur7QD9TRC+euDi6UR5VZEBztuBKp33cCatWFln8 gvnAjZAR3knqrNI8zzvYNo9Ul+1fFtNvdmutGV8JGvAw1PhKhXBiTl+VazPLJczxN3dD rxFQg0bTAtKUVXBuZ4cd9//SFU/X3IpvPCpNwMZOWMlvgBhqIexqR3DzJ5/4McHlK1LC 5pzVsG6a1TOm4QCLxXi+TANPZfFhUmU1FE9WwwGYxWi8COujdJ4xRiTo3HlmlIAFmiG9 8+pQ== X-Gm-Message-State: AOJu0Yza5D7tVlGr25xsd/uZKZn7UulK8Ct+EoroGpXInzCRa802jUdT NDx9tIsNx3xX5kYJulFRAwe2dseL1dKI7T1X0Q== X-Google-Smtp-Source: AGHT+IG1Ge95404hqGLT8btxtkMpRkXTbHOLwKNDNUdXtu0RebdAB+W5LspYi2Z7g+Z5RWmq9dd1g6wCFok= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:83d1:0:b0:dbc:ed8b:feaa with SMTP id v17-20020a2583d1000000b00dbced8bfeaamr33135ybm.10.1704841410603; Tue, 09 Jan 2024 15:03:30 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 9 Jan 2024 15:02:39 -0800 In-Reply-To: <20240109230250.424295-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240109230250.424295-1-seanjc@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20240109230250.424295-20-seanjc@google.com> Subject: [PATCH v10 19/29] KVM: selftests: Test consistency of CPUID with num of fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Extend the PMU counters test to verify KVM emulation of fixed counters in addition to general purpose counters. Fixed counters add an extra wrinkle in the form of an extra supported bitmask. Thus quoth the SDM: fixed-function performance counter 'i' is supported if ECX[i] || (EDX[4:0= ] > i) Test that KVM handles a counter being available through either method. Reviewed-by: Dapeng Mi Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 60 ++++++++++++++++++- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 863418842ef8..b07294af71a3 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -290,7 +290,7 @@ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !v= ector, \ msr, expected_val, val); =20 static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_co= unters, - uint8_t nr_counters) + uint8_t nr_counters, uint32_t or_mask) { uint8_t i; =20 @@ -301,7 +301,13 @@ static void guest_rd_wr_counters(uint32_t base_msr, ui= nt8_t nr_possible_counters */ const uint64_t test_val =3D 0xffff; const uint32_t msr =3D base_msr + i; - const bool expect_success =3D i < nr_counters; + + /* + * Fixed counters are supported if the counter is less than the + * number of enumerated contiguous counters *or* the counter is + * explicitly enumerated in the supported counters mask. + */ + const bool expect_success =3D i < nr_counters || (or_mask & BIT(i)); =20 /* * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are @@ -343,7 +349,7 @@ static void guest_test_gp_counters(void) else base_msr =3D MSR_IA32_PERFCTR0; =20 - guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters); + guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters, 0); } =20 static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, @@ -363,9 +369,50 @@ static void test_gp_counters(uint8_t pmu_version, uint= 64_t perf_capabilities, kvm_vm_free(vm); } =20 +static void guest_test_fixed_counters(void) +{ + uint64_t supported_bitmask =3D 0; + uint8_t nr_fixed_counters =3D 0; + + /* Fixed counters require Architectural vPMU Version 2+. */ + if (guest_get_pmu_version() >=3D 2) + nr_fixed_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTE= RS); + + /* + * The supported bitmask for fixed counters was introduced in PMU + * version 5. + */ + if (guest_get_pmu_version() >=3D 5) + supported_bitmask =3D this_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_= BITMASK); + + guest_rd_wr_counters(MSR_CORE_PERF_FIXED_CTR0, MAX_NR_FIXED_COUNTERS, + nr_fixed_counters, supported_bitmask); +} + +static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabil= ities, + uint8_t nr_fixed_counters, + uint32_t supported_bitmask) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_fixed_counters, + pmu_version, perf_capabilities); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, + supported_bitmask); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS, + nr_fixed_counters); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters(void) { uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_= COUNTERS); uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; @@ -435,6 +482,13 @@ static void test_intel_counters(void) v, perf_caps[i]); for (j =3D 0; j <=3D nr_gp_counters; j++) test_gp_counters(v, perf_caps[i], j); + + pr_info("Testing fixed counters, PMU version %u, perf_caps =3D %lx\n", + v, perf_caps[i]); + for (j =3D 0; j <=3D nr_fixed_counters; j++) { + for (k =3D 0; k <=3D (BIT(nr_fixed_counters) - 1); k++) + test_fixed_counters(v, perf_caps[i], j, k); + } } } } --=20 2.43.0.472.g3155946c3a-goog