From nobody Fri Dec 19 00:19:51 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0480B47F66 for ; Tue, 9 Jan 2024 23:03:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="cyRVBMEg" Received: by mail-pg1-f201.google.com with SMTP id 41be03b00d2f7-5ca4ee5b97aso1220829a12.1 for ; Tue, 09 Jan 2024 15:03:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1704841400; x=1705446200; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=bzI7ZO6tNGlUzmltnB+PRcMw8O3L9lh6nE9+2Vf5zg0=; b=cyRVBMEgmrai+tiaoH/GOFzx5hSoKzJI/IF/7XUN1fZctnqZJO+0gkcKRGg+12ngCJ NuV9paau9ij+aG2b7kB1n4ws/x17PL/ZL0254kFsoqJJVqdU5I9Zva9apTg/3X9/xfrd ESxv9ZFtT3idWjejYR4dsM1EqZRq/QCYZk+JiszxcT5KVSoRH7Dj4fJThtyUDVgC0Or6 hldH4BVorDsV9B1gnHFGhWvhk6/cynN0m+W2PqE2DchBFMkAPAlQ2w3AeutTZ2hdAD7Y I6IIjaHwj0eB3Qrvt80w38JEXZyYQMj8E1vfHhpd3P2R8Oro1jPexyhQEzVbB6Uk/7iW RXQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704841400; x=1705446200; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bzI7ZO6tNGlUzmltnB+PRcMw8O3L9lh6nE9+2Vf5zg0=; b=WKnLRDBL3KKZdJday61MIy9TRkd4DFVRrnPFLYA6JFuy8BI8QgxX5YWuc/BNFPu8GM xnAB6xlj5ATb8q1mW0CzfU/l0QK+wRcEcXrt67705Xz5az57KJeoqnWDdj44nCj+er++ Rikl9aQg2rIvp5pZDTAdfvCtm3I8qc5Et7MgU2rjC4BKoxTIxF/7JUWzCOoUIS9BsJHk qtRHm8mEPNTEJ6y8NN1ptGkyEWC8kn97ccZsCGquK81uwuIugETPL8SFg4gv/KCFlRdj +fHrOWdyZiJs2vBmGAh6BRcLnN5CX/xyvJSYVMJ7qC2p+sfVxWkPqSjzn60xUSfV70MF nCjg== X-Gm-Message-State: AOJu0Yy2F8SYoi2zN+6HiCqJViRJJwHpgaVSwfasaDGKJhpIqJFCZvEM 78pajGtExDqzrr8x5HGnGcpZbgiV6F+OR1j6Uw== X-Google-Smtp-Source: AGHT+IEJx0829jjIBoOoljy2kP5D4IwQCn4OXklePKI0EzLVLwuusEhN95ynYfMMGDRkNJW6WRPHMaR5cFE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a65:6390:0:b0:5ce:d4a8:3820 with SMTP id h16-20020a656390000000b005ced4a83820mr143pgv.10.1704841400468; Tue, 09 Jan 2024 15:03:20 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 9 Jan 2024 15:02:34 -0800 In-Reply-To: <20240109230250.424295-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240109230250.424295-1-seanjc@google.com> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog Message-ID: <20240109230250.424295-15-seanjc@google.com> Subject: [PATCH v10 14/29] KVM: selftests: Extend {kvm,this}_pmu_has() to support fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the kvm_x86_pmu_feature framework to allow querying for fixed counters via {kvm,this}_pmu_has(). Like architectural events, checking for a fixed counter annoyingly requires checking multiple CPUID fields, as a fixed counter exists if: FxCtr[i]_is_supported :=3D ECX[i] || (EDX[4:0] > i); Note, KVM currently doesn't actually support exposing fixed counters via the bitmask, but that will hopefully change sooner than later, and Intel's SDM explicitly "recommends" checking both the number of counters and the mask. Rename the intermedate "anti_feature" field to simply 'f' since the fixed counter bitmask (thankfully) doesn't have reversed polarity like the architectural events bitmask. Note, ideally the helpers would use BUILD_BUG_ON() to assert on the incoming register, but the expected usage in PMU tests can't guarantee the inputs are compile-time constants. Opportunistically define macros for all of the known architectural events and fixed counters. Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/x86_64/processor.h | 65 ++++++++++++++----- 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 4f737d3b893c..92d4f8ecc730 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -282,24 +282,41 @@ struct kvm_x86_cpu_property { * that indicates the feature is _not_ supported, and a property that stat= es * the length of the bit mask of unsupported features. A feature is suppo= rted * if the size of the bit mask is larger than the "unavailable" bit, and s= aid - * bit is not set. + * bit is not set. Fixed counters also bizarre enumeration, but inverted = from + * arch events for general purpose counters. Fixed counters are supported= if a + * feature flag is set **OR** the total number of fixed counters is greater + * than index of the counter. * - * Wrap the "unavailable" feature to simplify checking whether or not a gi= ven - * architectural event is supported. + * Wrap the events for general purpose and fixed counters to simplify chec= king + * whether or not a given architectural event is supported. */ struct kvm_x86_pmu_feature { - struct kvm_x86_cpu_feature anti_feature; + struct kvm_x86_cpu_feature f; }; -#define KVM_X86_PMU_FEATURE(__bit) \ -({ \ - struct kvm_x86_pmu_feature feature =3D { \ - .anti_feature =3D KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ - }; \ - \ - feature; \ +#define KVM_X86_PMU_FEATURE(__reg, __bit) \ +({ \ + struct kvm_x86_pmu_feature feature =3D { \ + .f =3D KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ + }; \ + \ + kvm_static_assert(KVM_CPUID_##__reg =3D=3D KVM_CPUID_EBX || \ + KVM_CPUID_##__reg =3D=3D KVM_CPUID_ECX); \ + feature; \ }) =20 -#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(5) +#define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) +#define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) +#define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) +#define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) +#define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) +#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) +#define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) +#define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) + +#define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) +#define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) +#define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX= , 2) +#define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) =20 static inline unsigned int x86_family(unsigned int eax) { @@ -698,10 +715,16 @@ static __always_inline bool this_cpu_has_p(struct kvm= _x86_cpu_property property) =20 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LE= NGTH); + uint32_t nr_bits; =20 - return nr_bits > feature.anti_feature.bit && - !this_cpu_has(feature.anti_feature); + if (feature.f.reg =3D=3D KVM_CPUID_EBX) { + nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.f.bit && !this_cpu_has(feature.f); + } + + GUEST_ASSERT(feature.f.reg =3D=3D KVM_CPUID_ECX); + nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.f.bit || this_cpu_has(feature.f); } =20 static __always_inline uint64_t this_cpu_supported_xcr0(void) @@ -917,10 +940,16 @@ static __always_inline bool kvm_cpu_has_p(struct kvm_= x86_cpu_property property) =20 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LEN= GTH); + uint32_t nr_bits; =20 - return nr_bits > feature.anti_feature.bit && - !kvm_cpu_has(feature.anti_feature); + if (feature.f.reg =3D=3D KVM_CPUID_EBX) { + nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); + } + + TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); + nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); } =20 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) --=20 2.43.0.472.g3155946c3a-goog