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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:33 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 04/12] tty: serial: samsung: prepare for different IO types Date: Tue, 9 Jan 2024 12:58:06 +0000 Message-ID: <20240109125814.3691033-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. If using 8-bit register accesses, a SError Interrupt is raised causing the system unusable. Instead of specifying the reg-io-width =3D 4 everywhere, for each node, the requirement should be deduced from the compatible. Prepare the samsung tty driver to allow IO types different than UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all its 8 bits are exposed to uapi. We can't make NULL checks on it to verify if it's set, thus always set it from the driver's data. Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to emphasize that the iotype is an 8 bit mask. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko --- v3: - reposition the ``iotype`` member of ``struct s3c24xx_uart_info`` so that we reduce the struct's memory footprint. - change ``iotype`` to u8 to emphasize that it's a 8 bit mask and update the commit message explaining why. v2: new patch drivers/tty/serial/samsung_tty.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_= tty.c index 66bd6c090ace..ff646cddd3f8 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -84,6 +84,7 @@ struct s3c24xx_uart_info { unsigned long clksel_mask; unsigned long clksel_shift; unsigned long ucon_mask; + u8 iotype; =20 /* uart port features */ =20 @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int inde= x) { =20 spin_lock_init(&port->lock); =20 - port->iotype =3D UPIO_MEM; port->uartclk =3D 0; port->fifosize =3D 16; port->flags =3D UPF_BOOT_AUTOCONF; @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_devic= e *pdev) break; } =20 + ourport->port.iotype =3D ourport->info->iotype; + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); @@ -2401,6 +2403,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_s= erial_drv_data =3D { .name =3D "Samsung S3C6400 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .fifosize =3D 64, .has_divslot =3D 1, .rx_fifomask =3D S3C2440_UFSTAT_RXMASK, @@ -2430,6 +2433,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_s= erial_drv_data =3D { .name =3D "Samsung S5PV210 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .has_divslot =3D 1, .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, @@ -2459,6 +2463,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_s= erial_drv_data =3D { .name =3D "Samsung Exynos UART", \ .type =3D TYPE_S3C6400, \ .port_type =3D PORT_S3C6400, \ + .iotype =3D UPIO_MEM, \ .has_divslot =3D 1, \ .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, \ .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, \ @@ -2519,6 +2524,7 @@ static const struct s3c24xx_serial_drv_data s5l_seria= l_drv_data =3D { .name =3D "Apple S5L UART", .type =3D TYPE_APPLE_S5L, .port_type =3D PORT_8250, + .iotype =3D UPIO_MEM, .fifosize =3D 16, .rx_fifomask =3D S3C2410_UFSTAT_RXMASK, .rx_fifoshift =3D S3C2410_UFSTAT_RXSHIFT, @@ -2548,6 +2554,7 @@ static const struct s3c24xx_serial_drv_data artpec8_s= erial_drv_data =3D { .name =3D "Axis ARTPEC-8 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .fifosize =3D 64, .has_divslot =3D 1, .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, --=20 2.43.0.472.g3155946c3a-goog