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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:29 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Sam Protsenko Subject: [PATCH v3 01/12] dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Date: Tue, 9 Jan 2024 12:58:03 +0000 Message-ID: <20240109125814.3691033-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0) clock management unit. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring --- v3: - rename the clock names to just "bus" and "ip" as per Rob's suggestion - collect Peter's R-b tag v2: - fix comments as per Sam's suggestion and collect his R-b tag - Rob's suggestion of renaming the clock-names to just "bus" and "ip" was not implemented as I felt it affects readability in the driver and consistency with other exynos clock drivers. I will happily update the names in the -rc phase if someone else has a stronger opinion than mine.=20 .../bindings/clock/google,gs101-clock.yaml | 25 +++++- include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index ca7fdada3ff2..03698cdecf7a 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,15 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 =20 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 =20 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 =20 "#clock-cells": const: 1 @@ -88,6 +89,26 @@ allOf: - const: bus - const: sss =20 + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0 bus clock (from CMU_T= OP) + - description: Connectivity Peripheral 0 IP clock (from CMU_TO= P) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings= /clock/google,gs101.h index 21adec22387c..64e6bdc6359c 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,85 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 =20 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:30 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Wolfram Sang , Rob Herring , Sam Protsenko Subject: [PATCH v3 02/12] dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible Date: Tue, 9 Jan 2024 12:58:04 +0000 Message-ID: <20240109125814.3691033-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add google,gs101-hsi2c dedicated compatible for representing I2C of Google GS101 SoC. Acked-by: Wolfram Sang Acked-by: Rob Herring Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- v3: collect Peter's tag v2: collect tags Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Docum= entation/devicetree/bindings/i2c/i2c-exynos5.yaml index df9c57bca2a8..cc8bba5537b9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,7 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - google,gs101-hsi2c - samsung,exynos850-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A5938F9C for ; Tue, 9 Jan 2024 12:58:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="r1Zuhkmu" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3368ae75082so2213349f8f.1 for ; Tue, 09 Jan 2024 04:58:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805113; x=1705409913; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JJrLSScx+Kg0xKGZsxHeMIlo3t4+N2J/9tXIuV54jXY=; b=r1Zuhkmu1pmgD6giY5NOzBkgd7BxQFqv+sTb/EczDD9fLsPtoM+HgPFCC7vR8F2f+n FYZ4n2HgBXbDkDPpWAEsW5J5hgGX6pmwYOBoegFrRRtTaE/Cesr+BCPd2y+NHl7Xq8rS DALtoAXpjgtM/eW6BAaDbMD14hbIWssJ1MliHJ4dP6kPAQgnaX5UgWIQcfHgCnqw89c9 x6yQz4f+1woEu72y6gO/Aq3sQOO77m0xyBLPKgXPV3LFplr/C7PBtczTZOVifLAL0qN0 +bRqi10bTjihyT0g4AaDjDM3HUDjYQVqzcBjLho7UCx0VQswaESbTf6WLygWlEChLIz8 t7Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805113; x=1705409913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JJrLSScx+Kg0xKGZsxHeMIlo3t4+N2J/9tXIuV54jXY=; b=Uo1h9DQ2DwQgoW3XqaNoncEnZjgWaEsjlQdgiexu1CgFNcUPpDvPs3wHlZ60448sQC 9MMBsblb2B0fK7V/s86ru3zzFVq6rPGQzC7QJAyz85aIAGkZttEJPzmXi0e54jV3UWaZ JyL1ayvvDxYpOUSMd8u+YwVAjvBDmZ+xuKO1iHaRXb9khAI4+TpVjnLq1qmdL9sJop9R X3Baq3hcCM+0zsTCZwopKlvuqItiGgxxIp7VJ3NnyolpNKkS7dx4V5fg562vFOkXdU5D dO7tfw0/fKJfXoMMwwVn1ShDqXBih8xomEzJ1zaQXU7YiLggq62+4DUTS6ZQT3/gwHIP idyg== X-Gm-Message-State: AOJu0YyaSP12YTrLpXRB19JPjpVv4yGqu7N/VdZf5Gq7i1Ai7uxnpuoI 2G+eOiVp+3i2ZMbD+Gv85IFXqHBb/JdYkw== X-Google-Smtp-Source: AGHT+IG99CWD951Q5V2toPvO6G1nhCnt1vNx3YMD3bUpgj+DUjA0ncxLc94mFArBzl45B4ITaRAVCg== X-Received: by 2002:a05:600c:1695:b0:40e:43d3:209d with SMTP id k21-20020a05600c169500b0040e43d3209dmr355287wmn.168.1704805112974; Tue, 09 Jan 2024 04:58:32 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:32 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Krzysztof Kozlowski Subject: [PATCH v3 03/12] dt-bindings: serial: samsung: do not allow reg-io-width for gs101 Date: Tue, 9 Jan 2024 12:58:05 +0000 Message-ID: <20240109125814.3691033-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All gs101 serial ports are restricted to 32-bit register accesses. This requirement will be inferred from the compatible. Do not allow the reg-io-width property for the google,gs101-uart compatible. Suggested-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko --- v3: collect Peter's R-b tag v2: new patch Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/D= ocumentation/devicetree/bindings/serial/samsung_uart.yaml index 133259ed3a34..0f0131026911 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -143,6 +143,8 @@ allOf: then: required: - samsung,uart-fifosize + properties: + reg-io-width: false =20 unevaluatedProperties: false =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E74B39853 for ; Tue, 9 Jan 2024 12:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gLfLjFPh" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3376f71fcbbso1359241f8f.1 for ; Tue, 09 Jan 2024 04:58:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805114; x=1705409914; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QYANYm/flTLm8ltfdyXSV/4KcEiWh8iO47/Oolwzemw=; b=gLfLjFPhX6ggGDo5EhGrBt3hCaHDWBGhH8hF+LhjGwFxHiqM1lSHB4r2oPVp2MZrln KfUUeGECf/l6QJz+doJ1rhJFBimbLc/59QLKyts5kVSieRKZsbyZcO0sR8aJ3nmerIyz R1fsO2QwF8IXXE57XWh66bj4iNmsiZYkUbJ2st35kgFfWXWjenlKz+AebI3wTRyGiulv J0skOOKKDL15dmfEoOxnPFPiZR2BoUVr9M9PViaMFQm+FvivKlilpbkZSiW4str9XL2y 6rge7LHqujNI4LWdOx2rbcSB93ssx7SxqjDVjPjZD1Y5Hp4UWqBNfsALVBoArtZBXPoH YkBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805114; x=1705409914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QYANYm/flTLm8ltfdyXSV/4KcEiWh8iO47/Oolwzemw=; b=wcM5GNLUPiPEiF/lK79ETQhhIDoDKWLFYY9KuR4Ljwz0kiB28mC0dyZ2X1kakJJLHg x0Z74Nzm3XLsHReakEx+WJkq4JLDyz2AlQ8ijDe5M/BTFYZ5NHKoPcqMueqQmKpECkTI hZwv0e2jra9TXFbaAKy8/DGtCEAMLv+SmC5KHY/1fE5zkF2O/CZgRkig1+476aIlZ9GY tEvZuOVObIAAxWdf1AWlcoohSBUqPT6Iv5tQtmvCOK6RiglQ3eloMhRRVmzqkil67A7r ZOYAv+G9rJHSZoEBo5kYV4TuBRCILVFNETJYqdbunqF6DWYa4mLhXCN6pz8BMFzsOezL FwRQ== X-Gm-Message-State: AOJu0YwFSOg94BQ69P+Nod+hlTHoIrj8d/QNV4FRniD9aIBBdmY8A1l7 g99/WFficWFwyCt1rlEeagh1mb2oukmfmQ== X-Google-Smtp-Source: AGHT+IGceZtkC0wZrtIHBAy7xlhr33Ldl9WFLcDfsJupgFjb103my2Ayh3FwlSnEldsW+8gESDuUsw== X-Received: by 2002:a5d:55c5:0:b0:337:5d0:1f1a with SMTP id i5-20020a5d55c5000000b0033705d01f1amr478794wrw.66.1704805114750; Tue, 09 Jan 2024 04:58:34 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:33 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 04/12] tty: serial: samsung: prepare for different IO types Date: Tue, 9 Jan 2024 12:58:06 +0000 Message-ID: <20240109125814.3691033-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. If using 8-bit register accesses, a SError Interrupt is raised causing the system unusable. Instead of specifying the reg-io-width =3D 4 everywhere, for each node, the requirement should be deduced from the compatible. Prepare the samsung tty driver to allow IO types different than UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all its 8 bits are exposed to uapi. We can't make NULL checks on it to verify if it's set, thus always set it from the driver's data. Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to emphasize that the iotype is an 8 bit mask. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko --- v3: - reposition the ``iotype`` member of ``struct s3c24xx_uart_info`` so that we reduce the struct's memory footprint. - change ``iotype`` to u8 to emphasize that it's a 8 bit mask and update the commit message explaining why. v2: new patch drivers/tty/serial/samsung_tty.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_= tty.c index 66bd6c090ace..ff646cddd3f8 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -84,6 +84,7 @@ struct s3c24xx_uart_info { unsigned long clksel_mask; unsigned long clksel_shift; unsigned long ucon_mask; + u8 iotype; =20 /* uart port features */ =20 @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int inde= x) { =20 spin_lock_init(&port->lock); =20 - port->iotype =3D UPIO_MEM; port->uartclk =3D 0; port->fifosize =3D 16; port->flags =3D UPF_BOOT_AUTOCONF; @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_devic= e *pdev) break; } =20 + ourport->port.iotype =3D ourport->info->iotype; + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); @@ -2401,6 +2403,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_s= erial_drv_data =3D { .name =3D "Samsung S3C6400 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .fifosize =3D 64, .has_divslot =3D 1, .rx_fifomask =3D S3C2440_UFSTAT_RXMASK, @@ -2430,6 +2433,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_s= erial_drv_data =3D { .name =3D "Samsung S5PV210 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .has_divslot =3D 1, .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, @@ -2459,6 +2463,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_s= erial_drv_data =3D { .name =3D "Samsung Exynos UART", \ .type =3D TYPE_S3C6400, \ .port_type =3D PORT_S3C6400, \ + .iotype =3D UPIO_MEM, \ .has_divslot =3D 1, \ .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, \ .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, \ @@ -2519,6 +2524,7 @@ static const struct s3c24xx_serial_drv_data s5l_seria= l_drv_data =3D { .name =3D "Apple S5L UART", .type =3D TYPE_APPLE_S5L, .port_type =3D PORT_8250, + .iotype =3D UPIO_MEM, .fifosize =3D 16, .rx_fifomask =3D S3C2410_UFSTAT_RXMASK, .rx_fifoshift =3D S3C2410_UFSTAT_RXSHIFT, @@ -2548,6 +2554,7 @@ static const struct s3c24xx_serial_drv_data artpec8_s= erial_drv_data =3D { .name =3D "Axis ARTPEC-8 UART", .type =3D TYPE_S3C6400, .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM, .fifosize =3D 64, .has_divslot =3D 1, .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E771A39AE4 for ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:35 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 05/12] tty: serial: samsung: set UPIO_MEM32 iotype for gs101 Date: Tue, 9 Jan 2024 12:58:07 +0000 Message-ID: <20240109125814.3691033-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. Instead of specifying the reg-io-width =3D 4 everywhere, for each node, the requirement should be deduced from the compatible. Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. Update the uart info name to be GS101 specific in order to differentiate from the other exynos platforms. All the other settings are not changed. exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data because the iotype restriction is gs101 specific and there was no other user of exynos_fifoszdt_serial_drv_data. Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko --- v3: collect Peter's R-b tag v2: new patch drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_= tty.c index ff646cddd3f8..a81b61953a28 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos8= 50_serial_drv_data =3D { .fifosize =3D { 256, 64, 64, 64 }, }; =20 -/* - * Common drv_data struct for platforms that specify samsung,uart-fifosize= in - * device tree. - */ -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_dat= a =3D { - EXYNOS_COMMON_SERIAL_DRV_DATA(), +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data =3D { + .info =3D { + .name =3D "Google GS101 UART", + .type =3D TYPE_S3C6400, + .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM32, + .has_divslot =3D 1, + .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, + .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull =3D S5PV210_UFSTAT_RXFULL, + .tx_fifofull =3D S5PV210_UFSTAT_TXFULL, + .tx_fifomask =3D S5PV210_UFSTAT_TXMASK, + .tx_fifoshift =3D S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel =3D S3C2410_UCON_CLKSEL0, + .num_clks =3D 1, + .clksel_mask =3D 0, + .clksel_shift =3D 0, + }, + .def_cfg =3D { + .ucon =3D S5PV210_UCON_DEFAULT, + .ufcon =3D S5PV210_UFCON_DEFAULT, + .has_fracval =3D 1, + }, + /* samsung,uart-fifosize must be specified in the device tree. */ .fifosize =3D { 0 }, }; =20 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) =20 #else #define EXYNOS4210_SERIAL_DRV_DATA NULL #define EXYNOS5433_SERIAL_DRV_DATA NULL #define EXYNOS850_SERIAL_DRV_DATA NULL -#define EXYNOS_FIFOSZDT_DRV_DATA NULL +#define GS101_SERIAL_DRV_DATA NULL #endif =20 #ifdef CONFIG_ARCH_APPLE @@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial= _driver_ids[] =3D { .driver_data =3D (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { .name =3D "gs101-uart", - .driver_data =3D (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, + .driver_data =3D (kernel_ulong_t)GS101_SERIAL_DRV_DATA, }, { }, }; @@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_matc= h[] =3D { { .compatible =3D "axis,artpec8-uart", .data =3D ARTPEC8_SERIAL_DRV_DATA }, { .compatible =3D "google,gs101-uart", - .data =3D EXYNOS_FIFOSZDT_DRV_DATA }, + .data =3D GS101_SERIAL_DRV_DATA }, {}, }; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:36 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 06/12] tty: serial: samsung: add gs101 earlycon support Date: Tue, 9 Jan 2024 12:58:08 +0000 Message-ID: <20240109125814.3691033-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Always set UPIO_MEM32 iotype for the gs101 earlycon. Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko --- v3: collect Peter's R-b tag v2: update commit message drivers/tty/serial/samsung_tty.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_= tty.c index a81b61953a28..fed50423b7c1 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2812,6 +2812,17 @@ OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-= uart", OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart", s5pv210_early_console_setup); =20 +static int __init gs101_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + /* gs101 always expects MMIO32 register accesses. */ + device->port.iotype =3D UPIO_MEM32; + + return s5pv210_early_console_setup(device, opt); +} + +OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup); + /* Apple S5L */ static int __init apple_s5l_early_console_setup(struct earlycon_device *de= vice, const char *opt) --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF0739FFD for ; Tue, 9 Jan 2024 12:58:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oXzaqxG9" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-3368ac0f74dso2280850f8f.0 for ; Tue, 09 Jan 2024 04:58:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805119; x=1705409919; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FGKe/uejLuieH8T/GQCGpHThkR46+sOmd5J3JMNr6mI=; b=oXzaqxG9uG4lsZQ1IPRQCxYXjVxLDhHfzTXHByDpWGN6RFYazTn41TcktySCyMRgbM Ze6uJ7qsWzQLCYfBNHAvY+JLhTOwE5nBzrM6Fvn95DoWqSfcAprSsIrWNRKZTNNEmLq5 T/9fxXAE/r+6HE+1dXoXHaemG7XInFAKZ3dm0JUgjy790uRPvps+X7XlsNxwlKhcQME/ i5pxW5srSJkteV/19zz6lG8h/n6unEIGS13UYWf7bTHIRMAgsjTlwUQJWQaYKcw1CgWn yrr2+Umm6ZbmnRCY0MddLrvfWmVXuXQOEa4E9EoIEBAeO5TXWp+H4wlqPKEVmkMpVhwx wpUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805119; x=1705409919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FGKe/uejLuieH8T/GQCGpHThkR46+sOmd5J3JMNr6mI=; b=TAEXGoCfa3eFOqDs/S4ZKnvtYaEqrSBzmLK43QQCAqoqJNBUnZ+ecg3NilH74foGtS hYrbksKGLalao4e1x80CGSFsyE4iPWfcC67mp0V6nD2kNZoHdq3ukTdmVgJ39CU5sumE jJqczQK4ZjFkyt2QgPp2zBcGbWNnol9gxOxmwXl/6iuSurhOI8JlL/tbXtF+NgmcDB/y 9fpvk8b5vqIadfMzL4JUAJbfegLVQa42zeJTPjJ4INHRUmf7rcnXDq1yurQAhbc5UNiE T+1liWvC90YVwa0eZjn5vpRZufGG7UHFSoLmJDDoFUelXTuLIprkTEWf7/xRTmap42e0 OP0g== X-Gm-Message-State: AOJu0YxJuaYtUdFLVea7Ipk+JNb4+Ml1KVuHA6bdBuhucL5jMwCqMs/z GgmZt4KhlvY9cuDojsAEt02Zt5QYY68mMA== X-Google-Smtp-Source: AGHT+IHAK311ONMrcWLZH0+MUfovI+JgV0ajsqmh+qx5AVosmD6BADeGmHZqkR5cJvU8vfZ2UWW5oA== X-Received: by 2002:a5d:4ed1:0:b0:337:4900:de74 with SMTP id s17-20020a5d4ed1000000b003374900de74mr724928wrv.51.1704805118996; Tue, 09 Jan 2024 04:58:38 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:38 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 07/12] clk: samsung: gs101: add support for cmu_peric0 Date: Tue, 9 Jan 2024 12:58:09 +0000 Message-ID: <20240109125814.3691033-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CMU_PERIC0 is the clock management unit used for the peric0 block which is used for USI and I3C. Add support for all cmu_peric0 clocks but CLK_GOUT_PERIC0_IP (not enough info in the datasheet). Few clocks are marked as critical because when either of them is disabled, the system hangs even if their clock parents are enabled. Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v3: - comply with the renamed cmu_peric0 clock name: "bus" - collect Peter's R-b tag v2: - update commit message - identify and mark critical clocks drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++ 1 file changed, 583 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 782993951fff..f3f0f5feb28d 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -20,6 +20,7 @@ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 @@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info = __initconst =3D { .clk_name =3D "bus", }; =20 +/* ---- CMU_PERIC0 -------------------------------------------------------= --- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK = 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPOR= T_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x2= 00c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK = 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x= 201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x= 2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0= x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0= x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0= x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0= x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0= x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0= x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x= 203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x= 2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x= 2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x= 2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x= 204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x= 2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x= 2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x= 2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2= 05c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2= 060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x= 2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x= 2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x= 206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x= 2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x= 2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x= 2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2= 07c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2= 080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2= 084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2= 088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2= 08c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2= 090 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2= 094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2= 098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x= 209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x= 20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2= 0a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x2= 0b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT= _CLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_= CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCL= KPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCL= KPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLK= PORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLK= PORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLK= PORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLK= PORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLK= PORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLK= PORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLK= PORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLK= PORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2= 0e8 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 +#define QCH_CON_GPC_PERIC0_QCH 0x3028 +#define QCH_CON_GPIO_PERIC0_QCH 0x302c +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 + +static const unsigned long peric0_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, + CLK_CON_BUF_CLKBUF_PERIC0_IP, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC0_TOP0_QCH_S1, + DMYQCH_CON_PERIC0_TOP0_QCH_S2, + DMYQCH_CON_PERIC0_TOP0_QCH_S3, + DMYQCH_CON_PERIC0_TOP0_QCH_S4, + DMYQCH_CON_PERIC0_TOP0_QCH_S5, + DMYQCH_CON_PERIC0_TOP0_QCH_S6, + DMYQCH_CON_PERIC0_TOP0_QCH_S7, + DMYQCH_CON_PERIC0_TOP0_QCH_S8, + PCH_CON_LHM_AXI_P_PERIC0_PCH, + QCH_CON_D_TZPC_PERIC0_QCH, + QCH_CON_GPC_PERIC0_QCH, + QCH_CON_GPIO_PERIC0_QCH, + QCH_CON_LHM_AXI_P_PERIC0_QCH, + QCH_CON_PERIC0_CMU_PERIC0_QCH, + QCH_CON_PERIC0_TOP0_QCH_I3C1, + QCH_CON_PERIC0_TOP0_QCH_I3C2, + QCH_CON_PERIC0_TOP0_QCH_I3C3, + QCH_CON_PERIC0_TOP0_QCH_I3C4, + QCH_CON_PERIC0_TOP0_QCH_I3C5, + QCH_CON_PERIC0_TOP0_QCH_I3C6, + QCH_CON_PERIC0_TOP0_QCH_I3C7, + QCH_CON_PERIC0_TOP0_QCH_I3C8, + QCH_CON_PERIC0_TOP0_QCH_USI1_USI, + QCH_CON_PERIC0_TOP0_QCH_USI2_USI, + QCH_CON_PERIC0_TOP0_QCH_USI3_USI, + QCH_CON_PERIC0_TOP0_QCH_USI4_USI, + QCH_CON_PERIC0_TOP0_QCH_USI5_USI, + QCH_CON_PERIC0_TOP0_QCH_USI6_USI, + QCH_CON_PERIC0_TOP0_QCH_USI7_USI, + QCH_CON_PERIC0_TOP0_QCH_USI8_USI, + QCH_CON_PERIC0_TOP1_QCH_USI0_UART, + QCH_CON_PERIC0_TOP1_QCH_USI14_UART, + QCH_CON_SYSREG_PERIC0_QCH, + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, +}; + +/* List of parent clocks for Muxes in CMU_PERIC0 */ +PNAME(mout_peric0_bus_user_p) =3D { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_i3c_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi0_uart_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_usi_user_p) =3D { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI0_UART_USER, + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI1_USI_USER, + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI2_USI_USER, + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI3_USI_USER, + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI4_USI_USER, + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI5_USI_USER, + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI6_USI_USER, + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI7_USI_USER, + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI8_USI_USER, + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst =3D { + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 3), + DIV(CLK_DOUT_PERIC0_USI0_UART, + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 3), + DIV(CLK_DOUT_PERIC0_USI14_USI, + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI1_USI, + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI2_USI, + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI3_USI, + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI4_USI, + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI5_USI, + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI6_USI, + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI7_USI, + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 3), + DIV(CLK_DOUT_PERIC0_USI8_USI, + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 3), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst =3D { + /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, + "gout_peric0_clk_peric0_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_= CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical= . */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_C= LK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CL= K, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst =3D { + .mux_clks =3D peric0_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(peric0_mux_clks), + .div_clks =3D peric0_div_clks, + .nr_div_clks =3D ARRAY_SIZE(peric0_div_clks), + .gate_clks =3D peric0_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids =3D CLKS_NR_PERIC0, + .clk_regs =3D peric0_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(peric0_clk_regs), + .clk_name =3D "bus", +}; + /* ---- platform_driver --------------------------------------------------= --- */ =20 static int __init gs101_cmu_probe(struct platform_device *pdev) @@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[]= =3D { }, { .compatible =3D "google,gs101-cmu-misc", .data =3D &misc_cmu_info, + }, { + .compatible =3D "google,gs101-cmu-peric0", + .data =3D &peric0_cmu_info, }, { }, }; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ACAB3A1CE for ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:39 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 08/12] arm64: dts: exynos: gs101: remove reg-io-width from serial Date: Tue, 9 Jan 2024 12:58:10 +0000 Message-ID: <20240109125814.3691033-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v3: collect Peter's R-b tag v2: new patch arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d838e3a7af6e..4e5f4c748906 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible =3D "google,gs101-uart"; reg =3D <0x10a00000 0xc0>; - reg-io-width =3D <4>; interrupts =3D ; clocks =3D <&dummy_clk 0>, <&dummy_clk 0>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8573A27E for ; Tue, 9 Jan 2024 12:58:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ambpe2Bt" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-336990fb8fbso2593018f8f.1 for ; Tue, 09 Jan 2024 04:58:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805122; x=1705409922; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pzoEE5PLx3WRPb0R+UBAoAAnvkztgFUqzYVVDoII6wM=; b=ambpe2Bt1HFcLigmRNc/avgV5KYS7g/LeDr+WXepIudCRCjrhJw3vDt9oztGVoQx+U 0w69EeEAebcBNxU2SEs7qtlcYtHNZADSEreHnefGRml1xSMo+oqw63SJ50j7dXneJNpr 78WY/mt/ICJvxmTBOCgJRXoKjN8Bg4fufr1zq4W9Ru7IQKI1hPXOudA/WiIjpGkQM4Xw RlfjfsdDDm5y81YocdxY3LWAaGaXlfgT51z+2RvSZkoEGAHPk7IPBl/DCvDPF3924zTF Waf7rkhvG60tdl9dzAw1MwaZg9EGLbvX9PMWnjcFq8M0bEpdENFnpOA3IFJC6+YqSc6x 3oaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805122; x=1705409922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pzoEE5PLx3WRPb0R+UBAoAAnvkztgFUqzYVVDoII6wM=; b=Z1EtPQlHUmK93jJPbCzOQl8FzcyuX8jtpIpooqmsotOIHc69eWo/w5mR+pFjSLPnS0 teu1Sbt4K/rOtTZfIyC4mjv0b7JcTXyYPKvzZvWWPk5UQKfojAs4p+DAs/dONkZORKN8 NUjmdnPnorqmLUlPqukzUsrAlzkoJ613SyugLL3dcqJvTkwqfqRmMGqZaGB9EPjkqirH 96uyUWsVH1dDBAJ5dRX54n6AR7hi+iFDoKlECvhnsqcvw035zwEO9zUGvjQLl9HpObWc dj1c4MabZDmlWftDDjrsQwJKPwa0KrXWTP1NyKg+uWZY7dHsE4rIRDSyawnxalBtI98r qd8w== X-Gm-Message-State: AOJu0YzxEXPRf5S2G8/CzfK2rfuhnDTGPFccqfj+jE4FsfBaFCrORweN 7mlCQCy6z0phzHEqkhGNBlkF1Cc/3wEsiA== X-Google-Smtp-Source: AGHT+IHnzxsCCm/HNg2HHqErus8BQHdl5sV5n8eEODKKGDLsEgoRlPc0eelp+pMKNq5BCbvjmbiXtg== X-Received: by 2002:adf:e941:0:b0:337:3f72:3de1 with SMTP id m1-20020adfe941000000b003373f723de1mr555630wrn.37.1704805121855; Tue, 09 Jan 2024 04:58:41 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:40 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Sam Protsenko Subject: [PATCH v3 09/12] arm64: dts: exynos: gs101: enable cmu-peric0 clock controller Date: Tue, 9 Jan 2024 12:58:11 +0000 Message-ID: <20240109125814.3691033-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- v3: - comply with the renamed cmu_peric0 clock names, "bus" and "ip" - collect Peter's R-b tag v2: collect Sam's R-b tag arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 4e5f4c748906..2d1344a202a9 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -339,6 +339,16 @@ ppi_cluster2: interrupt-partition-2 { }; }; =20 + cmu_peric0: clock-controller@10800000 { + compatible =3D "google,gs101-cmu-peric0"; + reg =3D <0x10800000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names =3D "oscclk", "bus", "ip"; + }; + sysreg_peric0: syscon@10820000 { compatible =3D "google,gs101-peric0-sysreg", "syscon"; reg =3D <0x10820000 0x10000>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8C653A8CD for ; Tue, 9 Jan 2024 12:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pC/BcBMY" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-3366e78d872so3139935f8f.3 for ; Tue, 09 Jan 2024 04:58:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805123; x=1705409923; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oaGDi0TjQr7Ub9IZJcZUMigpK3k/y+7+MgVg6Cn1eL0=; b=pC/BcBMYIhWTsStqZnIJ+IuXn3IWFerSRZ5sSr/NiuBfSTaE/2VfJO/DOXtWt3x9Z9 UZ5nHgVQ7gT4iK4F9iNIGIZSxTMWeF/uMa+a8SpbXf5rvHU1vQMx8j0bKlOckcnFVbLJ WsX6V8MMtVtDb6rketEwQbaumufCsvWBU9veUwX0Tfu7ZU9g5Cwl6VXye6YmHercG+9f 2hE4o0Odjx91AMOkrASc3QccERas79JOkYi+k1YZXKWW4kGG6ovxZ2sWnL+Rrw3oejVo M1byxpd3NkPH0wtKo+NUHqJJAxkY3vS1vPAnaow0xl9sygS6I0Y7iPCbnJzNilitDUwN 4CpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805123; x=1705409923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oaGDi0TjQr7Ub9IZJcZUMigpK3k/y+7+MgVg6Cn1eL0=; b=hclcdIrdGVDdAp+gToMjZW5USrxbEBzK8CsDlqkXYz1XBnGu1rpRoCkEEkCGfoRemE qfKQP7AiF4z8d00UnIMkliv4grGPVml3e6MGmGHVDgor0LMNFhI0c1IklKrHtVvI1iUx Y+DMpZXcRi0PYMEuP449AILOkdQkDjxdKzYG+zXoF7xdcyOR2EFeaCoiZIKVm2yCmCmj jbMs3mOQXfmXfDHwLHgLqjiIOY3Wozd9aw6n3VsOia8jSmq1kQcRejvaFjPJmUNPNH4j D3/rLSvtJBbGLG73tdUaXgj1GEJHPYbZNyMVD7nyI+QrGPtyYbve6fFmVyXdONMB6If7 0xWA== X-Gm-Message-State: AOJu0Yyv0R6sprMuU7fmOXoPvVgsE/E1FN0kxaxKSU184d3cg/goOlcf QTiZ/Wtl9QRJZ50SvYAu9ngptf8doPMntA== X-Google-Smtp-Source: AGHT+IGXM0B1+9MuwIA8MtMhZnmxjuNKArN4QKZBkCUKGYztf1jMYVytIdcENRsUzaSub8ZdLjr8Hg== X-Received: by 2002:adf:b357:0:b0:337:6277:91e9 with SMTP id k23-20020adfb357000000b00337627791e9mr241460wrd.82.1704805123201; Tue, 09 Jan 2024 04:58:43 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:42 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 10/12] arm64: dts: exynos: gs101: update USI UART to use peric0 clocks Date: Tue, 9 Jan 2024 12:58:12 +0000 Message-ID: <20240109125814.3691033-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v3: no change v2: identify and use gate clocks instead of divider clocks arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 2d1344a202a9..6aa25cc4676e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; =20 - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <12345>; - clock-output-names =3D "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -367,7 +359,8 @@ usi_uart: usi@10a000c0 { ranges; #address-cells =3D <1>; #size-cells =3D <1>; - clocks =3D <&dummy_clk>, <&dummy_clk>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names =3D "pclk", "ipclk"; samsung,sysreg =3D <&sysreg_peric0 0x1020>; samsung,mode =3D ; @@ -378,7 +371,8 @@ serial_0: serial@10a00000 { reg =3D <0x10a00000 0xc0>; interrupts =3D ; - clocks =3D <&dummy_clk 0>, <&dummy_clk 0>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names =3D "uart", "clk_uart_baud0"; samsung,uart-fifosize =3D <256>; status =3D "disabled"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97AAF3AC12 for ; Tue, 9 Jan 2024 12:58:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zel1JUE5" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40d5336986cso38057015e9.1 for ; Tue, 09 Jan 2024 04:58:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805125; x=1705409925; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ndzvAtIphV3/MRhlh+roY7v2JbqJAf5pGogAL74MKKE=; b=zel1JUE5ru8qcQGqnsj4tTRAdM9+TD4SX1nq7G6N1BrAlOgzeSRB0TDM9UgQqJCZA3 /9fNpwg5zfffOhhRTWolPNIeJmY203tvrfXe90brvA1zUKIrRNARMoHD04DYpwx+y8RX SYnc9HX0+G3jVRT5NRF4+64GMWmO91tGkIZZjRzA3KcHgh5usePeqU4rmeMOQL0mC1Eh 380cO9ot9brLmLcAVrlOEs8m0uJlACq3MMRWvyaKevi+PwWIZHB4IkSrgb5rOLeKQs9U THwoVqS/9KsZdjl19UgjgHLaKUOI5jffGrKRcmjckGg3jpIKnmma0vxYfYL8h8kqupZm 64NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805125; x=1705409925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ndzvAtIphV3/MRhlh+roY7v2JbqJAf5pGogAL74MKKE=; b=DVyQ14DKOJyRccvLowHuDfay8uDpDljMYkPg85EZeprzPUoEV1dbjRIWd+UCMnbDaM 2zeZ7Y2l+rms+AoMp3MG/HJ+ac0fa5VNJlDAJbW9V4hxtLoFeYl1i6SjHlsWuYNLLJgz Sf8aj4lajFBxqvoBKX5slaZ+OttvQXJA/7LC5yKukofpG8pyWFgfOsceoRMHtqwYog4V 4BZnuJ4xcCkQod31kFg5KbVRinbQfkLUR6FQfYYn9PJINxhlXKeUby2Z0ziJiyQzXUds oCztXkmteUhO2QkZDRO3wszvmoXwTkc2zww8uSDeFYT+8iMOrX0umIO/gsQgTEODsaRO A2Zg== X-Gm-Message-State: AOJu0YxjE8qW+BGwtjfwauHOP5Zt5xcLQ1BdA37wiWEpDJCJjq2k50NU 4OgRGEWFn4jluPOPHC/lGpLHDeaKcbdG9w== X-Google-Smtp-Source: AGHT+IEXrqUo3X98KfIVdC+0JSNna7+jX0vhQXoPTaTb9u2LAvTigz3QPZnlngtgAikkgNuhljk1Dw== X-Received: by 2002:a05:600c:4f09:b0:40e:5057:91f2 with SMTP id l9-20020a05600c4f0900b0040e505791f2mr401494wmq.115.1704805125039; Tue, 09 Jan 2024 04:58:45 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:43 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v3 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration Date: Tue, 9 Jan 2024 12:58:13 +0000 Message-ID: <20240109125814.3691033-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v3: reorder usi8 clock order (thanks Andre'!). Did not make any difference at testing as the usi driver treats the clocks in bulk. v2: - identify and use gate clocks instead of dividers - move cells and pinctrl properties from dts to dtsi - move IRQ type constant on the previous line arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 6aa25cc4676e..f14a24628d04 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { interrupts =3D ; }; =20 + usi8: usi@109700c0 { + compatible =3D "google,gs101-usi", + "samsung,exynos850-usi"; + reg =3D <0x109700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&sysreg_peric0 0x101c>; + status =3D "disabled"; + + hsi2c_8: i2c@10970000 { + compatible =3D "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10970000 0xc0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hsi2c8_bus>; + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + status =3D "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible =3D "google,gs101-usi", "samsung,exynos850-usi"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Dec 26 05:08:37 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0293C3B28F for ; Tue, 9 Jan 2024 12:58:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jvboTT8H" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40e43fb2659so23429065e9.1 for ; Tue, 09 Jan 2024 04:58:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704805126; x=1705409926; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=66WHfoChmjF44TpuZe1F+scHybHenf1Nb7ZkRVtSfIY=; b=jvboTT8HDIIbPBJx1k1H6z2qsvXcBmMSE75MdksfIdcMvurkDML9c3BrdRy6wKiYf4 37Yl0qte142lNSU0zGWV4AQR6d+UaRSmHa9UINdfrRy8ecbSoFnXJ4MLRZDxjV7TVHZh HjhdkkyXozC78rPMvPTIJdVCa0t9olnBOzYcIOQ/WaesBxn9vErQaOmLXxsY2fpO9PBI nCGTfIsMjxzoSZhk9LvgseeJElpXgCP34aPrS+BvZvFpofmXzE+fYYEyFziS7J0j/3gL NzXmw2gSJhoKuN/5UzNrJAvO45A+wHz3xQ7xnfVe6b2pSh7rKSyiC7s4GLp6UV9BgM64 WOxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704805126; x=1705409926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=66WHfoChmjF44TpuZe1F+scHybHenf1Nb7ZkRVtSfIY=; b=B5Itw1I1NJVT1J5D6OzhcrykhTRv6OVnXvg4O9CoDbxNBX/EfnkfELbfQSi+eAdZgZ GGX7yOuGqR158pFBNtk0e33RR3MC/x94IQNRMJ4iUUy3dhoFx6ZZu5YjL9H5hR5Y0U5g SBKLMj3iUQ+g32ApXXMHSDc3GVsKwZg0HjcKYHw1faInDLl8cE3hwdT7pYcEVOSvBVQt Gb6X8Q8WPlfEpZI2RiPvkesBvYCJcswCCS2qdCXGigXw7CUjnGuv3ij4px1Z776ViMf2 mElmrGZvhNbzGCAKS8AQzMeO65s1m8MLwLFGP8F6haXsfs2NeIkyf/35st32K0RMFUzz nuBg== X-Gm-Message-State: AOJu0YwxVdu2JWWFq43GnDfinNaFcuLzAwBu5CeR9IlhcG66ASunFnCU oBZoa+3m9HAHVyDesZNu6hSsq8R2lRKBQA== X-Google-Smtp-Source: AGHT+IHTeV8EyfLOccPihdbXSpbOQ08P0ffNZMnT6S1UpNLyuVQRXyqsi0Qq1eRPCQMkBY5K2Eql1A== X-Received: by 2002:a05:600c:538d:b0:40e:41f2:6d74 with SMTP id hg13-20020a05600c538d00b0040e41f26d74mr2481510wmb.67.1704805126502; Tue, 09 Jan 2024 04:58:46 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id cw16-20020a056000091000b0033753a61e96sm2351302wrb.108.2024.01.09.04.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 04:58:45 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Sam Protsenko Subject: [PATCH v3 12/12] arm64: dts: exynos: gs101: enable eeprom on gs101-oriole Date: Tue, 9 Jan 2024 12:58:14 +0000 Message-ID: <20240109125814.3691033-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240109125814.3691033-1-tudor.ambarus@linaro.org> References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus --- v3: collect Peter's R-b tag v2: - move cells and pinctrls properties to dtsi - collect Sam's R-b arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm6= 4/boot/dts/exynos/google/gs101-oriole.dts index 4a71f752200d..cb4d17339b6b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -63,6 +63,15 @@ &ext_200m { clock-frequency =3D <200000000>; }; =20 +&hsi2c_8 { + status =3D "okay"; + + eeprom: eeprom@50 { + compatible =3D "atmel,24c08"; + reg =3D <0x50>; + }; +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins =3D "gpa7-3"; @@ -99,6 +108,11 @@ &usi_uart { status =3D "okay"; }; =20 +&usi8 { + samsung,mode =3D ; + status =3D "okay"; +}; + &watchdog_cl0 { timeout-sec =3D <30>; status =3D "okay"; --=20 2.43.0.472.g3155946c3a-goog