From nobody Fri Dec 26 09:16:44 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEEF629427; Tue, 9 Jan 2024 08:52:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="MC2Elf6V" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40924Sn5006375; Tue, 9 Jan 2024 09:52:03 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=iSjyXXBlLU8CmpUXVSZCKnI2Y7L6CFxxoTsOMTlPK98=; b=MC 2Elf6V9cwoMlVlIcT7Ks2GnvDP9ugzsDh22nsD2vI7LTWTbS94Zz8lwCWc1lszRT qgmMaTcwEiyXrO1prgLJEwxnp7lUsTeX50m43pgiv00bJ0kJL3EbAtLDHRpVUVoH IaoKog5Qzody/PMlkBEDXG/uTvWxynEmQr0r21WYKct6Cny/sMabRlletkhe43Rr jQdvCqVZoQnHWsOPOKiDL8GYN6T2M79aldlExoKHd5Q9KCqBFTAmL3c1HcTR2QJR qOYxM5hdSCjX8U4aXqeqPha550wgzGHhOzin7DhS4D5BDwjjsbUJQmBbA1OwGbUY f/b0qRIQnJg5RyVjAeTg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vexmfaetv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jan 2024 09:52:03 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3B85610004A; Tue, 9 Jan 2024 09:52:03 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2F9B322FA2D; Tue, 9 Jan 2024 09:52:03 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 9 Jan 2024 09:52:02 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v6 4/5] arm64: dts: st: add video decoder support to stm32mp255 Date: Tue, 9 Jan 2024 09:51:54 +0100 Message-ID: <20240109085155.252358-5-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240109085155.252358-1-hugues.fruchet@foss.st.com> References: <20240109085155.252358-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add VDEC hardware video decoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 96859d098ef8..8fc7e9199499 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ ck_icn_ls_mcu: ck-icn-ls-mcu { compatible =3D "fixed-clock"; clock-frequency =3D <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index e6fa596211f5..aea5096dac3c 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,4 +6,14 @@ #include "stm32mp253.dtsi" =20 / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible =3D "st,stm32mp25-vdec"; + reg =3D <0x480d0000 0x3c8>; + interrupts =3D ; + clocks =3D <&ck_icn_p_vdec>; + }; + }; + }; }; --=20 2.25.1