From nobody Fri Dec 26 09:15:49 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF31A2E62C; Tue, 9 Jan 2024 08:52:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="3r3PAkpO" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4091joRx022003; Tue, 9 Jan 2024 09:52:02 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=wPdYLi/Hw9vH2EqET3gxVUt2jy1fPUhcjP6s24nSXYA=; b=3r 3PAkpOSFgaX9ndEux/KhxUkqUoVavDZ8bbjCCf/zCv99o4Q99knUN4FBfB+VEpsd uxRiruIt1bIPEqJFvpErnHyq0bcSr8FVkTsafgrD6Ff3e/+2YBMpNKYJJ2qMEakk 4J6UtVST1bQcvx/pHKpicCuMDWph9DJQtS75eqcVhsMVG6D4PSNDjU2qvcTi0VPD NTbB0d412K9SDSSWQAJk7pPnhip/hfV/EJd1ag7JOKjlpn0OhinrAK2rfwVUy7cb uGLxcaObVxzBD0E7snmAsWXJaH+6cU79abJ7ADh5Y0JpX1pGP36kSnSIz4VHHIAd zXzYuB52ODcxwM4tCcdQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vfha4gham-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jan 2024 09:52:02 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 60C32100045; Tue, 9 Jan 2024 09:52:02 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 538D622FA51; Tue, 9 Jan 2024 09:52:02 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 9 Jan 2024 09:52:02 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [PATCH v6 3/5] media: hantro: add support for STM32MP25 VENC Date: Tue, 9 Jan 2024 09:51:53 +0100 Message-ID: <20240109085155.252358-4-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240109085155.252358-1-hugues.fruchet@foss.st.com> References: <20240109085155.252358-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add support for STM32MP25 VENC video hardware encoder. Support of JPEG encoding. VENC has its own reset/clock/irq. Reviewed-by: Nicolas Dufresne Signed-off-by: Hugues Fruchet --- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vpu_hw.c | 90 +++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/medi= a/platform/verisilicon/hantro_drv.c index 2db27c333924..4d97a8ac03de 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -736,6 +736,7 @@ static const struct of_device_id of_hantro_match[] =3D { #endif #ifdef CONFIG_VIDEO_HANTRO_STM32MP25 { .compatible =3D "st,stm32mp25-vdec", .data =3D &stm32mp25_vdec_variant,= }, + { .compatible =3D "st,stm32mp25-venc", .data =3D &stm32mp25_venc_variant,= }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media= /platform/verisilicon/hantro_hw.h index b7eccc1a96fc..70c72e9d11d5 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -407,6 +407,7 @@ extern const struct hantro_variant rk3588_vpu981_varian= t; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_variant stm32mp25_vdec_variant; +extern const struct hantro_variant stm32mp25_venc_variant; =20 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/driver= s/media/platform/verisilicon/stm32mp25_vpu_hw.c index 6af6edcb6650..833821120b20 100644 --- a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c +++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c @@ -9,6 +9,8 @@ */ =20 #include "hantro.h" +#include "hantro_jpeg.h" +#include "hantro_h1_regs.h" =20 /* * Supported formats. @@ -55,6 +57,67 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] =3D= { }, }; =20 +static const struct hantro_fmt stm32mp25_venc_fmts[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_YUV420M, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUV420P, + }, + { + .fourcc =3D V4L2_PIX_FMT_NV12M, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUV420SP, + }, + { + .fourcc =3D V4L2_PIX_FMT_YUYV, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_YUYV422, + }, + { + .fourcc =3D V4L2_PIX_FMT_UYVY, + .codec_mode =3D HANTRO_MODE_NONE, + .enc_fmt =3D ROCKCHIP_VPU_ENC_FMT_UYVY422, + }, + { + .fourcc =3D V4L2_PIX_FMT_JPEG, + .codec_mode =3D HANTRO_MODE_JPEG_ENC, + .max_depth =3D 2, + .header_size =3D JPEG_HEADER_SIZE, + .frmsize =3D { + .min_width =3D 96, + .max_width =3D FMT_4K_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D 96, + .max_height =3D FMT_4K_HEIGHT, + .step_height =3D MB_DIM, + }, + }, +}; + +static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu =3D dev_id; + enum vb2_buffer_state state; + u32 status; + + status =3D vepu_read(vpu, H1_REG_INTERRUPT); + state =3D (status & H1_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static void stm32mp25_venc_reset(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu =3D ctx->dev; + + reset_control_reset(vpu->resets); +} + /* * Supported codec ops. */ @@ -74,6 +137,14 @@ static const struct hantro_codec_ops stm32mp25_vdec_cod= ec_ops[] =3D { }, }; =20 +static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] =3D { + [HANTRO_MODE_JPEG_ENC] =3D { + .run =3D hantro_h1_jpeg_enc_run, + .reset =3D stm32mp25_venc_reset, + .done =3D hantro_h1_jpeg_enc_done, + }, +}; + /* * Variants. */ @@ -94,3 +165,22 @@ const struct hantro_variant stm32mp25_vdec_variant =3D { .clk_names =3D stm32mp25_vdec_clk_names, .num_clocks =3D ARRAY_SIZE(stm32mp25_vdec_clk_names), }; + +static const struct hantro_irq stm32mp25_venc_irqs[] =3D { + { "venc", stm32mp25_venc_irq }, +}; + +static const char * const stm32mp25_venc_clk_names[] =3D { + "venc-clk" +}; + +const struct hantro_variant stm32mp25_venc_variant =3D { + .enc_fmts =3D stm32mp25_venc_fmts, + .num_enc_fmts =3D ARRAY_SIZE(stm32mp25_venc_fmts), + .codec =3D HANTRO_JPEG_ENCODER, + .codec_ops =3D stm32mp25_venc_codec_ops, + .irqs =3D stm32mp25_venc_irqs, + .num_irqs =3D ARRAY_SIZE(stm32mp25_venc_irqs), + .clk_names =3D stm32mp25_venc_clk_names, + .num_clocks =3D ARRAY_SIZE(stm32mp25_venc_clk_names) +}; --=20 2.25.1