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[84.110.53.106]) by smtp.gmail.com with ESMTPSA id c15-20020a056000104f00b00336cbbf2e0fsm1587409wrx.27.2024.01.08.23.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 23:27:08 -0800 (PST) From: SilverPlate3 To: forest@alittletooquiet.net, gregkh@linuxfoundation.org Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, SilverPlate3 Subject: [PATCH] Staging: vt6655: Fix sparse warning. Restricted cast. Date: Tue, 9 Jan 2024 09:27:04 +0200 Message-Id: <20240109072704.44582-1-arielsilver77@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Running 'make M=3Ddrivers/staging/vt6655 C=3D2' causes sparse to generate few warnings. This patch fixes the following warnings by ensuring le64_to_cpu handles only __le64 values, thus dismissing chances of bad endianness. * drivers/staging/vt6655/card.c:302:45: warning: cast to restricted __le64 * drivers/staging/vt6655/card.c:336:23: warning: cast to restricted __le64 * drivers/staging/vt6655/card.c:804:23: warning: cast to restricted __le64 * drivers/staging/vt6655/card.c:831:18: warning: cast to restricted __le64 Signed-off-by: Ariel Silver --- drivers/staging/vt6655/card.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index 350ab8f3778a..5dc2200466b7 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -292,6 +292,7 @@ bool card_update_tsf(struct vnt_private *priv, unsigned= char rx_rate, { u64 local_tsf; u64 qwTSFOffset =3D 0; + __le64 le_qwTSFOffset =3D 0; =20 local_tsf =3D vt6655_get_current_tsf(priv); =20 @@ -299,7 +300,8 @@ bool card_update_tsf(struct vnt_private *priv, unsigned= char rx_rate, qwTSFOffset =3D CARDqGetTSFOffset(rx_rate, qwBSSTimestamp, local_tsf); /* adjust TSF, HW's TSF add TSF Offset reg */ - qwTSFOffset =3D le64_to_cpu(qwTSFOffset); + le_qwTSFOffset =3D cpu_to_le64(qwTSFOffset); + qwTSFOffset =3D le64_to_cpu(le_qwTSFOffset); iowrite32((u32)qwTSFOffset, priv->port_offset + MAC_REG_TSFOFST); iowrite32((u32)(qwTSFOffset >> 32), priv->port_offset + MAC_REG_TSFOFST = + 4); vt6655_mac_reg_bits_on(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TSFSYNC= EN); @@ -324,6 +326,7 @@ bool CARDbSetBeaconPeriod(struct vnt_private *priv, unsigned short wBeaconInterval) { u64 qwNextTBTT; + __le64 le_qwNextTBTT =3D 0; =20 qwNextTBTT =3D vt6655_get_current_tsf(priv); /* Get Local TSF counter */ =20 @@ -333,7 +336,8 @@ bool CARDbSetBeaconPeriod(struct vnt_private *priv, iowrite16(wBeaconInterval, priv->port_offset + MAC_REG_BI); priv->wBeaconInterval =3D wBeaconInterval; /* Set NextTBTT */ - qwNextTBTT =3D le64_to_cpu(qwNextTBTT); + le_qwNextTBTT =3D cpu_to_le64(qwNextTBTT); + qwNextTBTT =3D le64_to_cpu(le_qwNextTBTT); iowrite32((u32)qwNextTBTT, priv->port_offset + MAC_REG_NEXTTBTT); iowrite32((u32)(qwNextTBTT >> 32), priv->port_offset + MAC_REG_NEXTTBTT += 4); vt6655_mac_reg_bits_on(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TBTTSYNC= EN); @@ -796,12 +800,14 @@ void CARDvSetFirstNextTBTT(struct vnt_private *priv, { void __iomem *iobase =3D priv->port_offset; u64 qwNextTBTT; + __le64 le_qwNextTBTT =3D 0; =20 qwNextTBTT =3D vt6655_get_current_tsf(priv); /* Get Local TSF counter */ =20 qwNextTBTT =3D CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval); /* Set NextTBTT */ - qwNextTBTT =3D le64_to_cpu(qwNextTBTT); + le_qwNextTBTT =3D cpu_to_le64(qwNextTBTT); + qwNextTBTT =3D le64_to_cpu(le_qwNextTBTT); iowrite32((u32)qwNextTBTT, iobase + MAC_REG_NEXTTBTT); iowrite32((u32)(qwNextTBTT >> 32), iobase + MAC_REG_NEXTTBTT + 4); vt6655_mac_reg_bits_on(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); @@ -825,10 +831,12 @@ void CARDvUpdateNextTBTT(struct vnt_private *priv, u6= 4 qwTSF, unsigned short wBeaconInterval) { void __iomem *iobase =3D priv->port_offset; + __le64 le_qwTSF =3D 0; =20 qwTSF =3D CARDqGetNextTBTT(qwTSF, wBeaconInterval); /* Set NextTBTT */ - qwTSF =3D le64_to_cpu(qwTSF); + le_qwTSF =3D cpu_to_le64(qwTSF); + qwTSF =3D le64_to_cpu(le_qwTSF); iowrite32((u32)qwTSF, iobase + MAC_REG_NEXTTBTT); iowrite32((u32)(qwTSF >> 32), iobase + MAC_REG_NEXTTBTT + 4); vt6655_mac_reg_bits_on(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); --=20 2.25.1