From nobody Fri Dec 26 05:10:13 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4277E39FFC for ; Tue, 9 Jan 2024 16:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lvQCD/ig" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-3367a304091so2951656f8f.3 for ; Tue, 09 Jan 2024 08:06:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704816361; x=1705421161; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xrDQaKaLoC6HAA7NXSJEUsah06CyH+NV6eUOiFE3MbA=; b=lvQCD/igmHFnhOcBs88OExsrD0SjNSXZNH7oIjHcYJZMDPQDi4E219lgFeLkvmdDXL Q3s4c9UWIki7gPsOluzB+knR5PSBE76isu/9tAHvKHP1oV1o0lQgHrZ2pdd8tuzxiFzH GF1qNPmsD7l68icQB93zOxhaLctnmmU2jku+aEiJw8cxSLO9kmDkpm91DNI84SAw8tIh Ya4KyBS08gIHEoq8gbXGGFYpeIVPs1RpmsGVZr8ncrcSetowl9XY0thSzrcKtLoAvnFw KpRTPWBAQvKYIwAOtrZwjyx6s6L1tu+ROxMJQok5tihfwODyUvNevWTD6SWToReGvHrO wUxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704816361; x=1705421161; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xrDQaKaLoC6HAA7NXSJEUsah06CyH+NV6eUOiFE3MbA=; b=gnGLgaM8Cu476YfgdJyBoycA9zVD0sXKQsoxTcm/X25C5pL5dTcwQLgIOLEuJ1HX+d Z/wkwyC0F9gEv+prOhb7Si5yhP0CiNHdzbZFeLnkq9OPZn4ONFQttUhMOZOhArPppDO+ 2Ao5KKLIxJQFfPiD7pJXD5Wc4A8f+9w2Ib2js+oZAqw8m2jYMTlOeKtD/nERlVpri2uo SWgoUcu2LRyHhXzaH/0r66zVm1Pdlda266QoszzIQ6gkLUtYamyFm9KjogZklVXw34Lb uCnsnF8+u0lGGSgR5J52Tj+HwyqfpzOq7OPxOpqQMEA7KcSQGYTsOS/eNckjQvla1n8K YnZQ== X-Gm-Message-State: AOJu0YxTS40GwiGHJe34QmfrjngMPVZTOhNKRz2q3eTz9kaCY1SvwEui VFMFLmYZLkEENsJWwGTtYjbyy7QwKgLHyg== X-Google-Smtp-Source: AGHT+IEo9SoUdLbLfwlLwyHstgbrprERFZV7lGv3y66ty2G1w7fkWhp9KLqC1WLb4FV7k4fTE6f1ig== X-Received: by 2002:a5d:6d84:0:b0:337:5554:9f71 with SMTP id l4-20020a5d6d84000000b0033755549f71mr470750wrs.28.1704816361498; Tue, 09 Jan 2024 08:06:01 -0800 (PST) Received: from [127.0.1.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id z8-20020adfec88000000b0033762d4ad5asm2726490wrn.81.2024.01.09.08.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 08:06:01 -0800 (PST) From: Bryan O'Donoghue Date: Tue, 09 Jan 2024 16:06:02 +0000 Subject: [PATCH v3 1/4] dt-bindings: i2c: qcom-cci: Document sc8280xp compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-1-b8e3a74a6e6a@linaro.org> References: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> In-Reply-To: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-4e032 Add sc8280xp compatible consistent with recent CAMSS CCI interfaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue --- .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 8386cfe21532..369d72882874 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - qcom,sc7280-cci + - qcom,sc8280xp-cci - qcom,sdm845-cci - qcom,sm6350-cci - qcom,sm8250-cci @@ -176,6 +177,24 @@ allOf: - const: cci - const: cci_src =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-cci + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: camnoc_axi + - const: slow_ahb_src + - const: cpas_ahb + - const: cci + additionalProperties: false =20 examples: --=20 2.42.0 From nobody Fri Dec 26 05:10:13 2025 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B9D3A1BF for ; Tue, 9 Jan 2024 16:06:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fzpYD77k" Received: by mail-lj1-f174.google.com with SMTP id 38308e7fff4ca-2cd1232a2c7so36453061fa.0 for ; Tue, 09 Jan 2024 08:06:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704816363; x=1705421163; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=g1tGMZkZ9pe+vGPxtPhPtPgSrfYlIn/2+AsR9dEH15s=; b=fzpYD77kRjhib8K0xOGcrtInHCD8kZ/osHzZHpP88L6FYRraY1wJpDmWmdKplewuNK p+zbsENoIxXr0+knIOEkuQIGCgOJBKTdqjgAu8fdYJSsnlNSVVQbYPHa6dq5yCcbaRXA L70yM5wNSWlGi3V71zLMlYWPiV5lXszgc1xRuVFsM2YzeCoCWqO1AJbLlSGGM37zq/ia M3RIMIcRfRie1KvUS0j7hH3zSkpcr8KBSPTWjFQYz7xfRxLul/uoapgsJKzNObH7i1nX JboQYhUNycZL7pB+8lV1OEkPYdk7jFBwKtwDeiqGrkxE9ESrF9LF59UCu3M3EtCq1QPY f/nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704816363; x=1705421163; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g1tGMZkZ9pe+vGPxtPhPtPgSrfYlIn/2+AsR9dEH15s=; b=YmddtH99SvLjjEOsm6M7uva79qT+IQdrfHeUKsgQKzvP7UlsLu7bMbxwpGsiZuFVk7 yFCNPf4lFz4xBdhFJDDJkot0zVlAu0ClZMagT5hzRxQQTYckWfcwpuhQViz3L1EAjCS6 fs1JoPugu5WVJQntgGNmA+aMILWt6QAAb5X3iyxFOAtRI8EHP7IlxKxVcbqNrvetct2E v/RuRMIWsNEutf6B6t7GSFH0Few0//Ac0H54TsWvJttZtr9MH/U9tjoBZAKILL1DGjGt PI4HSPFy4NRFwGeNu7g6rlZPZoZ5x6hLvmmSfdkwFS/NEPR9tv5d62kVXxjqdp7o4ivn NvVQ== X-Gm-Message-State: AOJu0YzV79LToevCZ+VVebjRky8Wg20Ff2Mw9FiEooGG/nesels6izdt mHD0EJu98lkusl9fB1JrnG1kvfAK4yAsfQ== X-Google-Smtp-Source: AGHT+IFvciOAMfrfvDN2a0oCF6yyziLqBt1BOMXMtA48GzJJA5Jej+wld+9f3gSl42LoFxUaGjQ7Tg== X-Received: by 2002:a2e:8751:0:b0:2cd:1efa:d27a with SMTP id q17-20020a2e8751000000b002cd1efad27amr2293605ljj.106.1704816362648; Tue, 09 Jan 2024 08:06:02 -0800 (PST) Received: from [127.0.1.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id z8-20020adfec88000000b0033762d4ad5asm2726490wrn.81.2024.01.09.08.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 08:06:02 -0800 (PST) From: Bryan O'Donoghue Date: Tue, 09 Jan 2024 16:06:03 +0000 Subject: [PATCH v3 2/4] dt-bindings: media: camss: Add qcom,sc8280xp-camss binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-2-b8e3a74a6e6a@linaro.org> References: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> In-Reply-To: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-4e032 Add bindings for qcom,sc8280xp-camss in order to support the camera subsystem for sc8280xp as found in the Lenovo x13s Laptop. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/qcom,sc8280xp-camss.yaml | 512 +++++++++++++++++= ++++ 1 file changed, 512 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.ya= ml b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml new file mode 100644 index 000000000000..c0bc31709873 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml @@ -0,0 +1,512 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sc8280xp-camss + + clocks: + maxItems: 40 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe3_axi + - const: vfe3 + - const: vfe3_cphy_rx + - const: vfe3_csid + - const: vfe_lite0 + - const: vfe_lite0_cphy_rx + - const: vfe_lite0_csid + - const: vfe_lite1 + - const: vfe_lite1_cphy_rx + - const: vfe_lite1_csid + - const: vfe_lite2 + - const: vfe_lite2_cphy_rx + - const: vfe_lite2_csid + - const: vfe_lite3 + - const: vfe_lite3_cphy_rx + - const: vfe_lite3_csid + - const: gcc_axi_hf + - const: gcc_axi_sf + + interrupts: + maxItems: 20 + + interrupt-names: + items: + - const: csid1_lite + - const: vfe_lite1 + - const: csiphy3 + - const: csid0 + - const: vfe0 + - const: csid1 + - const: vfe1 + - const: csid0_lite + - const: vfe_lite0 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csid2 + - const: vfe2 + - const: csid3_lite + - const: csid2_lite + - const: vfe_lite3 + - const: vfe_lite2 + - const: csid3 + - const: vfe3 + + iommus: + maxItems: 16 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_mnoc + - const: cam_sf_icp_mnoc + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: IFE3 GDSC - Image Front End, Global Distributed Switc= h Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed = Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: ife3 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + reg: + maxItems: 20 + + reg-names: + items: + - const: csiphy2 + - const: csiphy3 + - const: csiphy0 + - const: csiphy1 + - const: vfe0 + - const: csid0 + - const: vfe1 + - const: csid1 + - const: vfe2 + - const: csid2 + - const: vfe_lite0 + - const: csid0_lite + - const: vfe_lite1 + - const: csid1_lite + - const: vfe_lite2 + - const: csid2_lite + - const: vfe_lite3 + - const: csid3_lite + - const: vfe3 + - const: csid3 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + camss: camss@ac5a000 { + compatible =3D "qcom,sc8280xp-camss"; + + reg =3D <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + + reg-names =3D "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + vdda-phy-supply =3D <&vreg_l6d>; + vdda-pll-supply =3D <&vreg_l4d>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains =3D <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names =3D "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>; + + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe3_axi", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf"; + + + iommus =3D <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC 0 &config_noc SL= AVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_E= BI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_E= BI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_= EBI1 0>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + csiphy_ep0: endpoint@0 { + reg =3D <0>; + clock-lanes =3D <7>; + data-lanes =3D <0 1>; + remote-endpoint =3D <&sensor_ep>; + }; + }; + }; + }; + }; --=20 2.42.0 From nobody Fri Dec 26 05:10:13 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663AF3A1DC for ; Tue, 9 Jan 2024 16:06:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org 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Tue, 09 Jan 2024 08:06:03 -0800 (PST) Received: from [127.0.1.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id z8-20020adfec88000000b0033762d4ad5asm2726490wrn.81.2024.01.09.08.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 08:06:03 -0800 (PST) From: Bryan O'Donoghue Date: Tue, 09 Jan 2024 16:06:04 +0000 Subject: [PATCH v3 3/4] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-3-b8e3a74a6e6a@linaro.org> References: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> In-Reply-To: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 sc8280xp has four Camera Control Interface (CCI) blocks which pinout to two I2C master controllers for each CCI. The CCI I2C pins are not muxed so we define them in the dtsi. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 307 +++++++++++++++++++++++++++++= ++++ 1 file changed, 307 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index febf28356ff8..f48dfa5e5f36 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3451,6 +3451,169 @@ usb_1_role_switch: endpoint { }; }; =20 + cci0: cci@ac4a000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4a000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci0_default>; + pinctrl-1 =3D <&cci0_sleep>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4b000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci1_default>; + pinctrl-1 =3D <&cci1_sleep>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac4c000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4c000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci2_default>; + pinctrl-1 =3D <&cci2_sleep>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci3: cci@ac4d000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4d000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_3_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&cci3_default>; + pinctrl-1 =3D <&cci3_sleep>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sc8280xp-camcc"; reg =3D <0 0x0ad00000 0 0x20000>; @@ -4076,6 +4239,150 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 230>; wakeup-parent =3D <&pdc>; + + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio113", "gpio114"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio115", "gpio116"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio113", "gpio114"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio115", "gpio116"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio10","gpio11"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins =3D "gpio123","gpio124"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio10","gpio11"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins =3D "gpio123","gpio124"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_default: cci2-default-state { + cci2_i2c0_default: cci2-i2c0-default-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins =3D "gpio117","gpio118"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci2_i2c1_default: cci2-i2c1-default-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins =3D "gpio12","gpio13"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci2_sleep: cci2-sleep-state { + cci2_i2c0_sleep: cci2-i2c0-sleep-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins =3D "gpio117","gpio118"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_i2c1_sleep: cci2-i2c1-sleep-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins =3D "gpio12","gpio13"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci3_default: cci3-default-state { + cci3_i2c0_default: cci3-i2c0-default-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins =3D "gpio145","gpio146"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci3_i2c1_default: cci3-i2c1-default-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins =3D "gpio164","gpio165"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci3_sleep: cci3-sleep-state { + cci3_i2c0_sleep: cci3-i2c0-sleep-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins =3D "gpio145","gpio146"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_i2c1_sleep: cci3-i2c1-sleep-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins =3D "gpio164","gpio165"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; }; =20 apps_smmu: iommu@15000000 { --=20 2.42.0 From nobody Fri Dec 26 05:10:13 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B73B3A8CA for ; Tue, 9 Jan 2024 16:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZEqXDbQJ" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40e490c2115so11961705e9.0 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-4-b8e3a74a6e6a@linaro.org> References: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> In-Reply-To: <20240109-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v3-0-b8e3a74a6e6a@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 Add CAMSS block definition for sc8280xp. This drop contains definitions for the following components on sc8280xp: VFE * 4 VFE Lite * 4 CSID * 4 CSIPHY * 4 This dtsi definition has been developed and validated on a Lenovo X13s laptop. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 239 +++++++++++++++++++++++++++++= ++++ 1 file changed, 239 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index f48dfa5e5f36..35bc31117b41 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3614,6 +3614,245 @@ cci3_i2c1: i2c-bus@1 { }; }; =20 + camss: camss@ac5a000 { + compatible =3D "qcom,sc8280xp-camss"; + + reg =3D <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + + reg-names =3D "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains =3D <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names =3D "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>; + + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe3_axi", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf"; + + iommus =3D <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMER= A_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sc8280xp-camcc"; reg =3D <0 0x0ad00000 0 0x20000>; --=20 2.42.0