From nobody Fri Dec 19 02:49:17 2025 Received: from eggs.gnu.org (eggs.gnu.org [209.51.188.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B562A14281; Mon, 8 Jan 2024 11:03:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gnu.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gnu.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gnu.org header.i=@gnu.org header.b="RelumATz" Received: from fencepost.gnu.org ([2001:470:142:3::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rMnPZ-0001Ry-73; Mon, 08 Jan 2024 06:03:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=gnu.org; s=fencepost-gnu-org; h=MIME-Version:References:In-Reply-To:Date:Subject:To: From; bh=k2bv0lubVH8NsRJr5+61Oe3KPK8iIPvWwJlHbhSRxgY=; b=RelumATzJt8gnNL/W/76 kqcOOtSogvG2oXBtVajdlhjh8CZh7CLmMW5zO1dTaFrWdsQEw1jOnpgcLRts/afq+UpTI8dZ2jfau y0uwkiivyFY9ZUej+oNd4rvvKaF0/dmuqPDht0cw3FNfb63AH0Nv3er+8BNKZsc/XkLtqpaAe6i3m iywYGFJAtYCFZUZxwfKkgQyzml5/67hl1ErcpUV14OTk4SXJX/AgoFARWIhIY3fvkTrowoh6YYXdy zZMlDhj/NCtZbWPmc1ah3EbwJU4y37Ngy4FdUcl03nuuC8YvCRLrL0uEvdJg0gdUcd31VtGZivEgR dEBl/XcO2F/1cw==; From: Mathieu Othacehe To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , Stefan Wahren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mathieu Othacehe , Krzysztof Kozlowski Subject: [PATCH v7 1/2] dt-bindings: arm: fsl: Add VAR-SOM-MX93 with Symphony Date: Mon, 8 Jan 2024 12:02:40 +0100 Message-ID: <20240108110241.8555-2-othacehe@gnu.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240108110241.8555-1-othacehe@gnu.org> References: <20240108110241.8555-1-othacehe@gnu.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Variscite i.MX93 VAR-SOM-MX93 SoM with Symphony board. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mathieu Othacehe --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 228dcc5c7d6f..27936edfe054 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM - const: fsl,imx93 =20 + - description: Variscite VAR-SOM-MX93 based boards + items: + - const: variscite,var-som-mx93-symphony + - const: variscite,var-som-mx93 + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings =20 --=20 2.41.0 From nobody Fri Dec 19 02:49:17 2025 Received: from eggs.gnu.org (eggs.gnu.org [209.51.188.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C86CD14282; Mon, 8 Jan 2024 11:03:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gnu.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gnu.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gnu.org header.i=@gnu.org header.b="ejZuxHCh" Received: from fencepost.gnu.org ([2001:470:142:3::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rMnPZ-0001SL-Iy; Mon, 08 Jan 2024 06:03:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=gnu.org; s=fencepost-gnu-org; h=MIME-Version:References:In-Reply-To:Date:Subject:To: From; bh=bEuXkbS7GmJBjdYAemrSoXHP/SGYNY9TGYw7x78sdlw=; b=ejZuxHChEeGRGyh14tDK 9+LBa6Ls9TBRDysV+lSU1+pNu75nd4c736IYZ7S3jJfcgSOn6Ls/I8hW3MqJuihtcK4cnSu+4dS7p wsd9iP2PuSorv3V5k4U2Qv4u/nHJ0x37qSrcNPepwWkKUkV103VNRQdEk6wcs5firILzlWCGfiY5r fwo8EGZ8783DBLB8jQdy4dv37uCMD92+q97thoXIiLt7HxsOafXTgm7ZwsKTWm2YtqGKUu1vFCc2n JO5i4OPv+p+oLOaakTvO5MXzcv7f46j3XN4NA6CGlPUhVyJ1/xJMnm6XBaI4Ir8q0OAnaJGPdGDdK +xbp0nTOH9isCg==; From: Mathieu Othacehe To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , Stefan Wahren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mathieu Othacehe Subject: [PATCH v7 2/2] arm64: dts: imx93-var-som: Add Variscite VAR-SOM-MX93 Date: Mon, 8 Jan 2024 12:02:41 +0100 Message-ID: <20240108110241.8555-3-othacehe@gnu.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240108110241.8555-1-othacehe@gnu.org> References: <20240108110241.8555-1-othacehe@gnu.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DTSI for Variscite VAR-SOM-MX93 System on Module and DTS for Variscite VAR-SOM-MX93 on Symphony evaluation board. This version comes with: - NXP i.MX 93 Dual, 1.7GHz, Cortex-A55 + Cortex-M33 - 2 GB of RAM - 16GB eMMC - 802.11ax/ac/a/b/g/n WiFi with 5.3 Bluetooth - CAN bus - Audio codec Signed-off-by: Mathieu Othacehe --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-var-som-symphony.dts | 351 ++++++++++++++++++ .../boot/dts/freescale/imx93-var-som.dtsi | 111 ++++++ 3 files changed, 463 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 2e027675d7bb..a6f1700961e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arc= h/arm64/boot/dts/freescale/imx93-var-som-symphony.dts new file mode 100644 index 000000000000..576d6982a4a0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include +#include "imx93-var-som.dtsi" + +/{ + model =3D "Variscite VAR-SOM-MX93 on Symphony evaluation board"; + compatible =3D "variscite,var-som-mx93-symphony", + "variscite,var-som-mx93", "fsl,imx93"; + + aliases { + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + /* + * Needed only for Symphony <=3D v1.5 + */ + reg_fec_phy: regulator-fec-phy { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec-phy"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <20000>; + gpio =3D <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + off-on-delay-us =3D <20000>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible =3D "shared-dma-pool"; + reusable; + reg =3D <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg =3D <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg =3D <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg =3D <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg =3D <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg =3D <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x87de0000 0 0x100000>; + no-map; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + key-back { + label =3D "Back"; + gpios =3D <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + key-home { + label =3D "Home"; + gpios =3D <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + key-menu { + label =3D "Menu"; + gpios =3D <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; +}; + +/* Use external instead of internal RTC*/ +&bbnsm_rtc { + status =3D "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <5>; + qca,disable-smarteee; + eee-broken-1000t; + reset-gpios =3D <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <20000>; + vddio-supply =3D <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy1>; + phy-supply =3D <®_fec_phy>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c1_gpio>; + scl-gpios =3D <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio1 1 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + /* DS1337 RTC module */ + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + }; +}; + +&lpi2c5 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c5>; + pinctrl-1 =3D <&pinctrl_lpi2c5_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c5_gpio>; + scl-gpios =3D <&gpio2 23 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio2 22 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + gpio-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9534>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <26 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells =3D <2>; + wakeup-source; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +/* J18.7, J18.9 */ +&lpuart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; + no-sdio; + no-mmc; +}; + +/* Watchdog */ +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/= boot/dts/freescale/imx93-var-som.dtsi new file mode 100644 index 000000000000..8210d1f63c31 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model =3D "Variscite VAR-SOM-MX93 module"; + compatible =3D "variscite,var-som-mx93", "fsl,imx93"; + + mmc_pwrseq: mmc-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <10000>; + reset-gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + + reg_eqos_phy: regulator-eqos-phy { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_eqos_phy>; + regulator-name =3D "eth_phy_pwr"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <100000>; + regulator-always-on; + }; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy0>; + phy-supply =3D <®_eqos_phy>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <1000000>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + eee-broken-1000t; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_reg_eqos_phy: regeqosgrp { + fsl,pins =3D < + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; +}; --=20 2.41.0