From nobody Fri Dec 26 09:36:10 2025 Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B973511CAD for ; Mon, 8 Jan 2024 09:32:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0x0f.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="pLZ/eXXR" Received: by mail-oi1-f180.google.com with SMTP id 5614622812f47-3bc09844f29so1773019b6e.0 for ; Mon, 08 Jan 2024 01:32:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; t=1704706351; x=1705311151; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pn2kTcTKQegvfRo59aF494Y7VB6jkLeF4G27EDz1T1U=; b=pLZ/eXXRB3+9mUJwci1Pof7Ix/tzRkQDLy0QtNzvUjT+Lo2Z5oesTNffFaatNJL84q 3YitEdqx3rOJp+gQWG7LGLQfQgxZAXHtrPAsKktEb1PqgyNTAMkMJJn9uMlVYqjIa1nG TX1xD02D3FksICc8NrmLham6kPqZB8qBWBy3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704706351; x=1705311151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pn2kTcTKQegvfRo59aF494Y7VB6jkLeF4G27EDz1T1U=; b=uvhNAAHP8f6JDuFciUx2dIm/lX36wKdC8ca0P1McHkxUvW241FYUI5+5taU9LAmhxx p9YZFnFknKKJl3aY2Jk+kkCiXRICsdIJ33zjDK3Lp5uOYz23C2d05IABgr5eLxRUw5Ju y302SakAb6XiHFWeghR9p/HBf4cM9SzeGQ+24I46fNOus6AHXeNymJKrpDH5LpJGta/k pTq6w2EOaIQhlYLS3RzMmNnnvLtCh7KzMUkqU9Xd/vsmk9831Uumm6kGE0XeP7f0qaQv I1TMJcADl1UJJMLnJ5mgkWCRIM+NA03QseHFbXHnUixd6qnYFDogEn+Lgawlwiyr/7Ne Fhrw== X-Gm-Message-State: AOJu0YzvP9K309eVz1chxMeKPUNq/DdCX4OVzGP8K4ICAXdgR9wa3qrd yphwwFEo7e5Cvf1NWGcDwNQpXnkTXcwyZypVU3BTphgED4o= X-Google-Smtp-Source: AGHT+IF0v9pYtaCUdIMW0KC8X3CbJCAZUdalzX5CmE1kx5uZ44HD8tapWvSVvYGzZsd5cm0k4YOdCQ== X-Received: by 2002:a05:6358:949d:b0:170:e930:bd3 with SMTP id i29-20020a056358949d00b00170e9300bd3mr3002255rwb.32.1704706350703; Mon, 08 Jan 2024 01:32:30 -0800 (PST) Received: from shiro.work.home.arpa ([2400:4162:2428:2ffe:a221:b29b:7116:6ce9]) by smtp.googlemail.com with ESMTPSA id i8-20020a632208000000b005cdbebd61d8sm5578974pgi.9.2024.01.08.01.32.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 01:32:30 -0800 (PST) From: Daniel Palmer To: gerg@linux-m68k.org, geert@linux-m68k.org, fthain@linux-m68k.org Cc: linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH v2 1/2] m68k: Use macro to generate 68000 interrupt entry sleds Date: Mon, 8 Jan 2024 18:32:20 +0900 Message-ID: <20240108093221.1477020-2-daniel@0x0f.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240108093221.1477020-1-daniel@0x0f.com> References: <20240108093221.1477020-1-daniel@0x0f.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for decoupling the plain 68000 code from the DragonBall support clean entry.S a little bit by using a macro to generic the interrupt sleds (needed to put the vector number on the stack as the 68000 doesn't do that) and use the correct numbers. The function to call from the sled is a parameter so that other interrupt types (i.e. autovectored ones) can specify their handler when they are added later. Signed-off-by: Daniel Palmer --- arch/m68k/68000/entry.S | 100 ++++++++-------------------------------- arch/m68k/68000/ints.c | 28 +++++------ 2 files changed, 34 insertions(+), 94 deletions(-) diff --git a/arch/m68k/68000/entry.S b/arch/m68k/68000/entry.S index 72e95663b62f..e1fc740412f2 100644 --- a/arch/m68k/68000/entry.S +++ b/arch/m68k/68000/entry.S @@ -23,13 +23,6 @@ .globl ret_from_exception .globl sys_call_table .globl bad_interrupt -.globl inthandler1 -.globl inthandler2 -.globl inthandler3 -.globl inthandler4 -.globl inthandler5 -.globl inthandler6 -.globl inthandler7 =20 badsys: movel #-ENOSYS,%sp@(PT_OFF_D0) @@ -119,85 +112,32 @@ Lsignal_return: addql #4,%sp jra 1b =20 -/* - * This is the main interrupt handler, responsible for calling process_int= () - */ -inthandler1: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #65,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler2: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #66,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler3: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #67,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler4: +/* Create an interrupt vector sled */ + .macro inthandler num func + .globl inthandler\num + inthandler\num: SAVE_ALL_INT movew %sp@(PT_OFF_FORMATVEC), %d0 and #0x3ff, %d0 =20 movel %sp,%sp@- - movel #68,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler5: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #69,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler6: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #70,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ - bra ret_from_exception - -inthandler7: - SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 - - movel %sp,%sp@- - movel #71,%sp@- /* put vector # on stack*/ - jbsr process_int /* process the IRQ*/ -3: addql #8,%sp /* pop parameters off stack*/ + /* put vector # on stack*/ + movel #\num,%sp@- + /* process the IRQ*/ + jbsr \func + /* pop parameters off stack*/ + addql #8,%sp bra ret_from_exception + .endm + +/* Dragonball interrupts */ +inthandler 65 process_int +inthandler 66 process_int +inthandler 67 process_int +inthandler 68 process_int +inthandler 69 process_int +inthandler 70 process_int +inthandler 71 process_int =20 inthandler: SAVE_ALL_INT diff --git a/arch/m68k/68000/ints.c b/arch/m68k/68000/ints.c index 2ba9926e91ae..e721932e495d 100644 --- a/arch/m68k/68000/ints.c +++ b/arch/m68k/68000/ints.c @@ -63,13 +63,13 @@ asmlinkage void trap46(void); asmlinkage void trap47(void); asmlinkage irqreturn_t bad_interrupt(int, void *); asmlinkage irqreturn_t inthandler(void); -asmlinkage irqreturn_t inthandler1(void); -asmlinkage irqreturn_t inthandler2(void); -asmlinkage irqreturn_t inthandler3(void); -asmlinkage irqreturn_t inthandler4(void); -asmlinkage irqreturn_t inthandler5(void); -asmlinkage irqreturn_t inthandler6(void); -asmlinkage irqreturn_t inthandler7(void); +asmlinkage irqreturn_t inthandler65(void); +asmlinkage irqreturn_t inthandler66(void); +asmlinkage irqreturn_t inthandler67(void); +asmlinkage irqreturn_t inthandler68(void); +asmlinkage irqreturn_t inthandler69(void); +asmlinkage irqreturn_t inthandler70(void); +asmlinkage irqreturn_t inthandler71(void); =20 /* The 68k family did not have a good way to determine the source * of interrupts until later in the family. The EC000 core does @@ -163,13 +163,13 @@ void __init trap_init(void) =20 _ramvec[32] =3D system_call; =20 - _ramvec[65] =3D (e_vector) inthandler1; - _ramvec[66] =3D (e_vector) inthandler2; - _ramvec[67] =3D (e_vector) inthandler3; - _ramvec[68] =3D (e_vector) inthandler4; - _ramvec[69] =3D (e_vector) inthandler5; - _ramvec[70] =3D (e_vector) inthandler6; - _ramvec[71] =3D (e_vector) inthandler7; + _ramvec[65] =3D (e_vector) inthandler65; + _ramvec[66] =3D (e_vector) inthandler66; + _ramvec[67] =3D (e_vector) inthandler67; + _ramvec[68] =3D (e_vector) inthandler68; + _ramvec[69] =3D (e_vector) inthandler69; + _ramvec[70] =3D (e_vector) inthandler70; + _ramvec[71] =3D (e_vector) inthandler71; } =20 void __init init_IRQ(void) --=20 2.43.0 From nobody Fri Dec 26 09:36:10 2025 Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com [209.85.210.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D974312B87 for ; Mon, 8 Jan 2024 09:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0x0f.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="Ld18rbZ1" Received: by mail-ot1-f43.google.com with SMTP id 46e09a7af769-6dc20b4595bso1349542a34.0 for ; Mon, 08 Jan 2024 01:32:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; t=1704706353; x=1705311153; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TfdL1VvrUAffk+JEt/9C7vAUDoa3/sBqju5Vv3smMQQ=; b=Ld18rbZ1Y5wcUbVQYH428vzwZALY9KghdXoh/2OHSl1X2Ge4ktao7m6JKMSJFb8A79 XHJLe6dJRdb1u9ok5/xjs9JA2qrdZdZEJjFKMZOYv4xBSJ2RJV/xGeNLMx3JTQkrdDkk TY/VW++NW1xhOZA0CxI/Zsby5+irfwx3jPoc8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704706353; x=1705311153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfdL1VvrUAffk+JEt/9C7vAUDoa3/sBqju5Vv3smMQQ=; b=gNhiQuZlner/AgzeCxLV3YQqltJN3nDN2Zbewhk/oWSQFTJMzJuRrSFgNGn8CQ9w/C NeWcxPzESg74zPyNRmZmT4A3L7Nizg8qAz2sGeIp8rbTDW2eAahQGgrPY9EzoYaMPYi6 L+i9gUy03TRULvWe6wmDdZ/ZQvSK41vZmf8zGJ7uqUCSbN5vQ77wXpGGzmD7NXr1zZPI gZvpTy2slLWxOuEIMceEfuvB/YKI5UFS6kYO0TagQQ4zbDL9Pfd+4ArlE5XODSOLOXnJ wnMcvfZGd44Ne7KCZXkaupNDtJlHgApkR+8zRJSaQPCxkFKlMJGLx6n04qTNFOU4Fls4 bzJQ== X-Gm-Message-State: AOJu0Yz2IaMMGgGxiraiWNKKCtg9ngxHOuDsA7GbLWnVrAag5MNK+fbf AybaX3dBU3EGgV0ouQUZ57vUwUvx78hMcA6Ua3BqN/wxnwA= X-Google-Smtp-Source: AGHT+IHOfqcx1LisFMsghCeAdvBasVv/c4m8FJbkf6lrgBZPAPZGqSJTbJFW/Lb7JJGqlKNxTU388A== X-Received: by 2002:a9d:590a:0:b0:6db:fe20:fc1c with SMTP id t10-20020a9d590a000000b006dbfe20fc1cmr2517182oth.63.1704706352778; Mon, 08 Jan 2024 01:32:32 -0800 (PST) Received: from shiro.work.home.arpa ([2400:4162:2428:2ffe:a221:b29b:7116:6ce9]) by smtp.googlemail.com with ESMTPSA id i8-20020a632208000000b005cdbebd61d8sm5578974pgi.9.2024.01.08.01.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 01:32:32 -0800 (PST) From: Daniel Palmer To: gerg@linux-m68k.org, geert@linux-m68k.org, fthain@linux-m68k.org Cc: linux-m68k@lists.linux-m68k.org, linux-kernel@vger.kernel.org, Daniel Palmer Subject: [PATCH v2 2/2] m68k: Fix interrupt stack frames for 68000 Date: Mon, 8 Jan 2024 18:32:21 +0900 Message-ID: <20240108093221.1477020-3-daniel@0x0f.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240108093221.1477020-1-daniel@0x0f.com> References: <20240108093221.1477020-1-daniel@0x0f.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The plain old 68000 does not push the frame type/vector on the stack when an interrupt starts like the brand new 68010 does. This means that currently everything in struct pt_regs is a bit off because it expects the processor to push an extra short before the kernel interrupt code adds the rest. In entry.S for the 68000 we already need to manually put the vector number on the stack to work out what interrupt is being handled because the cpu doesn't push that to the stack. So we can jiggle this around a bit to fix the issue: - For 68000 use the same struct pt_regs layout as coldfire where frame/vector is after pc and sp. - In entry.S push the vector number first, the stack pointer now lines up with the sktadj field in pt_regs and when saving the remaining registers the offsets match the fields in the struct. - Remove the vec argument from the DragonBall interrupt decoding logic as it's not pushed on the stack anymore and not used either way. Signed-off-by: Daniel Palmer --- arch/m68k/68000/entry.S | 9 ++++----- arch/m68k/68000/ints.c | 2 +- arch/m68k/include/asm/entry.h | 3 +++ arch/m68k/include/uapi/asm/ptrace.h | 2 +- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/m68k/68000/entry.S b/arch/m68k/68000/entry.S index e1fc740412f2..58c64656713a 100644 --- a/arch/m68k/68000/entry.S +++ b/arch/m68k/68000/entry.S @@ -54,6 +54,7 @@ do_trace: jra ret_from_exception =20 ENTRY(system_call) + movew #32,%sp@- SAVE_ALL_SYS =20 /* save top of frame*/ @@ -116,17 +117,15 @@ Lsignal_return: .macro inthandler num func .globl inthandler\num inthandler\num: + movew #\num,%sp@- SAVE_ALL_INT - movew %sp@(PT_OFF_FORMATVEC), %d0 - and #0x3ff, %d0 =20 + /* Push frame address onto stack */ movel %sp,%sp@- - /* put vector # on stack*/ - movel #\num,%sp@- /* process the IRQ*/ jbsr \func /* pop parameters off stack*/ - addql #8,%sp + addql #4,%sp bra ret_from_exception .endm =20 diff --git a/arch/m68k/68000/ints.c b/arch/m68k/68000/ints.c index e721932e495d..67c8f9e000ca 100644 --- a/arch/m68k/68000/ints.c +++ b/arch/m68k/68000/ints.c @@ -77,7 +77,7 @@ asmlinkage irqreturn_t inthandler71(void); * into one vector and look in the blasted mask register... * This code is designed to be fast, almost constant time, not clean! */ -asmlinkage void process_int(int vec, struct pt_regs *fp) +asmlinkage void process_int(struct pt_regs *fp) { int irq; int mask; diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h index 9b52b060c76a..71396c948162 100644 --- a/arch/m68k/include/asm/entry.h +++ b/arch/m68k/include/asm/entry.h @@ -184,6 +184,7 @@ * that the stack frame is NOT for syscall */ .macro SAVE_ALL_INT + /* entry.S should populate the vector */ clrl %sp@- /* stk_adj */ pea -1:w /* orig d0 */ movel %d0,%sp@- /* d0 */ @@ -191,6 +192,7 @@ .endm =20 .macro SAVE_ALL_SYS + /* entry.S should populate the vector */ clrl %sp@- /* stk_adj */ movel %d0,%sp@- /* orig d0 */ movel %d0,%sp@- /* d0 */ @@ -202,6 +204,7 @@ movel %sp@+,%d0 addql #4,%sp /* orig d0 */ addl %sp@+,%sp /* stk adj */ + addql #2,%sp /* entry.S populated vector */ rte .endm =20 diff --git a/arch/m68k/include/uapi/asm/ptrace.h b/arch/m68k/include/uapi/a= sm/ptrace.h index 5b50ea592e00..49d7829df77c 100644 --- a/arch/m68k/include/uapi/asm/ptrace.h +++ b/arch/m68k/include/uapi/asm/ptrace.h @@ -39,7 +39,7 @@ struct pt_regs { long d0; long orig_d0; long stkadj; -#ifdef CONFIG_COLDFIRE +#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000) unsigned format : 4; /* frame format specifier */ unsigned vector : 12; /* vector offset */ unsigned short sr; --=20 2.43.0