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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id uz29-20020a170907119d00b00a2aae23b414sm666046ejb.26.2024.01.08.00.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 00:52:53 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Golle , Hsin-Yi Wang , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , jason-ch chen , Macpaul Lin , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sean Wang , Frank Wunderlich , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH V2 3/3] arm64: dts: mediatek: mt7988: add clock controllers Date: Mon, 8 Jan 2024 09:52:28 +0100 Message-Id: <20240108085228.4727-4-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240108085228.4727-1-zajec5@gmail.com> References: <20240108085228.4727-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki Add bindings of on-SoC clocks. Signed-off-by: Rafa=C5=82 Mi=C5=82ecki Reviewed-by: Daniel Golle --- V2: New PATCH in the series thanks to Daniel's bindings work arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 41 ++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index 5a778188ac21..bba97de4fb44 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -78,12 +78,51 @@ gic: interrupt-controller@c000000 { #interrupt-cells =3D <3>; }; =20 - watchdog@1001c000 { + clock-controller@10001000 { + compatible =3D "mediatek,mt7988-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1001b000 { + compatible =3D "mediatek,mt7988-topckgen", "syscon"; + reg =3D <0 0x1001b000 0 0x1000>; + #clock-cells =3D <1>; + }; + + watchdog: watchdog@1001c000 { compatible =3D "mediatek,mt7988-wdt"; reg =3D <0 0x1001c000 0 0x1000>; interrupts =3D ; #reset-cells =3D <1>; }; + + clock-controller@1001e000 { + compatible =3D "mediatek,mt7988-apmixedsys"; + reg =3D <0 0x1001e000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@11f40000 { + compatible =3D "mediatek,mt7988-xfi-pll"; + reg =3D <0 0x11f40000 0 0x1000>; + resets =3D <&watchdog 16>; + #clock-cells =3D <1>; + }; + + clock-controller@15000000 { + compatible =3D "mediatek,mt7988-ethsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + clock-controller@15031000 { + compatible =3D "mediatek,mt7988-ethwarp"; + reg =3D <0 0x15031000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 timer { --=20 2.35.3