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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id uz29-20020a170907119d00b00a2aae23b414sm666046ejb.26.2024.01.08.00.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 00:52:50 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Daniel Golle , Hsin-Yi Wang , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , jason-ch chen , Macpaul Lin , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sean Wang , Frank Wunderlich , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH V2 2/3] arm64: dts: mediatek: Add initial MT7988A and BPI-R4 Date: Mon, 8 Jan 2024 09:52:27 +0100 Message-Id: <20240108085228.4727-3-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240108085228.4727-1-zajec5@gmail.com> References: <20240108085228.4727-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki MT7988A (AKA MediaTek Filogic 880) is a quad-core ARM Cortex-A73 platform designed for Wi-Fi 7 devices (there is no wireless on SoC though). The first public MT7988A device is Banana Pi BPI-R4. Many SoC parts remain to be added (they need their own bindings or depend on missing clocks). Those present block however are correct and having base .dtsi will help testing & working on missing stuff. Signed-off-by: Rafa=C5=82 Mi=C5=82ecki --- V2: Drop thermal zones & reserved memory from .dtsi (those don't belong there and we also need thermal controller first). Fix compatible. arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 11 +++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 97 +++++++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 1e6f91731e92..0a189d5d8006 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-= nor.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-bananapi-bpi-r3-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7986b-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt7988a-bananapi-bpi-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arc= h/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts new file mode 100644 index 000000000000..efc4ad0b08b8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7988a.dtsi" + +/ { + compatible =3D "bananapi,bpi-r4", "mediatek,mt7988a"; + model =3D "Banana Pi BPI-R4"; + chassis-type =3D "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi new file mode 100644 index 000000000000..5a778188ac21 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include + +/ { + compatible =3D "mediatek,mt7988a"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a73"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu@1 { + compatible =3D "arm,cortex-a73"; + reg =3D <0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu@2 { + compatible =3D "arm,cortex-a73"; + reg =3D <0x2>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + + cpu@3 { + compatible =3D "arm,cortex-a73"; + reg =3D <0x3>; + device_type =3D "cpu"; + enable-method =3D "psci"; + }; + }; + + oscillator-40m { + compatible =3D "fixed-clock"; + clock-frequency =3D <40000000>; + #clock-cells =3D <0>; + clock-output-names =3D "clkxtal"; + }; + + pmu { + compatible =3D "arm,cortex-a73-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + watchdog@1001c000 { + compatible =3D "mediatek,mt7988-wdt"; + reg =3D <0 0x1001c000 0 0x1000>; + interrupts =3D ; + #reset-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.35.3