From nobody Fri Dec 19 09:11:02 2025 Received: from mail-oa1-f50.google.com (mail-oa1-f50.google.com [209.85.160.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D34956764 for ; Mon, 8 Jan 2024 23:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="laHwm5MK" Received: by mail-oa1-f50.google.com with SMTP id 586e51a60fabf-203ae9903a6so1346967fac.0 for ; Mon, 08 Jan 2024 15:57:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704758251; x=1705363051; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AlBR54Ho+Y1o3mIpBCBVXs2u+7/gciH5xwmXB5mwVNU=; b=laHwm5MKj2xko3qTe9o5fIWZS/fRDyMFOKlIQo2ZaAM0R3fc8jmUPkno6f652tLRuL MsQlYjSj5J2+0EpNJULl6WPUnqS1+jW6wq4Hm+hpiPowhadsJbCXejdjHHT4iGoO+GD9 VByoCwlWEk9q+9Qyshyx0z68HPJ3u33cV6SS6H07jVjBLxs3cR00GTBsNB76/n2fb/v0 t58L/S8WCm2sR1Vi9cLBo5NhKcX1pPxNYK17OqQtqYNGdxqCPURL/2WGgK47+UzI/u3w 7vv8bgf9DEFI+rfwGOav1nIQulkTqW1jfMkKusd3WU49nB0kLnFx0rcDVt8FebaLvTju 5fKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704758251; x=1705363051; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AlBR54Ho+Y1o3mIpBCBVXs2u+7/gciH5xwmXB5mwVNU=; b=eqOrGKta1E5optxZlPLlRiFCbVRYRqWU8XcMjP42tYHmV+ASRsl9L0dQLp7CagB6ep 6iXkAUKK3fzQlAnPv7l15fNj0zx7icYpuWVUXdsITTEU8b+Jp3U6Q8W9lHqcAu1k4cdf 2d1q8re36ZLT1qn7fe4TIyoGL+TZckmd/1fkodwiY5/XTWhZFqidVxyMiASK5yrqtmxX EXWdid7CDWPFqki1QBWaSkhHA51qzBMfTcSLT5OfudUosQBbYM58W7az9rsOK2/fYUYN MBj5rPbhbD1leuliCeYkfnYehYGNIzufyi0oMacrM7hHBzWkEyGj24EmMjWaaCHOo+ij pRcA== X-Gm-Message-State: AOJu0Yx9zGjiS1fMqzSOh9SG98iIWMYkyIZsvEUaCNk44Gh0tXYqYQ+0 UbtI64qh+xJB0xchehHTS4v2qLLPaST61g== X-Google-Smtp-Source: AGHT+IHwPAPXTkLLxmW8VZ4pal/a4TJ6IKFDbgC3aJOyBsOPpUm3+f9Bvw8flyX2Z5h4eOW/h8eVig== X-Received: by 2002:a05:6870:9728:b0:1fa:f418:d071 with SMTP id n40-20020a056870972800b001faf418d071mr4620078oaq.23.1704758251521; Mon, 08 Jan 2024 15:57:31 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id ti5-20020a056871890500b002043b415eaasm206961oab.29.2024.01.08.15.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 15:57:31 -0800 (PST) From: Charlie Jenkins Date: Mon, 08 Jan 2024 15:57:04 -0800 Subject: [PATCH v15 3/5] riscv: Add checksum header Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240108-optimize_checksum-v15-3-1c50de5f2167@rivosinc.com> References: <20240108-optimize_checksum-v15-0-1c50de5f2167@rivosinc.com> In-Reply-To: <20240108-optimize_checksum-v15-0-1c50de5f2167@rivosinc.com> To: Charlie Jenkins , Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Xiao Wang , Evan Green , Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: Paul Walmsley , Albert Ou , Arnd Bergmann , Conor Dooley X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704758245; l=3093; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=5kLrZ5pIGOixKzGlevacL81yKd58H4/jGvyu52ss5bM=; b=vlnj2iaVuImO4Aya69nCeHVLgDjfp2gYnqsLnMwcOp5cZZIflMKLy90+Mo+3sPLADQFs0ICrd PhcHtJaoVmACVFzOfqi+6dDhy9fB+84Yi5XE9Ks3nXptNwlKUYAGlLm X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Provide checksum algorithms that have been designed to leverage riscv instructions such as rotate. In 64-bit, can take advantage of the larger register to avoid some overflow checking. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley Reviewed-by: Xiao Wang --- arch/riscv/include/asm/checksum.h | 82 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 82 insertions(+) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h new file mode 100644 index 000000000000..5a810126aac7 --- /dev/null +++ b/arch/riscv/include/asm/checksum.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Checksum routines + * + * Copyright (C) 2023 Rivos Inc. + */ +#ifndef __ASM_RISCV_CHECKSUM_H +#define __ASM_RISCV_CHECKSUM_H + +#include +#include + +#define ip_fast_csum ip_fast_csum + +/* Define riscv versions of functions before importing asm-generic/checksu= m.h */ +#include + +/** + * Quickly compute an IP checksum with the assumption that IPv4 headers wi= ll + * always be in multiples of 32-bits, and have an ihl of at least 5. + * + * @ihl: the number of 32 bit segments and must be greater than or equal t= o 5. + * @iph: assumed to be word aligned given that NET_IP_ALIGN is set to 2 on + * riscv, defining IP headers to be aligned. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned long csum =3D 0; + int pos =3D 0; + + do { + csum +=3D ((const unsigned int *)iph)[pos]; + if (IS_ENABLED(CONFIG_32BIT)) + csum +=3D csum < ((const unsigned int *)iph)[pos]; + } while (++pos < ihl); + + /* + * ZBB only saves three instructions on 32-bit and five on 64-bit so not + * worth checking if supported without Alternatives. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + + if (IS_ENABLED(CONFIG_32BIT)) { + asm(".option push \n\ + .option arch,+zbb \n\ + not %[fold_temp], %[csum] \n\ + rori %[csum], %[csum], 16 \n\ + sub %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); + } else { + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + not %[fold_temp], %[csum] \n\ + roriw %[csum], %[csum], 16 \n\ + subw %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); + } + return (__force __sum16)(csum >> 16); + } +no_zbb: +#ifndef CONFIG_32BIT + csum +=3D ror64(csum, 32); + csum >>=3D 32; +#endif + return csum_fold((__force __wsum)csum); +} + +#endif /* __ASM_RISCV_CHECKSUM_H */ --=20 2.43.0