From nobody Fri Dec 26 07:20:45 2025 Received: from mail-oa1-f47.google.com (mail-oa1-f47.google.com [209.85.160.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CF2854BFB for ; Mon, 8 Jan 2024 18:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="muCuUKnu" Received: by mail-oa1-f47.google.com with SMTP id 586e51a60fabf-2044ecf7035so1608355fac.0 for ; Mon, 08 Jan 2024 10:42:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704739360; x=1705344160; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e6V5mUDz/ArwMQCWHpehsnGmBF913UphNBnehcxty1g=; b=muCuUKnuMXtfbKHk4lvwzGSW0Z49U5yHDS3n66jSNlQml0yGwiOwEkkWLRY4v2x+Uy NToUsqKMZnNJs0ACoxwQNRE8U+wavvsa/5lwJ2w1T9Wvfjg1FpeQDOQTmQhNQOFQVDkA eQz/+TcfNHPWfvEokzEAfc3eJKZ0HBBAPi7IbDc1xH9jlGFyyXvkeSQxPGeAN4sNhGEi 7xBGZYMyOTu+R3wvx/Ng4+ygl/bNpg6na1vGbG16vS3fg+IYtQBcBcraB3mAtooiMzS+ xE0z3l6zcPG91QvnqUL9IwfRr42683J5zCKtRx7fg9rfXSZrhEtnv57NAKJvh5YWfdBi KDQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704739360; x=1705344160; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e6V5mUDz/ArwMQCWHpehsnGmBF913UphNBnehcxty1g=; b=jbmv5TM2PQXXpxEKgepUMu5QfLp8NGXQ5mdE5wzzWYURYaXmRvSZvC+ZvTQkiR36j8 1VgN8UbMzi2IeOdmkENz4L04vOZerDdF6coZAcGhmvpImE3N3Aii9TonLV7Wj9srYM3e L61ColOe/+JzGDKoRIvzRLG1IEmGMmC5KRc/MKqS162XV16CH0sESMHtHS+LK4XHcpEi YYYQsy/ktylMKhWeizffNzQ5e6OsYopqNFA9cIvWO3eQUvug2WCMjIh7F5qDvh7f/Iqs cYPzEt25Pn0D0czNxZF/+WPwErnmLhAXvw70DBVbuA6Sf64Me+TnyJLfWcZcZvmnhuXA LLVg== X-Gm-Message-State: AOJu0YyiwI2ogmqU2E0uSxKsMbIVFo3Lsh3COjjEWz3SoOnXTNCqBnsf bMKtnu54a0eEmWgGUm1Fpf2YMMyU1s59YQ== X-Google-Smtp-Source: AGHT+IEFvadrZzOWSqQPBZQGfiG8LafYKw8OApL2jimhZSwKvSPUg8DPD4zF/Fq7TUyYsKnfUHxyQw== X-Received: by 2002:a05:6870:280b:b0:206:16d9:e0f4 with SMTP id gz11-20020a056870280b00b0020616d9e0f4mr3702444oab.83.1704739360461; Mon, 08 Jan 2024 10:42:40 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id pp24-20020a0568709d1800b002044a0677adsm97860oab.8.2024.01.08.10.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 10:42:40 -0800 (PST) From: Charlie Jenkins Date: Mon, 08 Jan 2024 10:42:29 -0800 Subject: [PATCH v5 1/2] riscv: Include riscv_set_icache_flush_ctx prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240108-fencei-v5-1-aa1e51d7222f@rivosinc.com> References: <20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com> In-Reply-To: <20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704739355; l=7202; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=Jzlf965RqW01Ti4D8HEqjrOfLlTHg/6RiAi+H3J00Cc=; b=ZaUc08rRD9dRcmfhB9brz8NAWSmy/Vh1ORdCW2niSGY9YhoDXv0fT6L7GvrHT2XiYGDSMCF/w 6YBsAPd32ziC/ssb+4+IdqyTw7Q3a0QCbOdrqmOgQSxvLq5iCieIG4i X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable optimization of cross modifying code. This prctl enables userspace code to use icache flushing instructions such as fence.i with the guarantee that the icache will continue to be clean after thread migration. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra --- arch/riscv/include/asm/mmu.h | 2 ++ arch/riscv/include/asm/processor.h | 6 ++++ arch/riscv/mm/cacheflush.c | 56 ++++++++++++++++++++++++++++++++++= ++++ arch/riscv/mm/context.c | 8 ++++-- include/uapi/linux/prctl.h | 4 +++ kernel/sys.c | 6 ++++ 6 files changed, 79 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index f19f861cda54..7eda6c75e0f2 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -84,6 +84,9 @@ struct thread_struct { unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; unsigned long align_ctl; +#ifdef CONFIG_SMP + bool force_icache_flush; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -145,6 +148,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, uns= igned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) =20 +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(= arg1, arg2) +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per= _thread); + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 55a34f2020a8..a647b8abbe37 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include =20 @@ -152,3 +153,58 @@ void __init riscv_init_cbo_blocksizes(void) if (cboz_block_size) riscv_cboz_block_size =3D cboz_block_size; } + +/** + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructi= ons in userspace. + * @ctx: Set the type of icache flushing instructions permitted/prohibited. + * + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in userspace. + * + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in userspace. When + * ``per_thread =3D=3D 0``, this will effect all threads in a process. T= herefore, + * caution must be taken -- only use this flag when you can guarantee th= at no + * thread in the process will emit fence.i from this point onward. + * + * @per_thread: When set to 0, will perform operation on process migration= . When + * set to 1, will perform operation on thread migration. + * + * When ``per_thread =3D=3D 0``, all threads in the process are permitted = to emit + * icache flushing instructions. Whenever any thread in the process is mig= rated, + * the corresponding hart's icache will be guaranteed to be consistent with + * instruction storage. Note this does not enforce any guarantees outside = of + * migration. If a thread modifies an instruction that another thread may + * attempt to execute, the other thread must still emit an icache flushing + * instruction before attempting to execute the potentially modified + * instruction. This must be performed by the userspace program. + * + * In per-thread context (eg. ``per_thread =3D=3D 1``), only the thread ca= lling this + * function is permitted to emit icache flushing instructions. When the th= read + * is migrated, the corresponding hart's icache will be guaranteed to be + * consistent with instruction storage. + * + * On kernels configured without SMP, this function is a nop as migrations + * across harts will not occur. + */ +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread) +{ +#ifdef CONFIG_SMP + switch (ctx) { + case PR_RISCV_CTX_SW_FENCEI_ON: + if (per_thread) + current->thread.force_icache_flush =3D true; + else + current->mm->context.force_icache_flush =3D true; + break; + case PR_RISCV_CTX_SW_FENCEI_OFF: + if (per_thread) + current->thread.force_icache_flush =3D false; + else + current->mm->context.force_icache_flush =3D false; + break; + + default: + break; + } +#endif + return 0; +} diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..0146c61be0ab 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -297,12 +297,14 @@ static inline void set_mm(struct mm_struct *prev, * * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu, + struct task_struct *task) { #ifdef CONFIG_SMP cpumask_t *mask =3D &mm->context.icache_stale_mask; =20 - if (cpumask_test_cpu(cpu, mask)) { + if (cpumask_test_cpu(cpu, mask) || mm->context.force_icache_flush || + (task && task->thread.force_icache_flush)) { cpumask_clear_cpu(cpu, mask); /* * Ensure the remote hart's writes are visible to this hart. @@ -332,5 +334,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct= *next, =20 set_mm(prev, next, cpu); =20 - flush_icache_deferred(next, cpu); + flush_icache_deferred(next, cpu, task); } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..ec731dda5b8e 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,8 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f =20 +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 +# define PR_RISCV_CTX_SW_FENCEI_ON 0 +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 420d9cb9cc8e..e806a8a67c36 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,9 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef RISCV_SET_ICACHE_FLUSH_CTX +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) +#endif =20 /* * this is where the system-wide overflow UID and GID are defined, for @@ -2739,6 +2742,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, ar= g2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error =3D RISCV_V_GET_CONTROL(); break; + case PR_RISCV_SET_ICACHE_FLUSH_CTX: + error =3D RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); + break; default: error =3D -EINVAL; break; --=20 2.43.0 From nobody Fri Dec 26 07:20:45 2025 Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EA8354F96 for ; Mon, 8 Jan 2024 18:42:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="eDlG6tH2" Received: by mail-oa1-f51.google.com with SMTP id 586e51a60fabf-205f223639fso1606734fac.2 for ; Mon, 08 Jan 2024 10:42:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704739361; x=1705344161; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lcesxSICs9qqjU3mn/6A1YTx2ZHWyVmXZ47Xf1Piv0E=; b=eDlG6tH2zgcGycOb83uS5GjWn+wHjTI2RANNfk2+TEsjd3iw+s5xJ68E5pt2iSXKiO IKJ3iECmCONf9g9CBXiuEKBQU5wSdcn4Ow2Nqbwln8L9X7qLTx8+dj0OP1TSlQHwIwyf M14eq5/DKwlI9EHIc7DxNSwBUGegrJY5HkKCnem1Dv/M8n4kt4tzmHJ8YcGOumeVF5ts Hj8sdOToxOnsa4mFtjlmrEax4D+4lbOpATkPqtL7ijJIllPc8Yo98mMwmO7FW4NhXLbp 6Wnw3iL2plXFATQsK+hjfw4H1EPUtaQsXwmkeC97pGfBLPAWwY8TudSbHfye86hI682P ynBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704739361; x=1705344161; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lcesxSICs9qqjU3mn/6A1YTx2ZHWyVmXZ47Xf1Piv0E=; b=RzheCDqmyOfxdfR5AwvFMjHyS8NJXEg3FxBTlMkYGl6Sc8bEk/P0tsVDBcWDku1bwx aNiIhagUPppWX8Cw8JfOUmltgC3ieebLKuAv2PPFDiZo9BXMiHwfCKk/SBDv85fGnTId oWakdLlYBDzrCyoyzZ8YHc1VB2kaPtMz1J46qYO/rDPoO8rV7LWqM/2cIQamLDNZyPe9 gsTstjX5drJoXllZwvxJ8tw4cm9zcJgJ1YkdQa971xwWMFKjnakMT8GBgNWP/rEiEZxt XQ5FtJjBTFSZO1RlH8j7y81iAaSY+6YukAIMGnu2OQ9cD/sERTbm25ny9SBbdnDEHTtN DcxA== X-Gm-Message-State: AOJu0YwJn40jp+KU9Hdtgwjr6pRbSscrEl7mB8GL68e2z9ulPZq6sHPI 3jMOLkT3FE+YOub5k4msX1oWEqHzbufZyQ== X-Google-Smtp-Source: AGHT+IHUfVeCnv4iKNZVjJjiJFF2rvptuznnQATx/D78AfBQ3DUmNpAnx4Mu8VUhkskBrWEn/uojFQ== X-Received: by 2002:a05:6871:750f:b0:204:2c51:99a9 with SMTP id ny15-20020a056871750f00b002042c5199a9mr5736175oac.72.1704739361703; Mon, 08 Jan 2024 10:42:41 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id pp24-20020a0568709d1800b002044a0677adsm97860oab.8.2024.01.08.10.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 10:42:41 -0800 (PST) From: Charlie Jenkins Date: Mon, 08 Jan 2024 10:42:30 -0800 Subject: [PATCH v5 2/2] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240108-fencei-v5-2-aa1e51d7222f@rivosinc.com> References: <20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com> In-Reply-To: <20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704739355; l=3760; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=OS05nIxwBZL4G2IIyGllNjNhS5yx7iCRPhXs7gfJa/I=; b=xGpIlJ7LWvsBwbp5/el5+9Vw7b/vKKgIwAwZ1naQ8EmRCK7fdaRW4B6EP2ncbP9SDglCunL43 PdHrDoiKQJ7D1VgKO0b5I2TMy1Udfm+wfaDy5yuadv8GmlmMHhJARM7 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra --- Documentation/arch/riscv/cmodx.rst | 88 ++++++++++++++++++++++++++++++++++= ++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 89 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/= cmodx.rst new file mode 100644 index 000000000000..afd7086c222c --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,88 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V L= inux +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +CMODX is a programming technique where a program executes instructions tha= t were +modified by the program itself. Instruction storage and the instruction ca= che +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefo= re, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new har= t. If +migration occurs after the userspace synchronized the icache and instructi= on +storage with fence.i, the icache will no longer be clean. This is due to t= he +behavior of fence.i only affecting the hart that it is called on. Thus, th= e hart +that the task has been migrated to may not have synchronized instruction s= torage +and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() sys= call, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The p= rctl +changes the Linux ABI to allow userspace to emit icache flushing operation= s. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument.= The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. T= he +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a= zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value =3D get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, 0); + modify_instruction(); + + value =3D get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/= index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx =20 features =20 --=20 2.43.0