From nobody Fri Dec 26 11:23:27 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 424912D787; Fri, 5 Jan 2024 13:42:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [120.235.8.87]) by gateway (Coremail) with SMTP id _____8Dx_7thB5hlzFUCAA--.281S3; Fri, 05 Jan 2024 21:42:57 +0800 (CST) Received: from localhost.localdomain (unknown [120.235.8.87]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxC95WB5hlx4cDAA--.9475S2; Fri, 05 Jan 2024 21:42:56 +0800 (CST) From: Xiaochuan Mao To: Huacai Chen , Jiaxun Yang , Thomas Gleixner , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, maoxiaochuan@loongson.cn Subject: [PATCH] irqchip:Correct the offset value of interrupt status register Date: Fri, 5 Jan 2024 21:42:44 +0800 Message-Id: <20240105134244.13003-1-maoxiaochuan@loongson.cn> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: AQAAf8CxC95WB5hlx4cDAA--.9475S2 X-CM-SenderInfo: xpdr5xxdrfx3ldqnw6o6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj9xXoW7Wry8uryDtw4rAFyxXFyDXFc_yoWDXwbEgr WI9ws7Wr9Ykrn3KrW0yrWDZa4qkFyUW3WI9F1Svry5A347tw4ayw15u3WUGa1YyF4rZFn7 XryDKFyfZw17WosvyTuYvTs0mTUanT9S1TB71UUUUj7qnTZGkaVYY2UrUUUUj1kv1TuYvT s0mT0YCTnIWjqI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUI cSsGvfJTRUUUbS8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20x vaj40_Wr0E3s1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV WUJVW8JwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1ln4kS14v26r126r1DM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12 xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r12 6r1DMcIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64 vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1l4IxYO2xFxVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8V AvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E 14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07j5o7tUUUUU= Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" from 2k500/2k1000 mannual known that the offset value between the interrupt status register and the interrupt entry register is 0x20. Signed-off-by: Xiaochuan Mao --- drivers/irqchip/irq-loongson-liointc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index e4b33aed1c97..417b4c91ca67 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -28,7 +28,7 @@ =20 #define LIOINTC_INTC_CHIP_START 0x20 =20 -#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20) +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START) #define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) #define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) --=20 2.17.1