From nobody Fri Dec 26 13:32:34 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB216364CA for ; Fri, 5 Jan 2024 20:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b+74iGxi" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-40d76923ec4so18578495e9.3 for ; Fri, 05 Jan 2024 12:39:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704487154; x=1705091954; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uoGXe5xgeyMcaxsKtX0mK7Fdtz9TN7DoVNyEmbulNGQ=; b=b+74iGxiFny/X0uD2I9baxYAwL8tqGrgLSeH3JYrbpX7ByDofdhumh0c4K3erNOCFt QsvVJsgMUi/kegVXKG7G4+lycbc2ZeakFoZ0zJehFJaxE4OzMQVnAb98UuJ6b4YoSj4g pK9FbZf+8Pbll0ZQibPFyVPGXBEHPjR1vEel1nJYRMtVQ7dMg1lbiNs9NGSiQnfnR4nJ naWdKMR0nkih/mG6MI/C8yrzjSRBhSaNN8+eMql90T8S9up6DE8tpqFijLrJMhZ1Fy7/ xJN2G8xY+lyeSbm73+zbRhDYrYcvuBgBqsl0g2lX0r39s4Rw/lXEMgEtmXYoRE0Q6SOx tdgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704487154; x=1705091954; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uoGXe5xgeyMcaxsKtX0mK7Fdtz9TN7DoVNyEmbulNGQ=; b=XUE1ocZIZ7d6CI8YS09BxfipzzM7tThdfpS3zXMihn6EHX9le3T40F2jWibqSmaDM2 P9tXk06BdJOadkVny0ldN+T7JpHI8wO91T8CWg6c5xUxFVLxhnr1YPxnGzry6D6qQtkt lmFHYDgcz9trmQU1XGpNWDtOiD/Exe/c2N9bg/sg3ru//93n5BZ1GD9Ksco9mVqBce8h t1r0SupXrvhoSnq1DhEMTv2Sruim8UqRYHUtoIYyTp5brvCdPY7aHA8imTcZB66InFpr Ouw5F4otpQs/sTfcYw+f31toX0q4o5Xk4HJ9FqBl7n5Cqu1Btd42r2sC8s4fPI0yQu1i FbEA== X-Gm-Message-State: AOJu0YxVviBiILjuNOz1Sx1ytTJQPWw0pBVTkenUJODAq5BU6bH7W3bJ XvYB6sCcy6Z2/6TmsR/HUO4U57AMXMu4sQ== X-Google-Smtp-Source: AGHT+IE+NVS5K56b0UZo1wZZ8vm3IPSZTHkoGsOIswyn/dapJotPXDqWGREo3fTp1GPVUAI8EkbWUg== X-Received: by 2002:a05:600c:4194:b0:40e:3946:353c with SMTP id p20-20020a05600c419400b0040e3946353cmr38593wmh.15.1704487154170; Fri, 05 Jan 2024 12:39:14 -0800 (PST) Received: from [127.0.1.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id hn3-20020a05600ca38300b0040e398f8cafsm2283890wmb.31.2024.01.05.12.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jan 2024 12:39:13 -0800 (PST) From: Bryan O'Donoghue Date: Fri, 05 Jan 2024 20:39:07 +0000 Subject: [PATCH v2 3/4] arm64: dts: qcom: sc8280xp: camss: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240105-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v2-3-7a57b8b07398@linaro.org> References: <20240105-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v2-0-7a57b8b07398@linaro.org> In-Reply-To: <20240105-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v2-0-7a57b8b07398@linaro.org> To: Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-4e032 sc8280xp has four Camera Control Interface (CCI) blocks which pinout to two I2C master controllers for each CCI. The CCI I2C pins are not muxed so we define them in the dtsi. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 316 +++++++++++++++++++++++++++++= ++++ 1 file changed, 316 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index febf28356ff8..2d7ae19dda3a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3451,6 +3451,162 @@ usb_1_role_switch: endpoint { }; }; =20 + cci0: cci@ac4a000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci0_default>; + pinctrl-1 =3D <&cci0_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci1_default>; + pinctrl-1 =3D <&cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac4c000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4c000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci2_default>; + pinctrl-1 =3D <&cci2_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci3: cci@ac4d000 { + compatible =3D "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x0ac4d000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_3_CLK>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci3_default>; + pinctrl-1 =3D <&cci3_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sc8280xp-camcc"; reg =3D <0 0x0ad00000 0 0x20000>; @@ -4076,6 +4232,166 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 230>; wakeup-parent =3D <&pdc>; + + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio113", "gpio114"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio115", "gpio116"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio113", "gpio114"; + function =3D "cci_i2c"; + + drive-strength =3D <2>; /* 2 mA */ + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio115", "gpio116"; + function =3D "cci_i2c"; + + drive-strength =3D <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio10","gpio11"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins =3D "gpio123","gpio124"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio10","gpio11"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins =3D "gpio123","gpio124"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci2_default: cci2-default-state { + cci2_i2c0_default: cci2-i2c0-default-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins =3D "gpio117","gpio118"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci2_i2c1_default: cci2-i2c1-default-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins =3D "gpio12","gpio13"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci2_sleep: cci2-sleep-state { + cci2_i2c0_sleep: cci2-i2c0-sleep-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins =3D "gpio117","gpio118"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci2_i2c1_sleep: cci2-i2c1-sleep-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins =3D "gpio12","gpio13"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci3_default: cci3-default-state { + cci3_i2c0_default: cci3-i2c0-default-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins =3D "gpio145","gpio146"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci3_i2c1_default: cci3-i2c1-default-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins =3D "gpio164","gpio165"; + function =3D "cci_i2c"; + + bias-pull-up; + drive-strength =3D <2>; /* 2 mA */ + }; + }; + + cci3_sleep: cci3-sleep-state { + cci3_i2c0_sleep: cci3-i2c0-sleep-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins =3D "gpio145","gpio146"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + + cci3_i2c1_sleep: cci3-i2c1-sleep-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins =3D "gpio164","gpio165"; + function =3D "cci_i2c"; + + bias-pull-down; + drive-strength =3D <2>; /* 2 mA */ + }; + }; }; =20 apps_smmu: iommu@15000000 { --=20 2.42.0