From nobody Fri Dec 26 17:19:00 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32BB42230D for ; Thu, 4 Jan 2024 13:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b="e1s7/3EE" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-336746a545fso259960f8f.0 for ; Thu, 04 Jan 2024 05:02:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1704373324; x=1704978124; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HQIEpNJctaz16RzA/leTZqNcUN7vsgkXc8Xvi93qAho=; b=e1s7/3EE+MeuNW95g+yb4nI2EfzKykj8shaTLoibDu7D3m/ffNrI6tEAU6DA6QSoTA mbnGXGkLbXqOvSFgn1mDXvBUqyIV91SKIGuKK7zJPhRjRXPwh4eMBYE9UOX9lndUWwPw fCfoSjPUPU4PGZn2Q3DO5UfmCX8Ql7GfM1BtQ4AfGNg9CxcR40b4tn5XkYVhadTUsCpJ TFaJULVT6u5l6SYVa9Z9hqAzB6+liviUn725RIMw31MnRlyZFwUpIjUIKQN6BF2+NDnZ O4CwH+t/AGZoWaEy/u3AAn2Ug/tiCKBUj4FeAjcxA/5pwS+ZB9sYFG1Zkht3aWPNu4Gl lncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704373324; x=1704978124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HQIEpNJctaz16RzA/leTZqNcUN7vsgkXc8Xvi93qAho=; b=VVkzWdirdNilm59ACZ7gcah/u8r83sJctJm5sfApn88yvpelEqsgOHmKJPpWBKcTur l2UVbTvdRIAHaZ/tcZZofAaiaeOSLA9VrUdBKIjXrSN/5vMrXzZCflg16nKD+niOFqXX XcCP/j9B7Onk+yWLrKVHRaKXubkKPT1egkp0wpgvER1xQURHZcpCZYQf3IqZWMjkS9mS DyBpXdVM4rZLgGUegpZCyMdcmk8Jz6OWyvX1ejNcTOTC2B8bDouvQTx4mHwRPRnDs1TP 7HfF1yfzAS6rE8VHHN8sMYi9wPYdkJJjyzp4YNGi+g8AIbvmmfjH3IBPCKKoYTu6nr+t QaUA== X-Gm-Message-State: AOJu0Yzk1woSjl8SdpFvkpo9KpgXQJa3MyP8bNPEmmBJcGPZB3vlgCdu gCyc9SL9advt/XPjCU1+Yb6MUvWE5ai7PA== X-Google-Smtp-Source: AGHT+IEYrrjaOaf5/IBZBDz2VUcMEHweLF977kWhWHW+xRF7Tv9rMBKm8dg3stU9d6EnW3pR2nQiEQ== X-Received: by 2002:a5d:4576:0:b0:337:4f04:933c with SMTP id a22-20020a5d4576000000b003374f04933cmr318898wrc.54.1704373323681; Thu, 04 Jan 2024 05:02:03 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:5b69:3768:8459:8fee]) by smtp.gmail.com with ESMTPSA id w5-20020a5d5445000000b0033660f75d08sm32887387wrv.116.2024.01.04.05.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 05:02:03 -0800 (PST) From: Bartosz Golaszewski To: Kalle Valo , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon , Bjorn Helgaas , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Linus Walleij , Geert Uytterhoeven , Arnd Bergmann , Neil Armstrong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Marek Szyprowski , Peng Fan , Robert Richter , Dan Williams , Jonathan Cameron , Terry Bowman , Kuppuswamy Sathyanarayanan , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Huacai Chen , Alex Elder , Srini Kandagatla , Greg Kroah-Hartman Cc: linux-wireless@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Bartosz Golaszewski Subject: [RFC 1/9] arm64: dts: qcom: sm8250: describe the PCIe port Date: Thu, 4 Jan 2024 14:01:15 +0100 Message-Id: <20240104130123.37115-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240104130123.37115-1-brgl@bgdev.pl> References: <20240104130123.37115-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Improve the description of the PCIe topology by defining the port node at the SoC level. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 760501c1301a..fef9c314ce55 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2197,6 +2197,16 @@ pcie0: pcie@1c00000 { dma-coherent; =20 status =3D "disabled"; + + pcieport0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + bus-range =3D <0x01 0xff>; + }; }; =20 pcie0_phy: phy@1c06000 { --=20 2.40.1