From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 486591DFFC for ; Thu, 4 Jan 2024 08:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="gnoO3NhR" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a28aa47bd15so26852666b.2 for ; Thu, 04 Jan 2024 00:42:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357737; x=1704962537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oZHp7o9P6sSCcRzfgnf9GmPoPPKRvORDv/jTzo46w2U=; b=gnoO3NhRumgjV7Z0Syw3CYrkGh7S8dJx1wNs1Jyn0BEVJA/cDp1kas48bdLEuMjL4s DPO3HkFTWqsypPfJkshy7OAeWXV72nmIAayCp2EjfAbc30yLFvvM6FXzwQZdnqcFJSrV uaIo5WNt3ULggh7Wxh3EE82WRgwlnaK/amEYc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357737; x=1704962537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZHp7o9P6sSCcRzfgnf9GmPoPPKRvORDv/jTzo46w2U=; b=K839l0kb0bLFc9L6WC626xmCAJZxXQYMv9Mj20PnJUKgJeBSPMFmyEOVCpzV51EO2o oBezOUDnMrdpJAVcBoGVHp19yUGL2ea71b4GMRjRVnsSW8O9KfTCQWpbuA2x1CTO5Ife yul8sJAPwmP77xRbhuN89OPaFv5DCNuPaqCDhr/PBG6oMEFrz6Kt9eTMuLxwF3VyOEEE /NVxx/DcKPYlaMuR2W+CHU0kSmRdQBciuwNnkPjnfLAkDf73pckglxpIs+5JN3IxPdfz tXFFR4N7huk07IqL0f+VaicSU8S/2wySPjhpw52qX3jm91sCUiDeUUCJYJ4nAs6z/cls Ainw== X-Gm-Message-State: AOJu0Yw92XBzjs4upXnXidV0bBrZQpxWB73gGoKAhcfh/6QJ5MT2Nyac pxoK5Zuq+VpyBCpzRlGpEjPx7HEbRBXqlEDMgxuC6Gnai/I= X-Google-Smtp-Source: AGHT+IEgjg6OXhxaGFS6AoqJMMElnHIe5/EC7kG/2rh205kCzPflc399WybxDe97Efqnv/xAvhfCjA== X-Received: by 2002:a17:906:3185:b0:a28:6801:4a81 with SMTP id 5-20020a170906318500b00a2868014a81mr143573ejy.71.1704357734691; Thu, 04 Jan 2024 00:42:14 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Conor Dooley , Krzysztof Kozlowski , Lee Jones , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 1/8] dt-bindings: mfd: stm32f7: Add binding definition for DSI Date: Thu, 4 Jan 2024 09:41:41 +0100 Message-ID: <20240104084206.721824-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding definition for MIPI DSI Host controller. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Add Acked-by tag of Conor Dooley include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mf= d/stm32f7-rcc.h index 8d73a9c51e2b..a4e4f9271395 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -108,6 +108,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 =20 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECD941E51E for ; Thu, 4 Jan 2024 08:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="RDncaYam" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5563944b3dfso310490a12.3 for ; Thu, 04 Jan 2024 00:42:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357736; x=1704962536; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mmQnQzOW0HVCglZmRdERbSkiK/7LfpA/GFNr/QR6hMQ=; b=RDncaYam2gQJ+/YQIrSs8QsGLjI4TdTMWhwfSKE5goeb8S5bezuUdFEDTJnt6M3CmE 0r+w+iorWaWcyHrM+10K6488ttCrkU/84UFetH3OEoJJ6jOJXjLSB3icspt70KuX2q19 PA1VMxFN/EKmiSnVrwnNIexBKw7M3v1Uw8vF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357736; x=1704962536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mmQnQzOW0HVCglZmRdERbSkiK/7LfpA/GFNr/QR6hMQ=; b=OqHx28UKncXrZIO8yFeVndzLbGR2mvIRQW/uSsIMSwMvFRvRtblTULow5eKs0a5La9 NuA20DBWLFEIkzeNFdprxUPIKMhYcqZkdY4Vbtv06XsGTuQaB/54YGhkyavw6slnTl2V n7mYwDBoIdsGwbO5OM6IfZ0MjguRHbPzblTg91vi5Hdf6UM0LdDfEsYLKAs9zFCFtlUm ok9bnP6b/C/JIcYWgc/FzUtoJ8oftEEIvTzyKcb242C9V/mayAakrGrP9s/OJkOy3kvw u+IpbZ+vAe8CJ3nbQXfOlgXFbOjed6Paz0/wM2KnaAr4ezkpDWDGU0hpOND87jktXHWC TwDg== X-Gm-Message-State: AOJu0Yy2yxkYy7NrnWL9SlJy9Z5VdTSy+wvI2m6yVRPKthI5Swf7o+RM lObulNrgdXjnuJ6rCTFkpamzPiKFNME/JmUUTpe7VnJPlu8= X-Google-Smtp-Source: AGHT+IHSYPcVifjg7WaTw/q5gyvP9LIwxVEzE68+cuj6LtkM0cSU6dPkyvmWyHhxnoLtxki+J+/I7Q== X-Received: by 2002:a17:906:c244:b0:a23:35d2:cf97 with SMTP id bl4-20020a170906c24400b00a2335d2cf97mr149261ejb.64.1704357735999; Thu, 04 Jan 2024 00:42:15 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:15 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 2/8] ARM: dts: stm32: add DSI support on stm32f769 Date: Thu, 4 Jan 2024 09:41:42 +0100 Message-ID: <20240104084206.721824-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for MIPI DSI Host controller. Since MIPI DSI is not available on stm32f746, the patch adds the "stm32f769.dtsi" file containing the dsi node inside. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm= 32f769.dtsi new file mode 100644 index 000000000000..e09184f7079c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible =3D "st,stm32-dsi"; + reg =3D <0x40016c00 0x800>; + interrupts =3D <98>; + clocks =3D <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names =3D "apb"; + status =3D "disabled"; + }; + }; +}; --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D951EA66 for ; Thu, 4 Jan 2024 08:42:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="dj6Wrnhb" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a27e323fdd3so23274666b.2 for ; Thu, 04 Jan 2024 00:42:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357737; x=1704962537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/mPDNXnb7QOonc0RYCjpM23Kv+HuP4dW7ug+KwP2qeg=; b=dj6WrnhbOC0VgsvsSLpEqAt7r0lE0FfD33CyzxxHVAKHYnQ2elt05Oy8ZR51RpoKON FgX4I2/GHrV/BX6sUhVKUlB5y+trUCRv3LCQdmKSW8DeDGhOHUgLYcewnOiCE0H7/pMG nxHm+W+IoSGc8qCEw8yESE5mCXHH8UDPdjGoY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357737; x=1704962537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/mPDNXnb7QOonc0RYCjpM23Kv+HuP4dW7ug+KwP2qeg=; b=pzq8sAb/GZVG5QmYP7TJo+tHnunTLPGYjlXKOA6OA1kswJkYRX7s+B2tmFeuafLt/4 AGq22cGcwGwyIKauyP/kPhwqmpwxe/v51gXtdTasP7Ubks8QJjLXuh2lFlm0YYAP55OG faShP4XOjqGu+EKILnrdH+6X60/NZ9YXI0iljRbajAIcBgbmRUprVcTX7tzRRDUgrok0 1/5f8HL1rVGF2/ET3wHawcr4vvyO1lUujRsCf97pG6ozLtzInK+1gC1XG0cHzDC0GNvp 4uBews4kZjFm/6g1D8DwA5dSTz3ys9QNVmwdSyhW1kcGiJkg0ms0s62AxYLHyLehIxRT wXdg== X-Gm-Message-State: AOJu0YwfzfBGRhG0F7nSz8rTYugo9+sCasqDidSDa86HO66O/AnCRozz 0DJDTfoo90pvQUJvpQ0CX7z86HD6GZTjSQuiu0bVn22pRyA= X-Google-Smtp-Source: AGHT+IGMBrhk2BY1jgoVaREF+PbuJeKGAfw77EEhYC1B1egTY4WydDER/luU0S/HZKRgRr4SQBSKSQ== X-Received: by 2002:a17:906:9807:b0:a27:fa1b:def4 with SMTP id lm7-20020a170906980700b00a27fa1bdef4mr98499ejb.17.1704357737328; Thu, 04 Jan 2024 00:42:17 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:16 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 3/8] ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco Date: Thu, 4 Jan 2024 09:41:43 +0100 Message-ID: <20240104084206.721824-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the schematics of document UM2033, the power supply for the micro SD card is the same 3v3 voltage that is used to power other devices on the board. By generalizing the name of the voltage regulator, it can be referenced by other nodes in the device tree without creating misunderstandings. This patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769-disco.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 5d12ae25b327..8632bd866272 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -92,9 +92,9 @@ usbotg_hs_phy: usb-phy { clock-names =3D "main_clk"; }; =20 - mmc_vcard: mmc_vcard { + vcc_3v3: vcc_3v3 { compatible =3D "regulator-fixed"; - regulator-name =3D "mmc_vcard"; + regulator-name =3D "vcc_3v3"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; }; @@ -128,7 +128,7 @@ &rtc { =20 &sdio2 { status =3D "okay"; - vmmc-supply =3D <&mmc_vcard>; + vmmc-supply =3D <&vcc_3v3>; cd-gpios =3D <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names =3D "default", "opendrain", "sleep"; --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 856B3200D8 for ; Thu, 4 Jan 2024 08:42:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fH5zyrUY" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-55539cac143so320431a12.0 for ; Thu, 04 Jan 2024 00:42:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357738; x=1704962538; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c6lTYGwOZkH/q3mVT10Wfxgf2APvMbHICMTqCuHaYlQ=; b=fH5zyrUYCmZQGCg6NMEVdBFUpVIM58zto2elXL74n8DzVcZProaDlb4YICAInDAzBS RXwyTYm8nS/aORDJRstiLWLPMwU6eGpXbcqPoM/9phTc9BRaPtyuDYiHcZuScyQldFeJ ORfhp212RB0G0G/oH30ebFwvkSwmqtbQudcDE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357738; x=1704962538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c6lTYGwOZkH/q3mVT10Wfxgf2APvMbHICMTqCuHaYlQ=; b=aQ3jCD5U/JC1ymbb3lQhyjWNZvNrVPN591VLOF1feRjVr7dlDPouyPgMiqU0kj6yFi 9ZOxULYz3bR0w32wFgKnpXFqiwaEFMBAFLB1xro7uqACTayeBdIOnTklC3sxUj02j4ln 8rJkB8laTjUZ3refdOVr1bSUc5j3te5zlryqL+681IRFDeU4/Pt7vgYDn7KXfiPnltRJ DhGGza3xB3EOT2dKUqsVcWhnpNW2oU9NYXex+Rhhnd9ZUbIRKiX4qJu/wt8jn28+XGgP GcZIW3bqlxKrZWp6jWo8e1UcMUcSBqJoxBsjNMjI5hqsrC0aZQQi0BLkSqPSRO/GY1xz TjCg== X-Gm-Message-State: AOJu0YzHDTsO+4qGt8Q612U4tY84d0sGuSfZLSGd/Jdcy35dmk5OSgyu QMkVTi+v9o2yBr3TNd6EVlJxWA1M5MDYLuo6XpDF199Nn4Y= X-Google-Smtp-Source: AGHT+IEKMwSrOrJmtl4FyW+DrqXhhMIzLZ+2RtqvjY5/wkknrU8YbM1QoSDjBXN33+GQGSiBO6Mk+w== X-Received: by 2002:a17:906:cc50:b0:a27:e0ae:99a8 with SMTP id mm16-20020a170906cc5000b00a27e0ae99a8mr112579ejb.145.1704357738586; Thu, 04 Jan 2024 00:42:18 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:18 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 4/8] ARM: dts: stm32: add display support on stm32f769-disco Date: Thu, 4 Jan 2024 09:41:44 +0100 Message-ID: <20240104084206.721824-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds display support on the stm32f769-disco board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/st/stm32f769-disco.dts | 72 +++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index 8632bd866272..d1eb5f9c78bf 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ =20 /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include #include @@ -60,6 +60,19 @@ memory@c0000000 { reg =3D <0xC0000000 0x1000000>; }; =20 + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + linux,dma { + compatible =3D "shared-dma-pool"; + linux,dma-default; + no-map; + size =3D <0x100000>; + }; + }; + aliases { serial0 =3D &usart1; }; @@ -85,6 +98,13 @@ button-0 { }; }; =20 + panel_backlight: panel-backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&gpioi 14 GPIO_ACTIVE_HIGH>; + default-on; + status =3D "okay"; + }; + usbotg_hs_phy: usb-phy { #phy-cells =3D <0>; compatible =3D "usb-nop-xceiv"; @@ -114,6 +134,46 @@ &clk_hse { clock-frequency =3D <25000000>; }; =20 +&dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi_in: endpoint { + remote-endpoint =3D <<dc_out_dsi>; + }; + }; + + port@1 { + reg =3D <1>; + dsi_out: endpoint { + remote-endpoint =3D <&dsi_panel_in>; + }; + }; + }; + + panel0: panel-dsi@0 { + compatible =3D "orisetech,otm8009a"; + reg =3D <0>; /* dsi virtual channel (0..3) */ + reset-gpios =3D <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply =3D <&vcc_3v3>; + backlight =3D <&panel_backlight>; + status =3D "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins_b>; pinctrl-names =3D "default"; @@ -122,6 +182,16 @@ &i2c1 { status =3D "okay"; }; =20 +<dc { + status =3D "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + remote-endpoint =3D <&dsi_in>; + }; + }; +}; + &rtc { status =3D "okay"; }; --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11D42208A5 for ; Thu, 4 Jan 2024 08:42:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="KAsc15QE" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a279ce3aab9so27719666b.0 for ; Thu, 04 Jan 2024 00:42:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357740; x=1704962540; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sXGsllobW7FM1Bh/GFVmgfSyiJn/KRbyHxvKaq5XBd4=; b=KAsc15QEBJmaXfzxnVwACiUaOt2FradDeNE4DzOGDaEQC4XlT08SRnpMQc3rL1lEKt ieJ9gc4KmYkb/DQTreO+Spjf8BPX3oU7sF/Ei1ZHO5nXMNHfz4EwCkCCelRNT6V/EzSx icr+WG/yZ3wRBp0pCLNCUlOwN6VQhFRb3L5FE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357740; x=1704962540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sXGsllobW7FM1Bh/GFVmgfSyiJn/KRbyHxvKaq5XBd4=; b=k8119ylQ9cgX3kXhYDNwbFlYzH6a69/CzoMUPwmS3hAwpDO8TdzRRVW2z2VR7zUaam f8gU3c/cXBlcfeNBDP0lKFWodf+WaIQHx4ZIaJPJqg7WzAVm2pJpvr8QbUtJT0L//dsD 2ODwBYAJETctqFjdsaXS8De1i2ivHtRNBxI5kZIw5TZyaUoCfTs7umIpnpOIh6cI+O2O p41G72TmlcwbyaRDCgwVBj127pdkzq2zxh1VCvHOFEN1R+GUhKIhXrrSuwRz2eB/ZsUk nTetmgoIj0amNeawB8mlxmb8CJB4d7tvssNMol31pDVJcv6EMyaT/8U6OowdZ4R/Z6vF R0cQ== X-Gm-Message-State: AOJu0YxWgYSL8kDuooB6rPSmTQLMAZ97nLk3DCOD/wCqsVvf8MFN9+3t uNM3qaeSQjXovaAGoWX28dMDInx4+j9zW24C4hLUGA+bF+8= X-Google-Smtp-Source: AGHT+IHmEppr/O53EySgWZMtoqd5scwBe7uUi57gjWCkgd3DZxEW3k2aOYRvBqHMPyUXPJ0NsC2ihA== X-Received: by 2002:a17:906:e083:b0:a28:27df:b38 with SMTP id gh3-20020a170906e08300b00a2827df0b38mr88170ejb.201.1704357740231; Thu, 04 Jan 2024 00:42:20 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:19 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Conor Dooley , Daniel Vetter , David Airlie , Jessica Zhang , Krzysztof Kozlowski , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Rob Herring , Sam Ravnborg , Thomas Zimmermann , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v4 5/8] dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK Date: Thu, 4 Jan 2024 09:41:45 +0100 Message-ID: <20240104084206.721824-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij --- Changes in v4: - Put the "enum" list in alphabetical order Changes in v3: - Use "enum" to have less code changed Changes in v2: - Add a dash in front of each "items:" .../devicetree/bindings/display/panel/novatek,nt35510.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt3551= 0.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.ya= ml index bc92928c805b..a4afaff483b7 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: items: - - const: hydis,hva40wv1 + - enum: + - frida,frd400b25025 + - hydis,hva40wv1 - const: novatek,nt35510 description: This indicates the panel manufacturer of the panel that is in turn using the NT35510 panel driver. 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:21 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Andre Przywara , Conor Dooley , Gregory CLEMENT , Krzysztof Kozlowski , =?UTF-8?q?Leonard=20G=C3=B6hrs?= , Maxime Coquelin , Rob Herring , Sean Nyekjaer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 6/8] ARM: dts: add stm32f769-disco-mb1225-revb03-mb1166-reva09 Date: Thu, 4 Jan 2024 09:41:46 +0100 Message-ID: <20240104084206.721824-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As reported in the section 8.3 (i. e. Board revision history) of document UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes related to the board revisions addressed by the patch: - Board MB1225 revision B-03: - Memory MICRON MT48LC4M32B2B5-6A replaced by ISSI IS42S32400F-6BL - Board MB1166 revision A-09: - LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK The patch only adds the DTS support for the new display which belongs to to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Change the status of panel_backlight node to "disabled" - Delete backlight property from panel0 node. arch/arm/boot/dts/st/Makefile | 1 + ...2f769-disco-mb1225-revb03-mb1166-reva09.dts | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb11= 66-reva09.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 7892ad69b441..390dbd300a57 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32f469-disco.dtb \ stm32f746-disco.dtb \ stm32f769-disco.dtb \ + stm32f769-disco-mb1225-revb03-mb1166-reva09.dts \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva= 09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.d= ts new file mode 100644 index 000000000000..014cac192375 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi + */ + +#include "stm32f769-disco.dts" + +&panel_backlight { + status =3D "disabled"; +}; + +&panel0 { + compatible =3D "frida,frd400b25025", "novatek,nt35510"; + vddi-supply =3D <&vcc_3v3>; + vdd-supply =3D <&vcc_3v3>; + /delete-property/backlight; + /delete-property/power-supply; +}; --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EB011EA66 for ; Thu, 4 Jan 2024 08:42:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Yi+YaoiG" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a27733ae1dfso26631466b.3 for ; Thu, 04 Jan 2024 00:42:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1704357743; x=1704962543; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mFqXTGTlYTvcm2/UHRhYI2FZvx1qxWqmcpgcCxysnrA=; b=Yi+YaoiGL1fMB11ihiMz0zREt4WBD6+3I3BtvqYCGp9UzesNhJ9/JpAFAq3QZPMjSd /YhSCHYT9VBU5bxLzlWJHBvZ7FgEM4PfNIHwzm2w40RvlH8VVcsFUh+zBkfhPc7hKt8l +zO9UCaZAp2yK9Ga86yccrqaKGgUNp44iCb9s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704357743; x=1704962543; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mFqXTGTlYTvcm2/UHRhYI2FZvx1qxWqmcpgcCxysnrA=; b=IPs1rL6LyMEp2KJarLBrIO1vqqYDIpJw2e10XfpY8LDeaeGVE9k2GwYI3BRvkuco7m Ku5K5U/EMSrW4l/2rcFbUEecYtrh+izb32//Eu7BNtNMLIuA9JVrMvwyIsvSk7McdfcK DQTyP0u+wPHQm3gLyxb/U6/4Ia4TSDrKjLg94Bx0tN/Wlsm5LfSfU+bHreA4aXoKuvv1 8Y72FIU9rh1hrGguFPhPypP6bGf+QwM+VpX/HSN9o8ct6y0vyy76BCxiiEPeGfYGKZTT mP31+rVZeK7DrZg0cLZb8LZGVoONN1l9RC+7GTsv/7SYFS+socR94J2B7gPgntIXHDYP xj8w== X-Gm-Message-State: AOJu0YwTM12086OI2a6SMc6R519ntwCwjANc9xmI9RR+gz7Ayt9jo16c vIkB/qI+nUmkKRsjn4HWP1EY4fUxQopc17IGTMY4rBa/q2M= X-Google-Smtp-Source: AGHT+IEuTBHPoWheiV+CKAMknHpY/JDL10WWIA3jiYObZ5C8zEi03Cx9l7bfPyxX730VD0aqs75UJQ== X-Received: by 2002:a17:906:f810:b0:a26:8c28:1b67 with SMTP id kh16-20020a170906f81000b00a268c281b67mr67694ejb.260.1704357743090; Thu, 04 Jan 2024 00:42:23 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com (net-93-150-255-34.cust.vodafonedsl.it. [93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v4 7/8] drm/panel: nt35510: move hardwired parameters to configuration Date: Thu, 4 Jan 2024 09:41:47 +0100 Message-ID: <20240104084206.721824-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch, preparatory for future developments, move the hardwired parameters to configuration data to allow the addition of new NT35510-based panels. Signed-off-by: Dario Binacchi Reviewed-by: Linus Walleij Tested-by: Linus Walleij --- (no changes since v2) Changes in v2: - Re-write the patch [7/8] "drm/panel: nt35510: refactor panel initializati= on" in the same style as the original driver in order to maintain the same structure. drivers/gpu/drm/panel/panel-novatek-nt35510.c | 140 ++++++++++++++---- 1 file changed, 115 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/dr= m/panel/panel-novatek-nt35510.c index d6dceb858008..ce8969f48286 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -171,6 +171,10 @@ struct nt35510_config { * timing in the display controller. */ const struct drm_display_mode mode; + /** + * @mode_flags: DSI operation mode related flags + */ + unsigned long mode_flags; /** * @avdd: setting for AVDD ranging from 0x00 =3D 6.5V to 0x14 =3D 4.5V * in 0.1V steps the default is 0x05 which means 6.0V @@ -273,6 +277,100 @@ struct nt35510_config { * same layout of bytes as @vgp. */ u8 vgn[NT35510_P1_VGN_LEN]; + /** + * @dopctr: setting optional control for display + * ERR bits 0..1 in the first byte is the ERR pin output signal setting. + * 0 =3D Disable, ERR pin output low + * 1 =3D ERR pin output CRC error only + * 2 =3D ERR pin output ECC error only + * 3 =3D ERR pin output CRC and ECC error + * The default is 0. + * N565 bit 2 in the first byte is the 16-bit/pixel format selection. + * 0 =3D R[4:0] + G[5:3] & G[2:0] + B[4:0] + * 1 =3D G[2:0] + R[4:0] & B[4:0] + G[5:3] + * The default is 0. + * DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error + * reporting. + * 0 =3D reporting when error + * 1 =3D not reporting when error + * DSIM bit 4 in the first byte is the video mode data type enable + * 0 =3D Video mode data type disable + * 1 =3D Video mode data type enable + * The default is 0. + * DSIG bit 5 int the first byte is the generic r/w data type enable + * 0 =3D Generic r/w disable + * 1 =3D Generic r/w enable + * The default is 0. + * DSITE bit 6 in the first byte is TE line enable + * 0 =3D TE line is disabled + * 1 =3D TE line is enabled + * The default is 0. + * RAMKP bit 7 in the first byte is the frame memory keep/loss in + * sleep-in mode + * 0 =3D contents loss in sleep-in + * 1 =3D contents keep in sleep-in + * The default is 0. + * CRL bit 1 in the second byte is the source driver data shift + * direction selection. This bit is XOR operation with bit RSMX + * of 3600h command. + * 0 (RMSX =3D 0) =3D S1 -> S1440 + * 0 (RMSX =3D 1) =3D S1440 -> S1 + * 1 (RMSX =3D 0) =3D S1440 -> S1 + * 1 (RMSX =3D 1) =3D S1 -> S1440 + * The default is 0. + * CTB bit 2 in the second byte is the vertical scanning direction + * selection for gate control signals. This bit is XOR operation + * with bit ML of 3600h command. + * 0 (ML =3D 0) =3D Forward (top -> bottom) + * 0 (ML =3D 1) =3D Reverse (bottom -> top) + * 1 (ML =3D 0) =3D Reverse (bottom -> top) + * 1 (ML =3D 1) =3D Forward (top -> bottom) + * The default is 0. + * CRGB bit 3 in the second byte is RGB-BGR order selection. This + * bit is XOR operation with bit RGB of 3600h command. + * 0 (RGB =3D 0) =3D RGB/Normal + * 0 (RGB =3D 1) =3D BGR/RB swap + * 1 (RGB =3D 0) =3D BGR/RB swap + * 1 (RGB =3D 1) =3D RGB/Normal + * The default is 0. + * TE_PWR_SEL bit 4 in the second byte is the TE output voltage + * level selection (only valid when DSTB_SEL =3D 0 or DSTB_SEL =3D 1, + * VSEL =3D High and VDDI =3D 1.665~3.3V). + * 0 =3D TE output voltage level is VDDI + * 1 =3D TE output voltage level is VDDA + * The default is 0. + */ + u8 dopctr[NT35510_P0_DOPCTR_LEN]; + /** + * @madctl: Memory data access control + * RSMY bit 0 is flip vertical. Flips the display image top to down. + * RSMX bit 1 is flip horizontal. Flips the display image left to right. + * MH bit 2 is the horizontal refresh order. + * RGB bit 3 is the RGB-BGR order. + * 0 =3D RGB color sequence + * 1 =3D BGR color sequence + * ML bit 4 is the vertical refresh order. + * MV bit 5 is the row/column exchange. + * MX bit 6 is the column address order. + * MY bit 7 is the row address order. + */ + u8 madctl; + /** + * @sdhdtctr: source output data hold time + * 0x00..0x3F =3D 0..31.5us in steps of 0.5us + * The default is 0x05 =3D 2.5us. + */ + u8 sdhdtctr; + /** + * @gseqctr: EQ control for gate signals + * GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps + * of 0.5us. + * The default is 0x07 =3D 3.5us + * GREQ_XX[7:4]: time setting of EQ step for rising edge in steps + * of 0.5us. + * The default is 0x07 =3D 3.5us + */ + u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; /** * @sdeqctr: Source driver control settings, first byte is * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and @@ -536,46 +634,28 @@ static int nt35510_setup_display(struct nt35510 *nt) { struct mipi_dsi_device *dsi =3D to_mipi_dsi_device(nt->dev); const struct nt35510_config *conf =3D nt->conf; - u8 dopctr[NT35510_P0_DOPCTR_LEN]; - u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN]; - /* FIXME: set up any rotation (assume none for now) */ - u8 addr_mode =3D NT35510_ROTATE_0_SETTING; - u8 val; int ret; =20 - /* Enable TE, EoTP and RGB pixel format */ - dopctr[0] =3D NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | - NT35510_DOPCTR_0_N565; - dopctr[1] =3D NT35510_DOPCTR_1_CTB; ret =3D nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR, NT35510_P0_DOPCTR_LEN, - dopctr); + conf->dopctr); if (ret) return ret; =20 - ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode, - sizeof(addr_mode)); + ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl, + sizeof(conf->madctl)); if (ret < 0) return ret; =20 - /* - * Source data hold time, default 0x05 =3D 2.5us - * 0x00..0x3F =3D 0 .. 31.5us in steps of 0.5us - * 0x0A =3D 5us - */ - val =3D 0x0A; - ret =3D mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val, - sizeof(val)); + ret =3D mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr, + sizeof(conf->sdhdtctr)); if (ret < 0) return ret; =20 - /* EQ control for gate signals, 0x00 =3D 0 us */ - gseqctr[0] =3D 0x00; - gseqctr[1] =3D 0x00; ret =3D nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR, NT35510_P0_GSEQCTR_LEN, - gseqctr); + conf->gseqctr); if (ret) return ret; =20 @@ -896,7 +976,6 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) */ dsi->hs_rate =3D 349440000; dsi->lp_rate =3D 9600000; - dsi->mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS; =20 /* * Every new incarnation of this display must have a unique @@ -908,6 +987,8 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return -ENODEV; } =20 + dsi->mode_flags =3D nt->conf->mode_flags; + nt->supplies[0].supply =3D "vdd"; /* 2.3-4.8 V */ nt->supplies[1].supply =3D "vddi"; /* 1.65-3.3V */ ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies), @@ -1030,6 +1111,7 @@ static const struct nt35510_config nt35510_hydis_hva4= 0wv1 =3D { .vtotal =3D 800 + 2 + 0 + 5, /* VBP =3D 5 */ .flags =3D 0, }, + .mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS, /* 0x09: AVDD =3D 5.6V */ .avdd =3D { 0x09, 0x09, 0x09 }, /* 0x34: PCK =3D Hsync/2, BTP =3D 2 x VDDB */ @@ -1050,6 +1132,14 @@ static const struct nt35510_config nt35510_hydis_hva= 40wv1 =3D { .vgp =3D { 0x00, 0xA3, 0x00 }, /* VGMP: 0x0A3 =3D 5.0375V, VGSP =3D 0V */ .vgn =3D { 0x00, 0xA3, 0x00 }, + /* Enable TE, EoTP and RGB pixel format */ + .dopctr =3D { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | + NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB }, + .madctl =3D NT35510_ROTATE_180_SETTING, + /* 0x0A: SDT =3D 5 us */ + .sdhdtctr =3D 0x0A, + /* EQ control for gate signals, 0x00 =3D 0 us */ + .gseqctr =3D { 0x00, 0x00 }, /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */ .sdeqctr =3D { 0x01, 0x05, 0x05, 0x05 }, /* SDVPCTR: Normal operation off color during v porch */ --=20 2.43.0 From nobody Fri Dec 26 15:30:46 2025 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C598120B3B for ; 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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id wh14-20020a170906fd0e00b00a233efe6aa7sm13495704ejb.51.2024.01.04.00.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 00:42:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v4 8/8] drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK Date: Thu, 4 Jan 2024 09:41:48 +0100 Message-ID: <20240104084206.721824-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> References: <20240104084206.721824-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The initialization commands are taken from the STMicroelectronics driver found at [1]. To ensure backward compatibility, flags have been added to enable gamma correction setting and display control. In other cases, registers have been set to their default values according to the specifications found in the datasheet. [1] https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/B= SP/Components/nt35510/ Signed-off-by: Dario Binacchi Reviewed-by: Linus Walleij --- (no changes since v2) Changes in v2: - Re-write the patch [8/8] "drm/panel: nt35510: support FRIDA FRD400B25025-= A-CTK" in the same style as the original driver. drivers/gpu/drm/panel/panel-novatek-nt35510.c | 282 ++++++++++++++++-- 1 file changed, 251 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/dr= m/panel/panel-novatek-nt35510.c index ce8969f48286..c85dd0d0829d 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -36,6 +36,9 @@ #include #include =20 +#define NT35510_CMD_CORRECT_GAMMA BIT(0) +#define NT35510_CMD_CONTROL_DISPLAY BIT(1) + #define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */ #define MCS_CMD_READ_ID1 0xDA #define MCS_CMD_READ_ID2 0xDB @@ -112,18 +115,33 @@ /* AVDD and AVEE setting 3 bytes */ #define NT35510_P1_AVDD_LEN 3 #define NT35510_P1_AVEE_LEN 3 +#define NT35510_P1_VCL_LEN 3 #define NT35510_P1_VGH_LEN 3 #define NT35510_P1_VGL_LEN 3 #define NT35510_P1_VGP_LEN 3 #define NT35510_P1_VGN_LEN 3 +#define NT35510_P1_VCMOFF_LEN 2 /* BT1CTR thru BT5CTR setting 3 bytes */ #define NT35510_P1_BT1CTR_LEN 3 #define NT35510_P1_BT2CTR_LEN 3 +#define NT35510_P1_BT3CTR_LEN 3 #define NT35510_P1_BT4CTR_LEN 3 #define NT35510_P1_BT5CTR_LEN 3 /* 52 gamma parameters times two per color: positive and negative */ #define NT35510_P1_GAMMA_LEN 52 =20 +#define NT35510_WRCTRLD_BCTRL BIT(5) +#define NT35510_WRCTRLD_A BIT(4) +#define NT35510_WRCTRLD_DD BIT(3) +#define NT35510_WRCTRLD_BL BIT(2) +#define NT35510_WRCTRLD_DB BIT(1) +#define NT35510_WRCTRLD_G BIT(0) + +#define NT35510_WRCABC_OFF 0 +#define NT35510_WRCABC_UI_MODE 1 +#define NT35510_WRCABC_STILL_MODE 2 +#define NT35510_WRCABC_MOVING_MODE 3 + /** * struct nt35510_config - the display-specific NT35510 configuration * @@ -175,6 +193,10 @@ struct nt35510_config { * @mode_flags: DSI operation mode related flags */ unsigned long mode_flags; + /** + * @cmds: enable DSI commands + */ + u32 cmds; /** * @avdd: setting for AVDD ranging from 0x00 =3D 6.5V to 0x14 =3D 4.5V * in 0.1V steps the default is 0x05 which means 6.0V @@ -224,6 +246,25 @@ struct nt35510_config { * The defaults are 4 and 3 yielding 0x34 */ u8 bt2ctr[NT35510_P1_BT2CTR_LEN]; + /** + * @vcl: setting for VCL ranging from 0x00 =3D -2.5V to 0x11 =3D -4.0V + * in 1V steps, the default is 0x00 which means -2.5V + */ + u8 vcl[NT35510_P1_VCL_LEN]; + /** + * @bt3ctr: setting for boost power control for the VCL step-up + * circuit (3) + * bits 0..2 in the lower nibble controls CLCK, the booster clock + * frequency, the values are the same as for PCK in @bt1ctr. + * bits 4..5 in the upper nibble controls BTCL, the boosting + * amplification for the step-up circuit. + * 0 =3D Disable + * 1 =3D -0.5 x VDDB + * 2 =3D -1 x VDDB + * 3 =3D -2 x VDDB + * The defaults are 4 and 2 yielding 0x24 + */ + u8 bt3ctr[NT35510_P1_BT3CTR_LEN]; /** * @vgh: setting for VGH ranging from 0x00 =3D 7.0V to 0x0B =3D 18.0V * in 1V steps, the default is 0x08 which means 15V @@ -277,6 +318,19 @@ struct nt35510_config { * same layout of bytes as @vgp. */ u8 vgn[NT35510_P1_VGN_LEN]; + /** + * @vcmoff: setting the DC VCOM offset voltage + * The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4. + * The second byte contains bits 0..7 of VCM. + * VCMOFFSEL the common voltage offset mode. + * VCMOFFSEL 0x00 =3D VCOM .. 0x01 Gamma. + * The default is 0x00. + * VCM the VCOM output voltage (VCMOFFSEL =3D 0) or the internal register + * offset for gamma voltage (VCMOFFSEL =3D 1). + * VCM 0x00 =3D 0V/0 .. 0x118 =3D 3.5V/280 in steps of 12.5mV/1step + * The default is 0x00 =3D 0V/0. + */ + u8 vcmoff[NT35510_P1_VCMOFF_LEN]; /** * @dopctr: setting optional control for display * ERR bits 0..1 in the first byte is the ERR pin output signal setting. @@ -441,6 +495,43 @@ struct nt35510_config { * @gamma_corr_neg_b: Blue gamma correction parameters, negative */ u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN]; + /** + * @wrdisbv: write display brightness + * 0x00 value means the lowest brightness and 0xff value means + * the highest brightness. + * The default is 0x00. + */ + u8 wrdisbv; + /** + * @wrctrld: write control display + * G bit 0 selects gamma curve: 0 =3D Manual, 1 =3D Automatic + * DB bit 1 selects display brightness: 0 =3D Manual, 1 =3D Automatic + * BL bit 2 controls backlight control: 0 =3D Off, 1 =3D On + * DD bit 3 controls display dimming: 0 =3D Off, 1 =3D On + * A bit 4 controls LABC block: 0 =3D Off, 1 =3D On + * BCTRL bit 5 controls brightness block: 0 =3D Off, 1 =3D On + */ + u8 wrctrld; + /** + * @wrcabc: write content adaptive brightness control + * There is possible to use 4 different modes for content adaptive + * image functionality: + * 0: Off + * 1: User Interface Image (UI-Mode) + * 2: Still Picture Image (Still-Mode) + * 3: Moving Picture Image (Moving-Mode) + * The default is 0 + */ + u8 wrcabc; + /** + * @wrcabcmb: write CABC minimum brightness + * Set the minimum brightness value of the display for CABC + * function. + * 0x00 value means the lowest brightness for CABC and 0xff + * value means the highest brightness for CABC. + * The default is 0x00. + */ + u8 wrcabcmb; }; =20 /** @@ -584,6 +675,16 @@ static int nt35510_setup_power(struct nt35510 *nt) nt->conf->bt2ctr); if (ret) return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SETVCL, + NT35510_P1_VCL_LEN, + nt->conf->vcl); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_BT3CTR, + NT35510_P1_BT3CTR_LEN, + nt->conf->bt3ctr); + if (ret) + return ret; ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SETVGH, NT35510_P1_VGH_LEN, nt->conf->vgh); @@ -620,6 +721,12 @@ static int nt35510_setup_power(struct nt35510 *nt) if (ret) return ret; =20 + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SETVCMOFF, + NT35510_P1_VCMOFF_LEN, + nt->conf->vcmoff); + if (ret) + return ret; + /* Typically 10 ms */ usleep_range(10000, 20000); =20 @@ -799,36 +906,38 @@ static int nt35510_power_on(struct nt35510 *nt) if (ret) return ret; =20 - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_r); - if (ret) - return ret; - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_g); - if (ret) - return ret; - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_pos_b); - if (ret) - return ret; - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_r); - if (ret) - return ret; - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_g); - if (ret) - return ret; - ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, - NT35510_P1_GAMMA_LEN, - nt->conf->gamma_corr_neg_b); - if (ret) - return ret; + if (nt->conf->cmds & NT35510_CMD_CORRECT_GAMMA) { + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_r); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_g); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_pos_b); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_r); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_g); + if (ret) + return ret; + ret =3D nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, + NT35510_P1_GAMMA_LEN, + nt->conf->gamma_corr_neg_b); + if (ret) + return ret; + } =20 /* Set up stuff in manufacturer control, page 0 */ ret =3D nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, @@ -907,6 +1016,26 @@ static int nt35510_prepare(struct drm_panel *panel) /* Up to 120 ms */ usleep_range(120000, 150000); =20 + if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY) { + ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, + &nt->conf->wrctrld, + sizeof(nt->conf->wrctrld)); + if (ret < 0) + return ret; + + ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE, + &nt->conf->wrcabc, + sizeof(nt->conf->wrcabc)); + if (ret < 0) + return ret; + + ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, + &nt->conf->wrcabcmb, + sizeof(nt->conf->wrcabcmb)); + if (ret < 0) + return ret; + } + ret =3D mipi_dsi_dcs_set_display_on(dsi); if (ret) { dev_err(nt->dev, "failed to turn display on (%d)\n", ret); @@ -1033,7 +1162,10 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return PTR_ERR(bl); } bl->props.max_brightness =3D 255; - bl->props.brightness =3D 255; + if (nt->conf->cmds & NT35510_CMD_CONTROL_DISPLAY) + bl->props.brightness =3D nt->conf->wrdisbv; + else + bl->props.brightness =3D 255; bl->props.power =3D FB_BLANK_POWERDOWN; nt->panel.backlight =3D bl; } @@ -1112,6 +1244,7 @@ static const struct nt35510_config nt35510_hydis_hva4= 0wv1 =3D { .flags =3D 0, }, .mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS, + .cmds =3D NT35510_CMD_CORRECT_GAMMA, /* 0x09: AVDD =3D 5.6V */ .avdd =3D { 0x09, 0x09, 0x09 }, /* 0x34: PCK =3D Hsync/2, BTP =3D 2 x VDDB */ @@ -1120,6 +1253,10 @@ static const struct nt35510_config nt35510_hydis_hva= 40wv1 =3D { .avee =3D { 0x09, 0x09, 0x09 }, /* 0x24: NCK =3D Hsync/2, BTN =3D -2 x VDDB */ .bt2ctr =3D { 0x24, 0x24, 0x24 }, + /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -2.5V */ + .vcl =3D { 0x00, 0x00, 0x00 }, + /* 0x24: CLCK =3D Hsync/2, BTN =3D -1 x VDDB */ + .bt3ctr =3D { 0x24, 0x24, 0x24 }, /* 0x05 =3D 12V */ .vgh =3D { 0x05, 0x05, 0x05 }, /* 0x24: NCKA =3D Hsync/2, VGH =3D 2 x AVDD - AVEE */ @@ -1132,6 +1269,8 @@ static const struct nt35510_config nt35510_hydis_hva4= 0wv1 =3D { .vgp =3D { 0x00, 0xA3, 0x00 }, /* VGMP: 0x0A3 =3D 5.0375V, VGSP =3D 0V */ .vgn =3D { 0x00, 0xA3, 0x00 }, + /* VCMOFFSEL =3D VCOM voltage offset mode, VCM =3D 0V */ + .vcmoff =3D { 0x00, 0x00 }, /* Enable TE, EoTP and RGB pixel format */ .dopctr =3D { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB }, @@ -1163,7 +1302,88 @@ static const struct nt35510_config nt35510_hydis_hva= 40wv1 =3D { .gamma_corr_neg_b =3D { NT35510_GAMMA_NEG_DEFAULT }, }; =20 +static const struct nt35510_config nt35510_frida_frd400b25025 =3D { + .width_mm =3D 52, + .height_mm =3D 86, + .mode =3D { + .clock =3D 23000, + .hdisplay =3D 480, + .hsync_start =3D 480 + 34, /* HFP =3D 34 */ + .hsync_end =3D 480 + 34 + 2, /* HSync =3D 2 */ + .htotal =3D 480 + 34 + 2 + 34, /* HBP =3D 34 */ + .vdisplay =3D 800, + .vsync_start =3D 800 + 15, /* VFP =3D 15 */ + .vsync_end =3D 800 + 15 + 12, /* VSync =3D 12 */ + .vtotal =3D 800 + 15 + 12 + 15, /* VBP =3D 15 */ + .flags =3D 0, + }, + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM, + .cmds =3D NT35510_CMD_CONTROL_DISPLAY, + /* 0x03: AVDD =3D 6.2V */ + .avdd =3D { 0x03, 0x03, 0x03 }, + /* 0x46: PCK =3D 2 x Hsync, BTP =3D 2.5 x VDDB */ + .bt1ctr =3D { 0x46, 0x46, 0x46 }, + /* 0x03: AVEE =3D -6.2V */ + .avee =3D { 0x03, 0x03, 0x03 }, + /* 0x36: PCK =3D 2 x Hsync, BTP =3D 2 x VDDB */ + .bt2ctr =3D { 0x36, 0x36, 0x36 }, + /* VBCLA: -2.5V, VBCLB: -2.5V, VBCLC: -3.5V */ + .vcl =3D { 0x00, 0x00, 0x02 }, + /* 0x26: CLCK =3D 2 x Hsync, BTN =3D -1 x VDDB */ + .bt3ctr =3D { 0x26, 0x26, 0x26 }, + /* 0x09 =3D 16V */ + .vgh =3D { 0x09, 0x09, 0x09 }, + /* 0x36: HCK =3D 2 x Hsync, VGH =3D 2 x AVDD - AVEE */ + .bt4ctr =3D { 0x36, 0x36, 0x36 }, + /* 0x08 =3D -10V */ + .vgl =3D { 0x08, 0x08, 0x08 }, + /* 0x26: LCK =3D 2 x Hsync, VGL =3D AVDD + VCL - AVDD */ + .bt5ctr =3D { 0x26, 0x26, 0x26 }, + /* VGMP: 0x080 =3D 4.6V, VGSP =3D 0V */ + .vgp =3D { 0x00, 0x80, 0x00 }, + /* VGMP: 0x080 =3D 4.6V, VGSP =3D 0V */ + .vgn =3D { 0x00, 0x80, 0x00 }, + /* VCMOFFSEL =3D VCOM voltage offset mode, VCM =3D -1V */ + .vcmoff =3D { 0x00, 0x50 }, + .dopctr =3D { NT35510_DOPCTR_0_RAMKP | NT35510_DOPCTR_0_DSITE | + NT35510_DOPCTR_0_DSIG | NT35510_DOPCTR_0_DSIM | + NT35510_DOPCTR_0_EOTP | NT35510_DOPCTR_0_N565, 0 }, + .madctl =3D NT35510_ROTATE_180_SETTING, + /* 0x03: SDT =3D 1.5 us */ + .sdhdtctr =3D 0x03, + /* EQ control for gate signals, 0x00 =3D 0 us */ + .gseqctr =3D { 0x00, 0x00 }, + /* SDEQCTR: source driver EQ mode 2, 1 us rise time on each step */ + .sdeqctr =3D { 0x01, 0x02, 0x02, 0x02 }, + /* SDVPCTR: Normal operation off color during v porch */ + .sdvpctr =3D 0x01, + /* T1: number of pixel clocks on one scanline: 0x184 =3D 389 clocks */ + .t1 =3D 0x0184, + /* VBP: vertical back porch toward the panel */ + .vbp =3D 0x1C, + /* VFP: vertical front porch toward the panel */ + .vfp =3D 0x1C, + /* PSEL: divide pixel clock 23MHz with 1 (no clock downscaling) */ + .psel =3D 0, + /* DPTMCTR12: 0x03: LVGL =3D VGLX, overlap mode, swap R->L O->E */ + .dpmctr12 =3D { 0x03, 0x00, 0x00, }, + /* write display brightness */ + .wrdisbv =3D 0x7f, + /* write control display */ + .wrctrld =3D NT35510_WRCTRLD_BCTRL | NT35510_WRCTRLD_DD | + NT35510_WRCTRLD_BL, + /* write content adaptive brightness control */ + .wrcabc =3D NT35510_WRCABC_STILL_MODE, + /* write CABC minimum brightness */ + .wrcabcmb =3D 0xff, +}; + static const struct of_device_id nt35510_of_match[] =3D { + { + .compatible =3D "frida,frd400b25025", + .data =3D &nt35510_frida_frd400b25025, + }, { .compatible =3D "hydis,hva40wv1", .data =3D &nt35510_hydis_hva40wv1, --=20 2.43.0