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[93.150.255.34]) by smtp.gmail.com with ESMTPSA id d3-20020a056402000300b00553772c2968sm18530735edu.82.2024.01.03.23.24.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 23:24:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Alexandre Torgue , Dario Binacchi , Daniel Vetter , David Airlie , Jessica Zhang , Linus Walleij , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Sam Ravnborg , Thomas Zimmermann , dri-devel@lists.freedesktop.org Subject: [PATCH v3 7/8] drm/panel: nt35510: move hardwired parameters to configuration Date: Thu, 4 Jan 2024 08:23:43 +0100 Message-ID: <20240104072407.41290-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240104072407.41290-1-dario.binacchi@amarulasolutions.com> References: <20240104072407.41290-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch, preparatory for future developments, move the hardwired parameters to configuration data to allow the addition of new NT35510-based panels. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Re-write the patch [7/8] "drm/panel: nt35510: refactor panel initializati= on" in the same style as the original driver in order to maintain the same structure. drivers/gpu/drm/panel/panel-novatek-nt35510.c | 140 ++++++++++++++---- 1 file changed, 115 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/dr= m/panel/panel-novatek-nt35510.c index d6dceb858008..ce8969f48286 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -171,6 +171,10 @@ struct nt35510_config { * timing in the display controller. */ const struct drm_display_mode mode; + /** + * @mode_flags: DSI operation mode related flags + */ + unsigned long mode_flags; /** * @avdd: setting for AVDD ranging from 0x00 =3D 6.5V to 0x14 =3D 4.5V * in 0.1V steps the default is 0x05 which means 6.0V @@ -273,6 +277,100 @@ struct nt35510_config { * same layout of bytes as @vgp. */ u8 vgn[NT35510_P1_VGN_LEN]; + /** + * @dopctr: setting optional control for display + * ERR bits 0..1 in the first byte is the ERR pin output signal setting. + * 0 =3D Disable, ERR pin output low + * 1 =3D ERR pin output CRC error only + * 2 =3D ERR pin output ECC error only + * 3 =3D ERR pin output CRC and ECC error + * The default is 0. + * N565 bit 2 in the first byte is the 16-bit/pixel format selection. + * 0 =3D R[4:0] + G[5:3] & G[2:0] + B[4:0] + * 1 =3D G[2:0] + R[4:0] & B[4:0] + G[5:3] + * The default is 0. + * DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error + * reporting. + * 0 =3D reporting when error + * 1 =3D not reporting when error + * DSIM bit 4 in the first byte is the video mode data type enable + * 0 =3D Video mode data type disable + * 1 =3D Video mode data type enable + * The default is 0. + * DSIG bit 5 int the first byte is the generic r/w data type enable + * 0 =3D Generic r/w disable + * 1 =3D Generic r/w enable + * The default is 0. + * DSITE bit 6 in the first byte is TE line enable + * 0 =3D TE line is disabled + * 1 =3D TE line is enabled + * The default is 0. + * RAMKP bit 7 in the first byte is the frame memory keep/loss in + * sleep-in mode + * 0 =3D contents loss in sleep-in + * 1 =3D contents keep in sleep-in + * The default is 0. + * CRL bit 1 in the second byte is the source driver data shift + * direction selection. This bit is XOR operation with bit RSMX + * of 3600h command. + * 0 (RMSX =3D 0) =3D S1 -> S1440 + * 0 (RMSX =3D 1) =3D S1440 -> S1 + * 1 (RMSX =3D 0) =3D S1440 -> S1 + * 1 (RMSX =3D 1) =3D S1 -> S1440 + * The default is 0. + * CTB bit 2 in the second byte is the vertical scanning direction + * selection for gate control signals. This bit is XOR operation + * with bit ML of 3600h command. + * 0 (ML =3D 0) =3D Forward (top -> bottom) + * 0 (ML =3D 1) =3D Reverse (bottom -> top) + * 1 (ML =3D 0) =3D Reverse (bottom -> top) + * 1 (ML =3D 1) =3D Forward (top -> bottom) + * The default is 0. + * CRGB bit 3 in the second byte is RGB-BGR order selection. This + * bit is XOR operation with bit RGB of 3600h command. + * 0 (RGB =3D 0) =3D RGB/Normal + * 0 (RGB =3D 1) =3D BGR/RB swap + * 1 (RGB =3D 0) =3D BGR/RB swap + * 1 (RGB =3D 1) =3D RGB/Normal + * The default is 0. + * TE_PWR_SEL bit 4 in the second byte is the TE output voltage + * level selection (only valid when DSTB_SEL =3D 0 or DSTB_SEL =3D 1, + * VSEL =3D High and VDDI =3D 1.665~3.3V). + * 0 =3D TE output voltage level is VDDI + * 1 =3D TE output voltage level is VDDA + * The default is 0. + */ + u8 dopctr[NT35510_P0_DOPCTR_LEN]; + /** + * @madctl: Memory data access control + * RSMY bit 0 is flip vertical. Flips the display image top to down. + * RSMX bit 1 is flip horizontal. Flips the display image left to right. + * MH bit 2 is the horizontal refresh order. + * RGB bit 3 is the RGB-BGR order. + * 0 =3D RGB color sequence + * 1 =3D BGR color sequence + * ML bit 4 is the vertical refresh order. + * MV bit 5 is the row/column exchange. + * MX bit 6 is the column address order. + * MY bit 7 is the row address order. + */ + u8 madctl; + /** + * @sdhdtctr: source output data hold time + * 0x00..0x3F =3D 0..31.5us in steps of 0.5us + * The default is 0x05 =3D 2.5us. + */ + u8 sdhdtctr; + /** + * @gseqctr: EQ control for gate signals + * GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps + * of 0.5us. + * The default is 0x07 =3D 3.5us + * GREQ_XX[7:4]: time setting of EQ step for rising edge in steps + * of 0.5us. + * The default is 0x07 =3D 3.5us + */ + u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; /** * @sdeqctr: Source driver control settings, first byte is * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and @@ -536,46 +634,28 @@ static int nt35510_setup_display(struct nt35510 *nt) { struct mipi_dsi_device *dsi =3D to_mipi_dsi_device(nt->dev); const struct nt35510_config *conf =3D nt->conf; - u8 dopctr[NT35510_P0_DOPCTR_LEN]; - u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN]; - /* FIXME: set up any rotation (assume none for now) */ - u8 addr_mode =3D NT35510_ROTATE_0_SETTING; - u8 val; int ret; =20 - /* Enable TE, EoTP and RGB pixel format */ - dopctr[0] =3D NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | - NT35510_DOPCTR_0_N565; - dopctr[1] =3D NT35510_DOPCTR_1_CTB; ret =3D nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR, NT35510_P0_DOPCTR_LEN, - dopctr); + conf->dopctr); if (ret) return ret; =20 - ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode, - sizeof(addr_mode)); + ret =3D mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl, + sizeof(conf->madctl)); if (ret < 0) return ret; =20 - /* - * Source data hold time, default 0x05 =3D 2.5us - * 0x00..0x3F =3D 0 .. 31.5us in steps of 0.5us - * 0x0A =3D 5us - */ - val =3D 0x0A; - ret =3D mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val, - sizeof(val)); + ret =3D mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr, + sizeof(conf->sdhdtctr)); if (ret < 0) return ret; =20 - /* EQ control for gate signals, 0x00 =3D 0 us */ - gseqctr[0] =3D 0x00; - gseqctr[1] =3D 0x00; ret =3D nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR, NT35510_P0_GSEQCTR_LEN, - gseqctr); + conf->gseqctr); if (ret) return ret; =20 @@ -896,7 +976,6 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) */ dsi->hs_rate =3D 349440000; dsi->lp_rate =3D 9600000; - dsi->mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS; =20 /* * Every new incarnation of this display must have a unique @@ -908,6 +987,8 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) return -ENODEV; } =20 + dsi->mode_flags =3D nt->conf->mode_flags; + nt->supplies[0].supply =3D "vdd"; /* 2.3-4.8 V */ nt->supplies[1].supply =3D "vddi"; /* 1.65-3.3V */ ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies), @@ -1030,6 +1111,7 @@ static const struct nt35510_config nt35510_hydis_hva4= 0wv1 =3D { .vtotal =3D 800 + 2 + 0 + 5, /* VBP =3D 5 */ .flags =3D 0, }, + .mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS, /* 0x09: AVDD =3D 5.6V */ .avdd =3D { 0x09, 0x09, 0x09 }, /* 0x34: PCK =3D Hsync/2, BTP =3D 2 x VDDB */ @@ -1050,6 +1132,14 @@ static const struct nt35510_config nt35510_hydis_hva= 40wv1 =3D { .vgp =3D { 0x00, 0xA3, 0x00 }, /* VGMP: 0x0A3 =3D 5.0375V, VGSP =3D 0V */ .vgn =3D { 0x00, 0xA3, 0x00 }, + /* Enable TE, EoTP and RGB pixel format */ + .dopctr =3D { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | + NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB }, + .madctl =3D NT35510_ROTATE_180_SETTING, + /* 0x0A: SDT =3D 5 us */ + .sdhdtctr =3D 0x0A, + /* EQ control for gate signals, 0x00 =3D 0 us */ + .gseqctr =3D { 0x00, 0x00 }, /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */ .sdeqctr =3D { 0x01, 0x05, 0x05, 0x05 }, /* SDVPCTR: Normal operation off color during v porch */ --=20 2.43.0