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([2a01:4262:1ab:c:5af0:999b:bb78:7614]) by smtp.gmail.com with ESMTPSA id eu18-20020a170907299200b00a26e53be089sm9549873ejc.44.2024.01.03.05.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:55 -0800 (PST) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Drew Fustini Subject: [PATCH v2 3/8] riscv: dts: thead: Add TH1520 pin control nodes Date: Wed, 3 Jan 2024 14:28:40 +0100 Message-ID: <20240103132852.298964-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132852.298964-1-emil.renner.berthing@canonical.com> References: <20240103132852.298964-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC. Signed-off-by: Emil Renner Berthing --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 4 ++++ .../dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 70e8042c8304..6c56318a8705 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,6 +44,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &apb_clk { clock-frequency =3D <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..9865925be372 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,6 +25,10 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 +&aonsys_clk { + clock-frequency =3D <73728000>; +}; + &apb_clk { clock-frequency =3D <62500000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ba4d2c673ac8..e65a306ff575 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,12 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 + aonsys_clk: aonsys-clk { + compatible =3D "fixed-clock"; + clock-output-names =3D "aonsys_clk"; + #clock-cells =3D <0>; + }; + apb_clk: apb-clk-clock { compatible =3D "fixed-clock"; clock-output-names =3D "apb_clk"; @@ -242,6 +248,12 @@ portd: gpio-controller@0 { }; }; =20 + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible =3D "thead,th1520-group2-pinctrl"; + reg =3D <0xff 0xe7f3c000 0x0 0x1000>; + clocks =3D <&apb_clk>; + }; + gpio0: gpio@ffec005000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xec005000 0x0 0x1000>; @@ -278,6 +290,12 @@ portb: gpio-controller@0 { }; }; =20 + padctrl0_apsys: pinctrl@ffec007000 { + compatible =3D "thead,th1520-group3-pinctrl"; + reg =3D <0xff 0xec007000 0x0 0x1000>; + clocks =3D <&apb_clk>; + }; + uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; @@ -414,6 +432,12 @@ porte: gpio-controller@0 { }; }; =20 + padctrl_aosys: pinctrl@fffff4a000 { + compatible =3D "thead,th1520-group1-pinctrl"; + reg =3D <0xff 0xfff4a000 0x0 0x2000>; + clocks =3D <&aonsys_clk>; + }; + ao_gpio1: gpio@fffff52000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xfff52000 0x0 0x1000>; --=20 2.43.0