From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59FBF1643A for ; Tue, 2 Jan 2024 21:08:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Joo2LHIv" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7baa8da5692so421987239f.0 for ; Tue, 02 Jan 2024 13:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229724; x=1704834524; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AULYiml6H3I+b2G8tlhMxcx/1ZvVdi4KizI4u111pxQ=; b=Joo2LHIvGCuK3aFERRxNSEtajHNauRc0yJaLHBjfMAMzRY8w7hVez0nRhsg3zc2dlN 5Up3Ht5heS20vtfDdGVUfDzWfCgfhs8QzZkJe6f9GOz2RddQH99u8O+exxZW46folbED T4xTPIQDzWuehQ0jdIS/SkAHnIMxQeG/QB46Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229724; x=1704834524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AULYiml6H3I+b2G8tlhMxcx/1ZvVdi4KizI4u111pxQ=; b=hPV0JlNixzp9tr7jsaCqkErLnKWM2GBwIs4JbgdaT/4RFsIU+y6S2vYTC4qssRr78W Y+eVM6QQIGjYwdssLn04Ad+Onejxd3zGwc6HQehBRmvcQ1OJp/JLI5WhRqk/xshoinPW ErJ8jBMTp2Y3eJtDORIvH/WOYG8333FnBkCIYy7HgvZ/VHn7KRPBWTwFeS8nhfS2Wgxr k4SqxW4EKcfWOYNHpOIyvccuQ7h5j6ru5b5Ntw3IgHB0i2QcLsWLmNn6SiFV2nzi33Fp 2eWgTGnHKw+xNqcKhIqFkvlJ58zcPgGGvjtvSNKJhKsNFI+80iWPadHZVLd+/R7lJ7if N5dA== X-Gm-Message-State: AOJu0YzcB+yrMpt6hkZsX9ikkRzTG/BkixGnWUNe5GZH8nlQJbVS9x01 9NWxpaY+rqnVqNIZuqRDavC9W7J1IOszs4CyVQ+SXIOe7weM X-Google-Smtp-Source: AGHT+IGQBwti5F/Jz854DmDNd9H038Pgm18QGidKZCnQxemnfJmFjyL/+xNqP1TRhwZsuOi9BMzzkQ== X-Received: by 2002:a5e:a70b:0:b0:7b7:3d:6452 with SMTP id b11-20020a5ea70b000000b007b7003d6452mr18789276iod.5.1704229724386; Tue, 02 Jan 2024 13:08:44 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:44 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , AKASHI Takahiro , Andrew Morton , Baoquan He , Greg Kroah-Hartman Subject: [PATCH v4 01/24] resource: Add DEFINE_RES_*_NAMED_FLAGS macro Date: Tue, 2 Jan 2024 14:07:25 -0700 Message-ID: <20240102140734.v4.1.I59b56ebd2f303784031c27bbb1529cf6ef71ba16@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In some cases, it would be nice to instantiate a struct resource with custom flags. For example, creating an IRQ resource with a flag that marks the interrupt as wake capable. Add a set of macros to provide custom flag arguments. Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer --- Changes in v4: -Update Andy's email to @linux.intel.com -Add Reviewed-by tag Changes in v3: -New patch include/linux/ioport.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index db7fe25f33700..a44e73ca058a8 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -163,28 +163,38 @@ enum { .desc =3D IORES_DESC_NONE, \ } =20 +#define DEFINE_RES_IO_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_IO) #define DEFINE_RES_IO_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_IO) + DEFINE_RES_IO_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_IO(_start, _size) \ DEFINE_RES_IO_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_MEM_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_MEM) #define DEFINE_RES_MEM_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_MEM) + DEFINE_RES_MEM_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_MEM(_start, _size) \ DEFINE_RES_MEM_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_REG_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_REG) #define DEFINE_RES_REG_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_REG) + DEFINE_RES_REG_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_REG(_start, _size) \ DEFINE_RES_REG_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_IRQ_NAMED_FLAGS(_irq, _name, _flags) \ + DEFINE_RES_NAMED((_irq), 1, (_name), (_flags) | IORESOURCE_IRQ) #define DEFINE_RES_IRQ_NAMED(_irq, _name) \ - DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ) + DEFINE_RES_IRQ_NAMED_FLAGS((_irq), (_name), 0) #define DEFINE_RES_IRQ(_irq) \ DEFINE_RES_IRQ_NAMED((_irq), NULL) =20 +#define DEFINE_RES_DMA_NAMED_FLAGS(_dma, _name, _flags) \ + DEFINE_RES_NAMED((_dma), 1, (_name), (_flags) | IORESOURCE_DMA) #define DEFINE_RES_DMA_NAMED(_dma, _name) \ - DEFINE_RES_NAMED((_dma), 1, (_name), IORESOURCE_DMA) + DEFINE_RES_DMA_NAMED_FLAGS((_dma), (_name), 0) #define DEFINE_RES_DMA(_dma) \ DEFINE_RES_DMA_NAMED((_dma), NULL) =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B7B6168A9 for ; Tue, 2 Jan 2024 21:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Pq2/3heP" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7ba737ee9b5so735121539f.0 for ; Tue, 02 Jan 2024 13:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229725; x=1704834525; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wDUs5YQEZsX9VnndGDbbu1yg628Gh+zaw5NO27kLhoY=; b=Pq2/3heP8p60zYEI/ughl50VZ2wrYs3fb63RiSNzKebkEBpr8uMQojlnVPuvRUgD3O ORV26BAfKYkHUHTPQRr1NoqTVKBpDarNE67YUGJfSqohVcH1gb32Pud25o4goHprmGSR zlhC+k6oZ4BbC2UXZNOQhwRVSgqlBn3wU1Cr0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229725; x=1704834525; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wDUs5YQEZsX9VnndGDbbu1yg628Gh+zaw5NO27kLhoY=; b=S0eVzTJngRJ2hCCDeDZ3N7CW0hLs0/NujD56Q6iKxqs0acDivu4KnnMQyA8vP24l+v wloQ1QVO/cAJtkmY3qNwkO3dtdWLEfZP6iklVaP2UY9gnNNErhlkR8pmmC25HJjy6mBX sh9Nm/lVWXYZ3RBVv5Ql9S0TC+BvqvOAW42lDSfMOeX2VIvSTrlRXq/N9KeO4OFscqZw 0Kk2F1xkl3OlvyP9TGUhXiBPb+0GZrURZ25iwXxnjuUqu67Wv8hSyAWgdTV3buznO4rk j9A3AhIr1c35LTbInCGCPOmXLjeNYc0JiNZiMXQP71KjJRUPgFbauSvy9lXlh9VOcWLJ 5ARg== X-Gm-Message-State: AOJu0YxAruv1AAgvH8Bv2fdyP5IUyBBk17whHMiMUxHScOF17Yeox9s1 qjQ7SlbVvvqbT+KmWTHvAXGxBsJ5hQnxRf2Rut/+2onwblVn X-Google-Smtp-Source: AGHT+IGYIUO0A61FkChjUrlpzBke+K1PVXOJlWlrCX2qs2jyDxueR5mmbRYujQnh6Emex6rkxeuhRw== X-Received: by 2002:a6b:7e0d:0:b0:7bb:d0a3:47b4 with SMTP id i13-20020a6b7e0d000000b007bbd0a347b4mr192538iom.19.1704229725292; Tue, 02 Jan 2024 13:08:45 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:45 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , Bartosz Golaszewski , Len Brown , Linus Walleij , Mika Westerberg , "Rafael J. Wysocki" , Wolfram Sang , linux-acpi@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH v4 02/24] gpiolib: acpi: Modify acpi_dev_irq_wake_get_by() to use resource Date: Tue, 2 Jan 2024 14:07:26 -0700 Message-ID: <20240102140734.v4.2.Ifd0903f1c351e84376d71dbdadbd43931197f5ea@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Other information besides wake capability can be provided about GPIO IRQs such as triggering, polarity, and sharability. Use resource flags to provide this information to the caller if they want it. This should keep the API more robust over time as flags are added, modified, or removed. It also more closely matches acpi_irq_get() which take a resource as an argument. Rename the function to acpi_dev_get_gpio_irq_resource() to better describe the function's new behavior. Signed-off-by: Mark Hasemeyer --- Changes in v4: -DEFINES_RES_NAMED->DEFINE_RES_IRQ_NAMED_FLAGS -Indent fix -Initialize struct resource on stack -Remove ioport.h dependency in acpi.h Changes in v3: -Use DEFINE_RES_NAMED macro -Add acpi_gpio_info.shareable doc Changes in v2: -Remove explicit cast to struct resource -irq -> IRQ drivers/gpio/gpiolib-acpi.c | 28 +++++++++++++++++++--------- drivers/i2c/i2c-core-acpi.c | 10 ++++++++-- include/linux/acpi.h | 25 +++++++++++-------------- 3 files changed, 38 insertions(+), 25 deletions(-) diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index 88066826d8e5b..d14426c831187 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -99,6 +100,7 @@ struct acpi_gpio_chip { * @pin_config: pin bias as provided by ACPI * @polarity: interrupt polarity as provided by ACPI * @triggering: triggering type as provided by ACPI + * @shareable: share type as provided by ACPI (shared vs exclusive). * @wake_capable: wake capability as provided by ACPI * @debounce: debounce timeout as provided by ACPI * @quirks: Linux specific quirks as provided by struct acpi_gpio_mapping @@ -111,6 +113,7 @@ struct acpi_gpio_info { int polarity; int triggering; bool wake_capable; + bool shareable; unsigned int debounce; unsigned int quirks; }; @@ -760,6 +763,7 @@ static int acpi_populate_gpio_lookup(struct acpi_resour= ce *ares, void *data) lookup->info.debounce =3D agpio->debounce_timeout; lookup->info.gpioint =3D gpioint; lookup->info.wake_capable =3D acpi_gpio_irq_is_wake(&lookup->info.adev->= dev, agpio); + lookup->info.shareable =3D agpio->shareable =3D=3D ACPI_SHARED; =20 /* * Polarity and triggering are only specified for GpioInt @@ -1004,11 +1008,11 @@ struct gpio_desc *acpi_find_gpio(struct fwnode_hand= le *fwnode, } =20 /** - * acpi_dev_gpio_irq_wake_get_by() - Find GpioInt and translate it to Linu= x IRQ number + * acpi_dev_get_gpio_irq_resource() - Find GpioInt and populate resource s= truct * @adev: pointer to a ACPI device to get IRQ from * @name: optional name of GpioInt resource * @index: index of GpioInt resource (starting from %0) - * @wake_capable: Set to true if the IRQ is wake capable + * @r: pointer to resource to populate with IRQ information. * * If the device has one or more GpioInt resources, this function can be * used to translate from the GPIO offset in the resource to the Linux IRQ @@ -1023,10 +1027,12 @@ struct gpio_desc *acpi_find_gpio(struct fwnode_hand= le *fwnode, * The GPIO is considered wake capable if the GpioInt resource specifies * SharedAndWake or ExclusiveAndWake. * - * Return: Linux IRQ number (> %0) on success, negative errno on failure. + * IRQ number will be available in the resource structure. + * + * Return: 0 on success, negative errno on failure. */ -int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, const char *na= me, int index, - bool *wake_capable) +int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev, const char *n= ame, int index, + struct resource *r) { int idx, i; unsigned int irq_flags; @@ -1045,6 +1051,7 @@ int acpi_dev_gpio_irq_wake_get_by(struct acpi_device = *adev, const char *name, in if (info.gpioint && idx++ =3D=3D index) { unsigned long lflags =3D GPIO_LOOKUP_FLAGS_DEFAULT; enum gpiod_flags dflags =3D GPIOD_ASIS; + unsigned long res_flags; char label[32]; int irq; =20 @@ -1084,16 +1091,19 @@ int acpi_dev_gpio_irq_wake_get_by(struct acpi_devic= e *adev, const char *name, in } =20 /* avoid suspend issues with GPIOs when systems are using S3 */ - if (wake_capable && acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) - *wake_capable =3D info.wake_capable; + if (info.wake_capable && !(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0= )) + info.wake_capable =3D false; =20 - return irq; + res_flags =3D acpi_dev_irq_flags(info.triggering, info.polarity, + info.shareable, info.wake_capable); + *r =3D DEFINE_RES_IRQ_NAMED_FLAGS(irq, NULL, res_flags); + return 0; } =20 } return -ENOENT; } -EXPORT_SYMBOL_GPL(acpi_dev_gpio_irq_wake_get_by); +EXPORT_SYMBOL_GPL(acpi_dev_get_gpio_irq_resource); =20 static acpi_status acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address, diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c index d6037a3286690..8126a87baf3d4 100644 --- a/drivers/i2c/i2c-core-acpi.c +++ b/drivers/i2c/i2c-core-acpi.c @@ -203,6 +203,7 @@ int i2c_acpi_get_irq(struct i2c_client *client, bool *w= ake_capable) { struct acpi_device *adev =3D ACPI_COMPANION(&client->dev); struct list_head resource_list; + struct resource irqres; struct i2c_acpi_irq_context irq_ctx =3D { .irq =3D -ENOENT, }; @@ -217,8 +218,13 @@ int i2c_acpi_get_irq(struct i2c_client *client, bool *= wake_capable) =20 acpi_dev_free_resource_list(&resource_list); =20 - if (irq_ctx.irq =3D=3D -ENOENT) - irq_ctx.irq =3D acpi_dev_gpio_irq_wake_get(adev, 0, &irq_ctx.wake_capabl= e); + if (irq_ctx.irq =3D=3D -ENOENT) { + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); + if (ret) + return ret; + irq_ctx.irq =3D irqres.start; + irq_ctx.wake_capable =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; + } =20 if (irq_ctx.irq < 0) return irq_ctx.irq; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index b7165e52b3c68..a0cd733febe34 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -9,7 +9,6 @@ #define _LINUX_ACPI_H =20 #include -#include /* for struct resource */ #include #include #include @@ -17,6 +16,7 @@ #include #include =20 +struct resource; struct irq_domain; struct irq_domain_ops; =20 @@ -1232,8 +1232,8 @@ bool acpi_gpio_get_irq_resource(struct acpi_resource = *ares, struct acpi_resource_gpio **agpio); bool acpi_gpio_get_io_resource(struct acpi_resource *ares, struct acpi_resource_gpio **agpio); -int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, const char *na= me, int index, - bool *wake_capable); +int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev, const char *n= ame, int index, + struct resource *r); #else static inline bool acpi_gpio_get_irq_resource(struct acpi_resource *ares, struct acpi_resource_gpio **agpio) @@ -1245,28 +1245,25 @@ static inline bool acpi_gpio_get_io_resource(struct= acpi_resource *ares, { return false; } -static inline int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, = const char *name, - int index, bool *wake_capable) +static inline int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev,= const char *name, + int index, struct resource *r) { return -ENXIO; } #endif =20 -static inline int acpi_dev_gpio_irq_wake_get(struct acpi_device *adev, int= index, - bool *wake_capable) +static inline int acpi_dev_gpio_irq_get_by(struct acpi_device *adev, const= char *name, int index) { - return acpi_dev_gpio_irq_wake_get_by(adev, NULL, index, wake_capable); -} + struct resource r =3D {}; + int ret; =20 -static inline int acpi_dev_gpio_irq_get_by(struct acpi_device *adev, const= char *name, - int index) -{ - return acpi_dev_gpio_irq_wake_get_by(adev, name, index, NULL); + ret =3D acpi_dev_get_gpio_irq_resource(adev, name, index, &r); + return ret ?: r.start; } =20 static inline int acpi_dev_gpio_irq_get(struct acpi_device *adev, int inde= x) { - return acpi_dev_gpio_irq_wake_get_by(adev, NULL, index, NULL); + return acpi_dev_gpio_irq_get_by(adev, NULL, index); } =20 /* Device properties */ --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01EB2168BD for ; Tue, 2 Jan 2024 21:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="YKh0zhED" Received: by mail-io1-f48.google.com with SMTP id ca18e2360f4ac-7ba8f139522so493850539f.1 for ; Tue, 02 Jan 2024 13:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229726; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:45 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , Mika Westerberg , Wolfram Sang , linux-acpi@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH v4 03/24] i2c: acpi: Modify i2c_acpi_get_irq() to use resource Date: Tue, 2 Jan 2024 14:07:27 -0700 Message-ID: <20240102140734.v4.3.Ib65096357993ff602e7dd0000dd59a36571c48d8@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The i2c_acpi_irq_context structure provides redundant information that can be provided with struct resource. Refactor i2c_acpi_get_irq() to use struct resource instead of struct i2c_acpi_irq_context. Suggested-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer --- Changes in v4: -Use Andy's @linux.intel.com email -Remove blank line in commit message -More error handling refactoring in i2c_acpi_get_irq() -Remove struct i2c_acpi_irq_context as it's unused Changes in v3: -Add Suggested-by -Check resource flags for valid irq -Drop error pointer check -Invert error checking logic in i2c_acpi_get_irq() -Drop redundant 0 in struct resource init -Drop unnecessary check for irq > 0 when setting I2C_CLIENT_WAKE Changes in v2: -New patch drivers/i2c/i2c-core-acpi.c | 49 +++++++++++++------------------------ drivers/i2c/i2c-core-base.c | 6 ++--- drivers/i2c/i2c-core.h | 4 +-- 3 files changed, 22 insertions(+), 37 deletions(-) diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c index 8126a87baf3d4..4c3df540c2f4b 100644 --- a/drivers/i2c/i2c-core-acpi.c +++ b/drivers/i2c/i2c-core-acpi.c @@ -137,11 +137,6 @@ static const struct acpi_device_id i2c_acpi_ignored_de= vice_ids[] =3D { {} }; =20 -struct i2c_acpi_irq_context { - int irq; - bool wake_capable; -}; - static int i2c_acpi_do_lookup(struct acpi_device *adev, struct i2c_acpi_lookup *lookup) { @@ -175,64 +170,54 @@ static int i2c_acpi_do_lookup(struct acpi_device *ade= v, =20 static int i2c_acpi_add_irq_resource(struct acpi_resource *ares, void *dat= a) { - struct i2c_acpi_irq_context *irq_ctx =3D data; - struct resource r; + struct resource *r =3D data; =20 - if (irq_ctx->irq > 0) + if (r->flags) return 1; =20 - if (!acpi_dev_resource_interrupt(ares, 0, &r)) + if (!acpi_dev_resource_interrupt(ares, 0, r)) return 1; =20 - irq_ctx->irq =3D i2c_dev_irq_from_resources(&r, 1); - irq_ctx->wake_capable =3D r.flags & IORESOURCE_IRQ_WAKECAPABLE; + i2c_dev_irq_from_resources(r, 1); =20 return 1; /* No need to add resource to the list */ } =20 /** - * i2c_acpi_get_irq - get device IRQ number from ACPI + * i2c_acpi_get_irq - get device IRQ number from ACPI and populate resource * @client: Pointer to the I2C client device - * @wake_capable: Set to true if the IRQ is wake capable + * @r: resource with populated IRQ information * * Find the IRQ number used by a specific client device. * * Return: The IRQ number or an error code. */ -int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_capable) +int i2c_acpi_get_irq(struct i2c_client *client, struct resource *r) { struct acpi_device *adev =3D ACPI_COMPANION(&client->dev); struct list_head resource_list; - struct resource irqres; - struct i2c_acpi_irq_context irq_ctx =3D { - .irq =3D -ENOENT, - }; int ret; =20 + if (!r) + return -EINVAL; + INIT_LIST_HEAD(&resource_list); =20 ret =3D acpi_dev_get_resources(adev, &resource_list, - i2c_acpi_add_irq_resource, &irq_ctx); + i2c_acpi_add_irq_resource, r); if (ret < 0) return ret; =20 acpi_dev_free_resource_list(&resource_list); =20 - if (irq_ctx.irq =3D=3D -ENOENT) { - ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); - if (ret) - return ret; - irq_ctx.irq =3D irqres.start; - irq_ctx.wake_capable =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; - } + if (r->flags) + return r->start; =20 - if (irq_ctx.irq < 0) - return irq_ctx.irq; + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, r); + if (ret) + return ret; =20 - if (wake_capable) - *wake_capable =3D irq_ctx.wake_capable; - - return irq_ctx.irq; + return r->start; } =20 static int i2c_acpi_get_info(struct acpi_device *adev, diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index 3bd48d4b6318f..0339c298ba50b 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -513,10 +513,10 @@ static int i2c_device_probe(struct device *dev) if (irq =3D=3D -EINVAL || irq =3D=3D -ENODATA) irq =3D of_irq_get(dev->of_node, 0); } else if (ACPI_COMPANION(dev)) { - bool wake_capable; + struct resource r =3D {}; =20 - irq =3D i2c_acpi_get_irq(client, &wake_capable); - if (irq > 0 && wake_capable) + irq =3D i2c_acpi_get_irq(client, &r); + if (r.flags & IORESOURCE_IRQ_WAKECAPABLE) client->flags |=3D I2C_CLIENT_WAKE; } if (irq =3D=3D -EPROBE_DEFER) { diff --git a/drivers/i2c/i2c-core.h b/drivers/i2c/i2c-core.h index 05b8b8dfa9bdd..b5dc559c49d11 100644 --- a/drivers/i2c/i2c-core.h +++ b/drivers/i2c/i2c-core.h @@ -61,11 +61,11 @@ static inline int __i2c_check_suspended(struct i2c_adap= ter *adap) #ifdef CONFIG_ACPI void i2c_acpi_register_devices(struct i2c_adapter *adap); =20 -int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_capable); +int i2c_acpi_get_irq(struct i2c_client *client, struct resource *r); #else /* CONFIG_ACPI */ static inline void i2c_acpi_register_devices(struct i2c_adapter *adap) { } =20 -static inline int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_c= apable) +static inline int i2c_acpi_get_irq(struct i2c_client *client, struct resou= rce *r) { return 0; } --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD699168CE for ; Tue, 2 Jan 2024 21:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="mxlR/JRm" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7ba8c218fe1so522823739f.3 for ; Tue, 02 Jan 2024 13:08:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229727; x=1704834527; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:46 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v4 04/24] dt-bindings: power: Clarify wording for wakeup-source property Date: Tue, 2 Jan 2024 14:07:28 -0700 Message-ID: <20240102140734.v4.4.I1016a45ac9e8daf8a9ebc9854ab90ec3542e7c30@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The wording in the current documentation is a little strong. The intention was not to fix any particular interrupt as wakeup capable but leave those details to the device. It wasn't intended to enforce any rules as what can be or can't be a wakeup interrupt. Soften the wording to not mandate that the 'wakeup-source' property be used, and clarify what it means when an interrupt is marked (or not marked) for wakeup. Link: https://lore.kernel.org/all/ZYAjxxHcCOgDVMTQ@bogus/ Link: https://lore.kernel.org/all/CAL_Jsq+MYwOG40X26cYmO9EkZ9xqWrXDi03MaRfx= nV-+VGkXWQ@mail.gmail.com/ Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit title prefixes Changes in v2: -New patch .../bindings/power/wakeup-source.txt | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/power/wakeup-source.txt b/Do= cumentation/devicetree/bindings/power/wakeup-source.txt index 697333a56d5e2..75bc20b95688f 100644 --- a/Documentation/devicetree/bindings/power/wakeup-source.txt +++ b/Documentation/devicetree/bindings/power/wakeup-source.txt @@ -3,16 +3,20 @@ Specifying wakeup capability for devices =20 Any device nodes ---------------- -Nodes that describe devices which has wakeup capability must contain an +Nodes that describe devices which have wakeup capability may contain a "wakeup-source" boolean property. =20 -Also, if device is marked as a wakeup source, then all the primary -interrupt(s) can be used as wakeup interrupt(s). +If the device is marked as a wakeup-source, interrupt wake capability depe= nds +on the device specific "interrupt-names" property. If no interrupts are la= beled +as wake capable, then it is up to the device to determine which interrupts= can +wake the system. =20 -However if the devices have dedicated interrupt as the wakeup source -then they need to specify/identify the same using device specific -interrupt name. In such cases only that interrupt can be used as wakeup -interrupt. +However if a device has a dedicated interrupt as the wakeup source, then it +needs to specify/identify it using a device specific interrupt name. In su= ch +cases only that interrupt can be used as a wakeup interrupt. + +While various legacy interrupt names exist, new devices should use "wakeup= " as +the canonical interrupt name. =20 List of legacy properties and respective binding document --------------------------------------------------------- --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-il1-f171.google.com (mail-il1-f171.google.com [209.85.166.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0AE7171BA for ; Tue, 2 Jan 2024 21:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="TzvupCHx" Received: by mail-il1-f171.google.com with SMTP id e9e14a558f8ab-35fe47edd2eso20695415ab.0 for ; Tue, 02 Jan 2024 13:08:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229728; x=1704834528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZjO95JnMkaDwwshxg++NkSMHj1Inq11nKJ2Uva51g+s=; b=TzvupCHxAkkrsakCQUzqs0yVAGMgiH7X+OVX1f6xgCQZhuzy8vI+jmgglIB58+S9A8 KKgaCT7i8KW2AG098C8PjBrgHatDj9qcDiI1C38wY/xg2Wc+6TKcqQT0FrkM6Obe5veF Is2QuhFPtC644eyxFHEh5OClumx/XWyBD638k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229728; x=1704834528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZjO95JnMkaDwwshxg++NkSMHj1Inq11nKJ2Uva51g+s=; b=iIS1BmbUOy4Idy6bQPBIQZgl9VlZH4rheqKma8oBC8L9SxeEYy6PbhEsRtlWZ+xvAl VZcEfpW31z/+tUXkDZxOFTArTfyH+zUttilYzwM+rUx1mLOPid9L+RXSRjzSAbiEMog/ 23oPpNMbZvOwCnbwYnMsA+YRyZDr+cYxKetrHfNWzo/Y5NXdYbxfyitLpIikjLRNJCDI AAk+KCJAh85ATviUZCB62XoLhdUfJXXnd4K8Ij3bVVxMmWmXH+j1VkO++ti70Y0Bg6F5 +i9WOWpC17zmFiIukZ15Udyt5OB3MXI91GQ7/zkHpYCwOvmURkKDyVHFC70ceFtBZPXZ 4eHQ== X-Gm-Message-State: AOJu0Yzu63+46MEVkTAm1wf15HMDCKze3lOuLtyjCOM+qv2S0FrCAUm8 qtWyDjx+1A0ujUtS6uAC9wt7HkGipezI+n6kne5aJ/0pmGfh X-Google-Smtp-Source: AGHT+IHfNiRymIq/Ou3HrROS4WwsUL4yhL5gA1ghZKZZRYnQQE6kSgie8hkLsVKsxguzK0X1QgYH8w== X-Received: by 2002:a05:6e02:20ea:b0:360:142:3fec with SMTP id q10-20020a056e0220ea00b0036001423fecmr44297ilv.6.1704229727943; Tue, 02 Jan 2024 13:08:47 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:47 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alexandre TORGUE , Andre Przywara , Conor Dooley , Jonathan Hunter , Krzysztof Kozlowski , Nick Hawkins , Paul Barker , Rob Herring , Romain Perier , Thierry Reding , Wei Xu , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 05/24] ARM: dts: tegra: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:29 -0700 Message-ID: <20240102140734.v4.5.Ia598792a1386cca61844068be03c3ccec9e81753@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/nvidia/tegra124-venice2.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dt= s/nvidia/tegra124-nyan.dtsi index a2ee371802004..8125c1b3e8d79 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ cros_ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/= dts/nvidia/tegra124-venice2.dts index 3924ee385dee0..df98dc2a67b85 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ cros_ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E12317726 for ; Tue, 2 Jan 2024 21:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="fXTEKLe7" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7baa8da5692so421989739f.0 for ; Tue, 02 Jan 2024 13:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229728; x=1704834528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y5uC/dqzQmYcBPDfBK6LehJHA1Nu9NUaC8OommBsuso=; b=fXTEKLe7q71mJsF+Dq10I3kngM4DFvGhqoxx//hTAim9J3VvhgQd4W/CiK4EUo7+Af uK8PO27JvkAxve0otUSqSKXT1YNZKQzNw8P788roY0qn05/S1OcWuW6AAHJPIVeiIUHb N4T8zQhbcNYrU/mfKq2Kf4JTp1/S8JwdyzYLs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229728; x=1704834528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y5uC/dqzQmYcBPDfBK6LehJHA1Nu9NUaC8OommBsuso=; b=kDhqxO2D6CfAc+/5cT+8kZTFb/5qc/eKZNy7Ns35l8uOEtzVmeenmNh+mEFT+8bAGc Qwj+bMv4MJhu19sd9Cfepnv4H0g48wE7MCOvuT9z1PAkTUek9zf97F/1oVo0rI197P5f HqSAqq4P1KaTMNrstzMnapLikurlENFphCEy5QXuY8bC2ZcJF9Iqy+tOIw+Ws7pSx9bG U6hugddZ+VReMGuWcx+6UFiHhbrHNeiaQNv71uET6pdV3bkPR4s/R8a8JEB+Ce+bLaze cPZkjK/2ub9RfmGtWqIEXlDOmGda5BBDnJw7pL5LWj12XD4MsMVcsElu4ub9qcAv0b2f 1SvQ== X-Gm-Message-State: AOJu0Yw6X0Bmh/jtf88798lIAdQARK4bRrcB493cToUjogbnuVIO8i9G TvpwF7z6hlnOBthmx6orhC9YzqVSWIY409bjFw8PIrxpGJLz X-Google-Smtp-Source: AGHT+IHWKoCxJRGKNJPcLHrsAhYdGs8ek7DpUdoZoMbtH5+b3OOlyzYczn2NyfouKVIhZZpmVYFcgQ== X-Received: by 2002:a5d:8d84:0:b0:7bb:40db:9a47 with SMTP id b4-20020a5d8d84000000b007bb40db9a47mr8538555ioj.34.1704229728788; Tue, 02 Jan 2024 13:08:48 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:48 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 06/24] ARM: dts: rockchip: rk3288: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:30 -0700 Message-ID: <20240102140734.v4.6.I8249df4df0b7d12fb68ea1e69f84ca589c574bb1@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arc= h/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 092316be67f74..1554fe36e60fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -112,6 +112,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_int>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 836991774F for ; Tue, 2 Jan 2024 21:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="grYAbEpE" Received: by mail-io1-f45.google.com with SMTP id ca18e2360f4ac-7b7f9fdc14dso535431039f.0 for ; Tue, 02 Jan 2024 13:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229729; x=1704834529; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kFylEVwz6/jxQq1ZweDsmHVwptzQPuyXfUnhxAJ710k=; b=grYAbEpEGE+CY/lcVPOfo1nBGvsxD8gVu/PNJDxGLdxkl9JO2ttuV88LTUkBL6Nvu+ NDF4w4L2ULGkrLijFRY+PJ9FqOQwcOwgH7o1SnrTzXrh2gfX/nI8eyCeHlWwXbJ2WXe1 yzIBQweyAEsgllUrhRDkcgnbHpf4Er2TQLN0g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229729; x=1704834529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kFylEVwz6/jxQq1ZweDsmHVwptzQPuyXfUnhxAJ710k=; b=GjqF5BupH6gBTnDJuTTlOIcdUOAUYGDRiwaEhakST/FX+oPvQTXcwhFFrNhKqzanfU 5PNjWJEIDGmlJfxyxZ3xwUVuhHf0zHqqqQ+M8NTFj8HJq0NVThJa9VSZM/akUIW1nOm0 7WP56ZbWF/RKJRl6gawVPLJTuPOCRLQcFJ6LOzq0/+LTIalGipBmHQDICMPUUU8j5YO0 zKPBGMaJhlHkiJ0i/CQPMCkAqeaCvxtDwKMruUTCjXAe6NyFh3qZ8fTOG0hvlqOZtsDe 6dCBj24KjjksdhRa3ebU+7Q+OCVr4ndqrVd+WAqCxyzBR5nFKxT1n5WWiORrqlwXafxF QRZw== X-Gm-Message-State: AOJu0YwfKOw5Rhp22qdzxBwdFaJQ8VF4RhfIuCezx2f5lQQEU5vOdOYn SQFhVxWdbs5toqnMsUH67LvWmxicJTjiWWYSAoW2EONZrNal X-Google-Smtp-Source: AGHT+IHEJbHth/xM3Ut15mQoMsgLsloOubZy6ZZ76RDsFpY7YTAqNzQUU9yztAFE3PAbKB9V85o07g== X-Received: by 2002:a6b:c342:0:b0:7bb:cc1:a3b3 with SMTP id t63-20020a6bc342000000b007bb0cc1a3b3mr7901421iof.21.1704229729647; Tue, 02 Jan 2024 13:08:49 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:49 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v4 07/24] ARM: dts: samsung: exynos5420: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:31 -0700 Message-ID: <20240102140734.v4.7.I06b059021de1bf6103e60a73211f078f2af75d17@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts b/arch/arm/= boot/dts/samsung/exynos5420-peach-pit.dts index 4e757b6e28e1c..3759742d38cac 100644 --- a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ cros_ec: cros-ec@0 { reg =3D <0>; spi-max-frequency =3D <3125000>; google,has-vbc-nvram; + wakeup-source; =20 controller-data { samsung,spi-feedback-delay =3D <1>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926811799E for ; Tue, 2 Jan 2024 21:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="NxKC8Bg1" Received: by mail-io1-f44.google.com with SMTP id ca18e2360f4ac-7ba7c845e1aso589483239f.2 for ; Tue, 02 Jan 2024 13:08:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229730; x=1704834530; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Iih8S9CbSKYXK6Eu1V5z5fk9f7rCImQ6DnJQzgwRsXQ=; b=NxKC8Bg1E9loB28npLQy86G1Uk0jberzz0pipqr7NQKvJ55wAfFyIo/RUlTOuhxG8u jQOtXZm8zekL6yMFVXzNdqAqdEDBIxF65VbIf9DGIXLYs5Dz0n1Qr4cPnF3jb3NqdZ55 Sb4E+K1G9ILQM6kDWcB0LKl5Ru1vymvI/M29o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229730; x=1704834530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Iih8S9CbSKYXK6Eu1V5z5fk9f7rCImQ6DnJQzgwRsXQ=; b=TQsTheEMRdgQA1yoHkLsDD91tr/ac9ieESB8vEd2zhjINGvzw8CnrOsd/Oshplcw6T 7MbtJuEXLbGTCJbvAVUwFOw033x8MMawZpRRy8JjbYdFQp1T5i5Zw0LaaYnGInPWLiUF JBTjmpHRIlqLj85RZfFzu2Yj7uKl4G3ZptVUfqB9mJ99JoTnP3223L7M7yV6TBGRwFe2 ujS7aHeWeCLY68DXV/X+ladL6RHuQXYmDss5UZGsaaxN6GsDgDtFACsuNhrtv1BiEK12 MTrkFAdfHRxEy/AqOu+mUMrwVCXM+h5dl2zBVo6urzEk6qetXHRHQLxx4DsfDpFN1ojQ DDdA== X-Gm-Message-State: AOJu0YyHjN36aGh0QztxAu+eKtfEGpye17jDLzMJdeMV5I5PyDHXUtzx xwyf1j3nbuKrc5tNCXhcEby4080Ey1UbdNgbnAQhkDQr8M4J X-Google-Smtp-Source: AGHT+IEGMyFoc4xM4Z76PcN9nzKX4GmQlxsOK5XWY9+A3y0Tt67mNC5lPz5MkPwv5iXKSvpSPmJo2g== X-Received: by 2002:a5e:a50b:0:b0:7b7:55fc:7d4 with SMTP id 11-20020a5ea50b000000b007b755fc07d4mr24457360iog.18.1704229730619; Tue, 02 Jan 2024 13:08:50 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:50 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v4 08/24] ARM: dts: samsung: exynos5800: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:32 -0700 Message-ID: <20240102140734.v4.8.Idc995ce08a52ba4c5fde0685118ddf2873fc8acd@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/b= oot/dts/samsung/exynos5800-peach-pi.dts index f91bc4ae008e4..9bbbdce9103a6 100644 --- a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ cros_ec: cros-ec@0 { reg =3D <0>; spi-max-frequency =3D <3125000>; google,has-vbc-nvram; + wakeup-source; =20 controller-data { samsung,spi-feedback-delay =3D <1>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F5F918023 for ; Tue, 2 Jan 2024 21:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PyeXmrBb" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7bb97d5ee3aso99555739f.2 for ; Tue, 02 Jan 2024 13:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229731; x=1704834531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LeATnxPiO37XaEtB4eQZXrEcgW0prfgDBCAc6VotlMc=; b=PyeXmrBbvHD0JEpLy/toV24mUPQXkcKEsrP2CPsbMBEuvug9xWLv23V0nsM8kdoo+w WiNM0e8Bz8Vhbweqg+l3plE1Jsa2Bm2ria9NHeYlnAevYO58QE8mLuVCm0bs77KA8ZOq W+IkdzfVuDsf48UFKrOG1IaC5HM+92ztPIzww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229731; x=1704834531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LeATnxPiO37XaEtB4eQZXrEcgW0prfgDBCAc6VotlMc=; b=mplvHwXNZuKG2lbWlcpskO3OLAatvlJ216qtmpV4w8labGd6akny+pL2lrjsfCz7gE 3rl4EWB+IHOM8/mzaCjZjlit2DD1DmuikDpSyp3N688yrYl53F3TjV13W+ZJLnq/C1gs AUMg1zLqeWeGLKsjog/vx1IDON+qWRuJEMad82yo1Xsr8mi+wK361tkvS1Ecye/izvgW t5ILpJOsgIEjdcLvTyTjzpzIXfm65TIsLKQzj7EHM0n6C6ac3kGKd5peBvapYpA/l3tF 2lzkQdGOnQpoy6lMk/+a0ACTfVJvn0dQ6PSbpxjvQiD4xGM1YNMjZat7TNgxVHMsqmn3 3gkQ== X-Gm-Message-State: AOJu0YznOc5wKeRyZaZbgzxLOVpEqpskrdJqxxprUle/KRmGjvMS2vog 0EytO5erh50nlAkOa3KEqqLAw945euj4FBoJa3JT4MEZD728 X-Google-Smtp-Source: AGHT+IEq/nXkNhcxVKQTcs7pZQy/wi+fDhhMJ7dsO0o+UvKjnInsDMjSKm1DUuQtSSG5kZZEdWWxwA== X-Received: by 2002:a6b:f008:0:b0:7b7:4c36:f295 with SMTP id w8-20020a6bf008000000b007b74c36f295mr20729710ioc.40.1704229731497; Tue, 02 Jan 2024 13:08:51 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:51 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 09/24] arm64: dts: mediatek: mt8173: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:33 -0700 Message-ID: <20240102140734.v4.9.Ic09ebe116c18e83cc1161f4bb073fea8043f03f3@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot= /dts/mediatek/mt8173-elm.dtsi index 8d614ac2c58ed..335aed42dc9e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1155,6 +1155,7 @@ cros_ec: ec@0 { spi-max-frequency =3D <12000000>; interrupts-extended =3D <&pio 0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay =3D <500>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel0 { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 261B718041 for ; Tue, 2 Jan 2024 21:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="OUJsj7U4" Received: by mail-io1-f47.google.com with SMTP id ca18e2360f4ac-7b7fdde8b98so496499039f.1 for ; Tue, 02 Jan 2024 13:08:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229732; x=1704834532; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5bEDuGxV/dPJIqZg1w0wl3qVgLyOuLBrt1YTH4lJcK4=; b=OUJsj7U4B/Wkgmd/AEzsPthDKbgyGX+3iugDar/5gA7ccoYTJ6wxikYoAtPZTOREmK UJ2mnqV+1gAUnr0GnKfLOhhpqJ/7zGJiUupAXFKyjhdkm8b3y1gJCpMPYQiqaPPvfz6H patHhOOm4j4GiWVlxD8AODicg2PmeldUrdKfg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229732; x=1704834532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5bEDuGxV/dPJIqZg1w0wl3qVgLyOuLBrt1YTH4lJcK4=; b=qG56ww6gYtnYpyj0sYOoFsyGK0UPHdp0s1MeMToCl3ASB5m8xRY1t6yH1ifeAfte64 UZmnmEtmRwGJq0VvnKLIX+T4+c0YuXCRA3g3nqcYY41HEs7xKCdFcYqbLzq++k27OkCJ /9HEX8fcGNS+OLS2J00gQ1XEey4rAMXXWZ5clRoOuvHUQ0W5P1tWWTaNYmaSo+mcnDJu GfdWRzA2Fd8z+hIhqhHYeOSkeX7KxRT6XJHFWWFF90qUjFIKj6UR08XbuUn7/yfVXviU 5XVW2gul4diDgi/26VDWnb/Oq/rmLrtsT4FD49jsTDmDx+QTJK1pyyEvR5MczU2AahWt mesA== X-Gm-Message-State: AOJu0Yz1e9i+d4PAgECuTkzCeAuwGA3yfJmYx7yVHvVha+nh0wVJZhsd b8MsRtDM75q6M8nkanPS2ESm6OuTfvYTnFnTa5x3cUwy/nl3 X-Google-Smtp-Source: AGHT+IEepz+cz572l3C4gGDpkRMfzMAxMxz3DhHQT6lcFpZI37i5Utc7APQrtUv4nIj51c+vjo/kRw== X-Received: by 2002:a05:6602:147:b0:7bb:cd42:ed8e with SMTP id v7-20020a056602014700b007bbcd42ed8emr301320iot.28.1704229732361; Tue, 02 Jan 2024 13:08:52 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:52 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 10/24] arm64: dts: mediatek: mt8183: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:34 -0700 Message-ID: <20240102140734.v4.10.Iba4a8b7e908989e57f7838a80013a4062be5e614@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 5506de83f61d4..08261164ab18d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -924,6 +924,7 @@ cros_ec: cros-ec@0 { interrupts-extended =3D <&pio 151 IRQ_TYPE_LEVEL_LOW>; pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_odl>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-il1-f173.google.com (mail-il1-f173.google.com [209.85.166.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16037182A7 for ; Tue, 2 Jan 2024 21:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="KkhdR48g" Received: by mail-il1-f173.google.com with SMTP id e9e14a558f8ab-35fe9a6609eso73631245ab.2 for ; Tue, 02 Jan 2024 13:08:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229733; x=1704834533; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kv/aa+b9yoEdKvBahkqrw433Fqiy1xO+ioSsYaTJvb4=; b=KkhdR48gDfOnK0JzFjr9dKqzquQEnAWkct5MJKxXTVUYMsVdlUwo5iSD+vN7NzaVQa jetjvii6Fno+XkzfzFS/H1THp689jd0nzmp9/pCLWh616Sa0EGBDt+JmupEyUi/76F/2 Re4a0iKMXdCcCSwVDy1s5HI2HojH4odrxmZGs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229733; x=1704834533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kv/aa+b9yoEdKvBahkqrw433Fqiy1xO+ioSsYaTJvb4=; b=QhLoPEaXPldUuxyJGLLzWlJ+HR42T0g4v/4Mi7jRBsBR/1NGTITUPMhuimaeXJVxRf ZxrUoF8VkcEd/BGEK2kACmCAkqGgjWg74KhUIMv6kUacDsp4TsFMqv02Kzxdp74EU2Me oGJeh8JRP1hLzC2BXveKwveIH1iQffHzGuPLanGbKu2HokWylAs8vnlRD4ogvLeTqbRR q74HwTMVe7hCD4Nhsgm5cQm89PN7gm1Kq4PWtWnjKbZaXKtiSnK01LNJkAdSVAXBKQUu s6hFqBt8jGFfiIpc7uxHzreBWE/ZMhnT8iHrRIFULN48r+f0juqyRDohemsv1y271Zd7 xGdw== X-Gm-Message-State: AOJu0YwcphmTuviG0GuQoCArfTXCdlpW7AqjMknqu2g1EBNcA/YeQZM2 Bp+bIM/iDaWzKj0vbL61Cy7QONSBlnmjWmGRJwwlFFwoDQLr X-Google-Smtp-Source: AGHT+IHHN3TbtDEmyfVNFzxMQSipzvaGMekbOIDXc3JT0zP9D5s4Ute8SBzjxYwpVjI4JooHeisxkw== X-Received: by 2002:a05:6e02:1a88:b0:35f:a4b2:7018 with SMTP id k8-20020a056e021a8800b0035fa4b27018mr27509779ilv.29.1704229733266; Tue, 02 Jan 2024 13:08:53 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:53 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 11/24] arm64: dts: mediatek: mt8192: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:35 -0700 Message-ID: <20240102140734.v4.11.Ibd330d26a00f5e219a7e448452769124833a9762@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index f2281250ac35d..ab44d382f757e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1332,6 +1332,7 @@ cros_ec: ec@0 { spi-max-frequency =3D <3000000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cros_ec_int>; + wakeup-source; =20 #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5441818632 for ; Tue, 2 Jan 2024 21:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="JXIgDXon" Received: by mail-io1-f47.google.com with SMTP id ca18e2360f4ac-7bb5fda069bso168111439f.0 for ; Tue, 02 Jan 2024 13:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229734; x=1704834534; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n3q5bAzQikGEaFLCjfRt4Z8nKD+aA0c3SnrfHNcWXEY=; b=JXIgDXonyYNTm//xOUZbqvGEUrcO/uNkN4iZlt5SKgdAoy2vIhCqJ8k3ilv1Qyju9n sqEoOwLdDWLnZ5BHEI3SEUOUyYRBKWtMGCPbadhqosOiYy2D0oupIDf7vv0ygYDSO2F6 Z92VWWV+mmFZk/gLa7p6FtRIY8D2fo6aJ2Mm8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229734; x=1704834534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n3q5bAzQikGEaFLCjfRt4Z8nKD+aA0c3SnrfHNcWXEY=; b=AwCIba5QWgWYIF8Tga2Krr4zgfP7rJbM3Cx/IkvYT5kobZO1lmnin1WXWVlx1FvhiA e8T7zHK04Zs5D1mUDynQv4+MY6n/L6G5iafNH/JgKSolrtCCyYWnP+UpxvdDTeRnVslH bvLFIgMQbUphlhFGocgnnu93hnsX4sBBsxCWy3SaMiYV0YDOtD74qvgdXC7Tp8PkI3wV 37kbSFeW9R6h8hbSB/GaXd/ECsmnoaOJaEzuVPbmDfH4zC694BRRtP2GQOeaZrYPwGah mGPL7YY5BZyZrcikUgS7Mw8a/wfN/fSlKvdyET8l1Tpv4Ao4JGK+FSqUYbPuCN74Mudj pClA== X-Gm-Message-State: AOJu0YxtMrdJVMFjdPDUzHDs0GSRJny2jOZrpT+xmM8kLTNYlk9t5Vfe Fn7E9jDC8AI+i5p2PVoPHMtccWorIsbaC4kwUdRUZer8oHkK X-Google-Smtp-Source: AGHT+IFyaB/cl9XINtwxzc8FyOfrkFwShCGVt+Q6OLCTlAP9Elw0gWl88LBFhGGJGmWTzbBD05MnBA== X-Received: by 2002:a6b:5905:0:b0:7bb:bca0:7670 with SMTP id n5-20020a6b5905000000b007bbbca07670mr1472284iob.23.1704229734077; Tue, 02 Jan 2024 13:08:54 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:53 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 12/24] arm64: dts: mediatek: mt8195: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:36 -0700 Message-ID: <20240102140734.v4.12.Iee33a7f1f991408cef372744199026f936bf54e2@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index bbdcd441c049d..2edb270d0bc2f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1149,6 +1149,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&cros_ec_int>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 keyboard-backlight { compatible =3D "google,cros-kbd-led-backlight"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-il1-f173.google.com (mail-il1-f173.google.com [209.85.166.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E26A118651 for ; Tue, 2 Jan 2024 21:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="J/iviGxT" Received: by mail-il1-f173.google.com with SMTP id e9e14a558f8ab-3600dc78bc0so29926405ab.2 for ; Tue, 02 Jan 2024 13:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229735; x=1704834535; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6xWplU6V/74zhrE0fU+phMJuFQc01H2ditVc3hsW/nY=; b=J/iviGxTnseTosGYD18/rbF8CRnnRPLnuoyhM+uMxt2rHo8zsjpoIu858je2rx9fSw nNFtxc1LOzjg1Bb5JrY3peV4KD6mCmd/qEqnogrUal+3AjklC1X68C2uWM0UK6ZPDF1m MCEH3hKAIXs4HL84mb8+Hlm2oT8Lv2Jt3Vbtk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229735; x=1704834535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6xWplU6V/74zhrE0fU+phMJuFQc01H2ditVc3hsW/nY=; b=RMOfL8q8TmjRvnzKJqTJksislE48NExfeTLEYqZuduZYRAsD5Ib3vwG5uS2Ox3tJKM A5PQ4R5rQMvfIgEgmtqL/PiWPxVqLoNLS4BNQOhLSQ8ITa7x8v3p67QBFjBf4QxfhpaM dGuZ26AqKb+zH469zwHpLObj5zyz/bNmpjc5vyQV5g+aPI5KQHshrOVPign2YXVmDN3R JrQ4/NsyR1wU9LRFjYFWYVKL/a/ddjxBWqX7oHjHoA/lA69VtIlNc9gWfogGeEgqmCBJ UpjS2TaMxQf/9k8b0AjHxjA/6EhWowLphLMOKlnHJMC0kTIP4N3rFsx0/dNRWiLK5iGW Ubjg== X-Gm-Message-State: AOJu0YxNEjgRNdPiE3E/nE9sWB2qq0lpksUp8GYOygWlJfFwO5o7Py2h OL/VKwEt3E45mCO+TLusi6QzWL1MfWdm7c/sEQJNfbl5HviB X-Google-Smtp-Source: AGHT+IHfOsWwH7XeGwxyO82lQ7Beiea2aMSZMszgEK2VhB9dcZJ2V4KeyfBreF3d8IlhWEEKQTrnQw== X-Received: by 2002:a05:6e02:1be1:b0:360:2197:4bbe with SMTP id y1-20020a056e021be100b0036021974bbemr15914894ilv.59.1704229735102; Tue, 02 Jan 2024 13:08:55 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:54 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring , Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 13/24] arm64: dts: tegra: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:37 -0700 Message-ID: <20240102140734.v4.13.Ic12bf13efe60f9ffaa444126c55a35fbf6c521cc@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/bo= ot/dts/nvidia/tegra132-norrin.dts index bbc2e9bef08da..14d58859bb55c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13BDD18AFA for ; Tue, 2 Jan 2024 21:08:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="DqgZYr4s" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7b7fbe3db16so507816539f.3 for ; Tue, 02 Jan 2024 13:08:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229736; x=1704834536; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ASVoJVcd+TT62Fgbp6rK6yB+IeWHJc5zYIDcydTnCh8=; b=DqgZYr4s3hSliN6FFFZaaGj74rg0u+PKQ1gTCVl99wqo4J+y870TQTIqaDrLDd/TzA IybtfT638ChuMEOSvh8m1OL/HOeSwCZUVK0vYTxkluiEZDWtcCcavssrYXdS7znuMpop e48pWg80Kd4vg6POS7V8Vk2nIpVzTckgE1a+c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229736; x=1704834536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ASVoJVcd+TT62Fgbp6rK6yB+IeWHJc5zYIDcydTnCh8=; b=owjQYf/5SiSu89gMNXDhYiIWxG5KFIK+gKVkoui/ioMytACv3RxhHaGrtgLejtayou 8v2gp6+XQhelw78YZwIltuUqrRUIDvkI6IS//Re7x46b5XsWS896jalXjPkcOuP8+eWo 83/acjAPGCANc1ae31/ew8ozJKZcvZHr5qBcU49pxdyPlVEgjrngrd0eXejkO3YD9G45 K3dxaIZqy9ihdNjNyJxUba4T3p2dxMMHVsTf8WqPkDi0bzWGvWXl+Q+K/99N38vAG6aI QgoBp2/Re3RplY0WZjRDGwKNJBbuePz5ucwPmRD8pdRCo6aQRBhFdShKoeP5FwlKZ+Up UjIg== X-Gm-Message-State: AOJu0YwcBrmu2h5rsvL20qeXHTa2mOMndR2RoTqTpuF7gYs10pnutzL8 Vpqd2mNaJHDuZ3Ujemgpmhngq+fLh9OSI1vHUns7VicAR63v X-Google-Smtp-Source: AGHT+IFfB2E9EzwO+I1teXfZzVOtZVKaH/8eX07388HbCZbdRd+yWGht2HftqPyzTSf0/1SlFl/Oyg== X-Received: by 2002:a5d:9358:0:b0:7ba:e1c5:7b47 with SMTP id i24-20020a5d9358000000b007bae1c57b47mr15402309ioo.33.1704229736202; Tue, 02 Jan 2024 13:08:56 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:55 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Douglas Anderson , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v4 14/24] arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:38 -0700 Message-ID: <20240102140734.v4.14.I2ee94aede9e25932f656c2bdb832be3199fa1291@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by: Douglas Anderson Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Douglas's Reviewed-by tag from v2 review Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index 46aaeba286047..f3a6da8b28901 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -649,6 +649,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0857E18C07 for ; Tue, 2 Jan 2024 21:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="G/dP0i3f" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7ba8f139522so493859439f.1 for ; Tue, 02 Jan 2024 13:08:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229737; x=1704834537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=17sTLQMT2wthv6A1NoR1+c8v3q9aB7n6ZqwH4HJJEV0=; b=G/dP0i3fJD0GauZiZhHTIMDLCqWdj0PmuwNf+pRtfpGVkOOxze1QGiQHgR8CJXkzQ0 M1eOOs20S4ff2isiJd9MsA1GwnWU0ZaMmDK6mVPekj7tWiRLCYxMiGDsFQg1tacsJCqK 7IJ10o14ZlZJ7KSVfc6p/qi8iz7hntt+wkNKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229737; x=1704834537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=17sTLQMT2wthv6A1NoR1+c8v3q9aB7n6ZqwH4HJJEV0=; b=aLIqPqdsgdrJJ0YU0oKY7Gdou0Fjuwdf+OYFjZC6CSZ7kNxXLHd75KQbFCBLfyky2W RVJjaqGtlLgpRpgVcgeGBU9iC29tImMpa6RI7LKtXjVM3afH4RprdsnQkgCMJcmbpHkQ qw9VM1aZybyA7YmPZI4JHeahdXsQomIao34WtizGKcc7dyyh+XJRWIXCr3yzXaZ03eBl zWApVXSF9RkK6iinKGroLb8G3hVEtZgtVNZWfqukyyJoKzO/r4XoCsIKWHwITH2z8/ic xB9y7DqyqhtpI21oDL+oycmne8Rz1uf191oIpdi8lQ+aAC9itJnY8uBpqk8xLqkxctpO 2hzw== X-Gm-Message-State: AOJu0YyyYOCDvH0JC0SVxCu/fqnXwT65mcHuHQwuIt/WmtsDTeKhSbcg nJy+rDYVP7UezXnA3Tv0I4kTRdaoQ1dwy1jfnwnr/pXL+feI X-Google-Smtp-Source: AGHT+IG15JicEnj5m9+AYHheVx6jq8nHGYdtkF3GHDFBR8wkn+8r3oGMHOzGhdudxknyHLeWlKuuSA== X-Received: by 2002:a05:6602:19cf:b0:7ba:8706:3413 with SMTP id ba15-20020a05660219cf00b007ba87063413mr23570133iob.41.1704229737084; Tue, 02 Jan 2024 13:08:57 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:56 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Douglas Anderson , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v4 15/24] arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:39 -0700 Message-ID: <20240102140734.v4.15.I7ea3f53272c9b7cd77633adfd18058ba443eed96@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by: Douglas Anderson Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Douglas's Reviewed-by tag from v2 review Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index 9ea6636125ad9..2ba4ea60cb147 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index ebae545c587c4..fbfac7534d3c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04052168B4 for ; Tue, 2 Jan 2024 21:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="gPGOZCPV" Received: by mail-io1-f48.google.com with SMTP id ca18e2360f4ac-7ba834684abso506386539f.2 for ; Tue, 02 Jan 2024 13:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229738; x=1704834538; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBXG8fkqI4E9TDywbJQDVQlGARTRe1Vl9dne1ILm/18=; b=gPGOZCPVl2IIrjDodIynds27pMs1g9tjyI6RUW8c4K5irQ1QWFY02ZdmSp9dw1xXuD lVXArgUDrQ1w0wwrIRF2JSKyrb2MoJmnK0jQdeXA9XfriG2gO5eaIKLgFI/l0UfGKoUS ImvMVxBWqgtbgpsE3ief97V6bU0JucG9PvaZY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229738; x=1704834538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBXG8fkqI4E9TDywbJQDVQlGARTRe1Vl9dne1ILm/18=; b=wlRizZOXCADgVzTxXqZEzSDm7Z9PcSEN39XiRl/37+ctImEKlX5IVBqJVWmMan8YvY QRuTl1VALfQRgqDMMse3nGoHcC44LmaLTpEbfEBjdpcedVpN8uaqbA436mQNpvl6BQkJ 5uhAbahYQEFmyOl4jquZsMQ05RNw63x4rEM9gKgLylDxcX47ih7LiNFON7R0AqqLa1Qh tn24Teeosw5rwpS3CVanuY+FwVSvEBLS/tJcCEkB7X3FAu5Muo3ActKoVPFeSKr/lvl1 aGlzuedqh8E+g+gORTPveIEi2jfR6kalQfGukwRLiAYK7FetYgmKD3NP7TG5GN8uZzDv OqEg== X-Gm-Message-State: AOJu0YxCBMj/eBuIiC07OwodZoLD4fUlvtIKfIET8YRjw/2uxlMyL8+x nNZiAB30uNlBYMREOW6PTYGA59B6hI4AL2ZMTXhst1hKngwZ X-Google-Smtp-Source: AGHT+IFDiPa9pElKMxmX/lH+gQE+ZfY9viPPALh0NbNdlcQ8hMR9S/3o4NKAXs823EmCxtbJutVSRw== X-Received: by 2002:a5d:974b:0:b0:7b7:4b32:7986 with SMTP id c11-20020a5d974b000000b007b74b327986mr22772171ioo.27.1704229738043; Tue, 02 Jan 2024 13:08:58 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:57 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Douglas Anderson , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v4 16/24] arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:40 -0700 Message-ID: <20240102140734.v4.16.I870e2c3490e7fc27a8f6bc41dba23b3dfacd2d13@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by: Douglas Anderson Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Douglas's Reviewed-by tag from v2 review Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index 0ab5e8f53ac9f..e8276db9eabb2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -852,6 +852,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99DE318E1C for ; Tue, 2 Jan 2024 21:08:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="FRVfJom6" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7bb99f77f97so50074439f.1 for ; Tue, 02 Jan 2024 13:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229739; x=1704834539; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HRoMMnuwwy1ybNYQkYoJT5CIAhjtnaw7FKUhRhlzX2I=; b=FRVfJom6hMAFayRvvyslNUklQnuLd0ysUghLiqfhR6iLGS1kGoXbYm6H9qGTU8wu6P XfpobjuNTGE9PZlaiRo72OJoWH8vPqtqoTDC69Ld3yX3qpIlH2h/CZ2SfvcrfIrrQ08E L/fRdPj+tw6Xlqa4PVQvC5kDXGmfh66BqgmGk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229739; x=1704834539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HRoMMnuwwy1ybNYQkYoJT5CIAhjtnaw7FKUhRhlzX2I=; b=PPT5/yY765F/XGzEbF1q5LfLd2RQh84/MxJ+gIIOMJHdRNIg1EQb9ow8/hj2GZFMV1 zVJwIhhncTG2dGNsP9PAmVG+ElBWAhuXZ4ID+QDi7A1+kKnAvRwae+XvqRjzK1j1ivBV gm9dZtRD0VNhOViMC3Kp5MbS6mnA52Ec3bPGP0AADcnOgHdKCTDRWCUx1waRe+LbC08d v2h6CAzAkmW9ONtIVU7CtRPY+CCm5OeDBZ0w/6jfpEZm3H60tszJBdAy305yGpFRiSw3 K0ouUhmQ5JUBkqTBvNOXwoyY96F0wavnYb18PlYGzJ07ra+pxliQNwngIg9gPs05KHzL Rfag== X-Gm-Message-State: AOJu0YwC2AopcYKD3/AAQ2Hy9jwRARdP860S1q06MFV3lLpfi6zs26gs MYs5ytxcGRY4NfGuP/1GlBQ4jwokv4/iboErZbCXmOROZ3iu X-Google-Smtp-Source: AGHT+IFgjON8QaOIIt26i2gGQ8LaLRzi4hK2OMzadsvli0BLJTN6UjupAQhSNUzvjDASC8Dg4A9IRQ== X-Received: by 2002:a5d:83c2:0:b0:7bb:b722:63c1 with SMTP id u2-20020a5d83c2000000b007bbb72263c1mr34165ior.16.1704229738882; Tue, 02 Jan 2024 13:08:58 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:58 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 17/24] arm64: dts: rockchip: rk3399: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:41 -0700 Message-ID: <20240102140734.v4.17.Ice617703aded22ad4c806459129e1ae693eb57af@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Signed-off-by: Mark Hasemeyer --- (no changes since v3) Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 789fd0dcc88ba..b5734e056aef1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -603,6 +603,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f43.google.com (mail-io1-f43.google.com [209.85.166.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCAE018EB4 for ; Tue, 2 Jan 2024 21:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BuKTDh26" Received: by mail-io1-f43.google.com with SMTP id ca18e2360f4ac-7bade847536so342478539f.0 for ; Tue, 02 Jan 2024 13:09:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229740; x=1704834540; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ukfFPOjxIuuxKMITUORsVWUdW86ng+CgXwCq16suFWg=; b=BuKTDh26A6XoTsL9jU4OHGP74zfboMwfa682+h1xxyYoT9Wy7X034wmDLOa2XtgGHj JNnJTueHayzv1E/RFzT1boN8Y1067xCddRoyDnwSi86lGooWovPJ5qzmDFOKvWp7DZNC KTbZD5Zoa8/3Fc58AX59iHYNm4dEDn288uGp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229740; x=1704834540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ukfFPOjxIuuxKMITUORsVWUdW86ng+CgXwCq16suFWg=; b=K52+dZkqcwUdL33k4c+ykNU8wUHeT5xaWGV5wZr90RMEwtUK5C+lS6ddG2qBcTVoLc JnLbkKCGkC4HMDLXSoBpTdF4EzRAxf3hYnQp5njVc0qO/4q4Co+NbrHaW6HKJEotwQb3 Lf/E32cMk6D29mRWojNQhYZ0lytJ3aERZS3HM3sTTyxtfQ4ED+eyOVSLlumvPXoVGLrt Aa5ZFXB5qZKJ+4gtvm65AUFm06ZIoFJ49ZbO1viq/gWHS5tjc+tX/SkZmKowBjaXa2o3 tML1v8HexstfoMTPIb5EFERjFoGljyudhNmLzxBFd8UwTWVr3hdMBtMLiWmCUgA1Fnsk 8j6Q== X-Gm-Message-State: AOJu0YyrsPQfNixsVE/3fKMIV3UOHfGgo038iL7ASkudUQW6aSh4A1sQ 1zEQ88GMgKCNa9y3fe/ZzINBgUIbMYtK+KQVj/cM4ZK8A1+O X-Google-Smtp-Source: AGHT+IHQLlMXlASfyYWPPcAmTYaHNcLGLWehburZ9CX9ch22O4LYpZP838Qcp2DVG1hld682ssfAhg== X-Received: by 2002:a5d:9a17:0:b0:7bb:41bd:715f with SMTP id s23-20020a5d9a17000000b007bb41bd715fmr12202311iol.39.1704229739844; Tue, 02 Jan 2024 13:08:59 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:59 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v4 18/24] of: irq: add wake capable bit to of_irq_resource() Date: Tue, 2 Jan 2024 14:07:42 -0700 Message-ID: <20240102140734.v4.18.I29b26a7f3b80fac0a618707446a10b6cc974fdaf@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add wake capability information to the IRQ resource. Wake capability is assumed based on conventions provided in the devicetree wakeup-source binding documentation. An interrupt is considered wake capable if the following are true: 1. A wakeup-source property exits in the same device node as the interrupt. 2. The IRQ is marked as dedicated by setting its interrupt-name to "wakeup". The wakeup-source documentation states that dedicated interrupts can use device specific interrupt names and device drivers are still welcome to use their own naming schemes. This API is provided as a helper if one is willing to conform to the above conventions. The ACPI subsystems already provides similar APIs that allow one to query the wake capability of an IRQ. This brings closer feature parity to the devicetree. Reviewed-by: Rob Herring Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Rob's Reviewed-by tag from v2 -Ignored Andy's Reviewed-by tag per his request: https://lore.kernel.org/all/ZYxgQn8L7ENkc0AJ@smile.fi.intel.com/ Changes in v3: -Use DEFINE_RES_IRQ_NAMED_FLAGS macro Changes in v2: -Update logic to return true only if wakeup-source property and "wakeup" interrupt-name are defined -irq->IRQ, api->API drivers/of/irq.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 174900072c18c..cdecdc3515f88 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -383,11 +383,39 @@ int of_irq_parse_one(struct device_node *device, int = index, struct of_phandle_ar } EXPORT_SYMBOL_GPL(of_irq_parse_one); =20 +/** + * __of_irq_wake_capable - Determine whether a given IRQ index is wake cap= able + * + * The IRQ is considered wake capable if the following are true: + * 1. wakeup-source property exists + * 2. provided IRQ index is labelled as a dedicated wakeirq + * + * This logic assumes the provided IRQ index is valid. + * + * @dev: pointer to device tree node + * @index: zero-based index of the IRQ + * Return: True if provided IRQ index for #dev is wake capable. False othe= rwise. + */ +static bool __of_irq_wake_capable(const struct device_node *dev, int index) +{ + int wakeindex; + + if (!of_property_read_bool(dev, "wakeup-source")) + return false; + + wakeindex =3D of_property_match_string(dev, "interrupt-names", "wakeup"); + return wakeindex >=3D 0 && wakeindex =3D=3D index; +} + /** * of_irq_to_resource - Decode a node's IRQ and return it as a resource * @dev: pointer to device tree node - * @index: zero-based index of the irq + * @index: zero-based index of the IRQ * @r: pointer to resource structure to return result into. + * + * Return: Linux IRQ number on success, or 0 on the IRQ mapping failure, or + * -EPROBE_DEFER if the IRQ domain is not yet created, or error code in ca= se + * of any other failure. */ int of_irq_to_resource(struct device_node *dev, int index, struct resource= *r) { @@ -399,6 +427,7 @@ int of_irq_to_resource(struct device_node *dev, int ind= ex, struct resource *r) /* Only dereference the resource if both the * resource and the irq are valid. */ if (r && irq) { + u32 irq_flags; const char *name =3D NULL; =20 memset(r, 0, sizeof(*r)); @@ -409,9 +438,11 @@ int of_irq_to_resource(struct device_node *dev, int in= dex, struct resource *r) of_property_read_string_index(dev, "interrupt-names", index, &name); =20 - r->start =3D r->end =3D irq; - r->flags =3D IORESOURCE_IRQ | irqd_get_trigger_type(irq_get_irq_data(irq= )); - r->name =3D name ? name : of_node_full_name(dev); + irq_flags =3D irqd_get_trigger_type(irq_get_irq_data(irq)); + if (__of_irq_wake_capable(dev, index)) + irq_flags |=3D IORESOURCE_IRQ_WAKECAPABLE; + + *r =3D DEFINE_RES_IRQ_NAMED_FLAGS(irq, name ?: of_node_full_name(dev), i= rq_flags); } =20 return irq; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-il1-f175.google.com (mail-il1-f175.google.com [209.85.166.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8350218ECB for ; Tue, 2 Jan 2024 21:09:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Jd+OrY9Y" Received: by mail-il1-f175.google.com with SMTP id e9e14a558f8ab-35fe47edd2eso20695865ab.0 for ; Tue, 02 Jan 2024 13:09:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229740; x=1704834540; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mrqyCRQGWqtYZon/B8x6Cl4Beyi5N2srdFtijVb67bM=; b=Jd+OrY9YWz3i/Dgd40CfK61o+Ojf3v5aYpvPs2XixprcNnM76DiksrFsbbvnYCw1F/ NsxXHGO/4IdweWWLAfvIFHf3LCILdaCKVxlgufoMIRO5YwRMy8+w1Zs+GD/2UzJNi/6Q 4C4KqXzv4tj0m1mlNjS+7c7LM29ibY27GoC8Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229740; x=1704834540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mrqyCRQGWqtYZon/B8x6Cl4Beyi5N2srdFtijVb67bM=; b=g99TlKcnX2a86hOv18ZUq9wlLTmnot74zH2AdQJ4aL/2MTgEyF8k6ibq6n7BWpsgFq HB3PazDILxhqh8o2rhVNNKXWJeB3cqO4iw71chEnGSAI9UmdAKzDbeZsNgGeAlLX/Vjo XBisXZV7DvUWbL/gDmmWKPfgWcgYcCptlhDY7OTMb2Jq4cC80XmDzDQpjkWTBAC9GwIl Ip7DfbcTWu6poRw0pI37vkmu9Fir6vnlB3fZhAIQ29YfMBzwg6i1ImPuLW/mU8zYYeK2 EPmEmkZY+/SyubtfDpwnOGLWNx17dpMWL1RETthERuM2g48k4ytHRvHAPo1U+hXW+mNm S/Kg== X-Gm-Message-State: AOJu0YywHGWtmbFru5tYoH3HFXKCU2rmaYNrC6nlF9JtrLoOAT6vTtxa VFnx/RhGR6HzYnyVOVlm5tx9OlcnfESFZ0U3jK1rjGzFQNBL X-Google-Smtp-Source: AGHT+IFQzUcaDIy67wDz2ySoGOwpwi0H1El9nejGF4EWnyK78NzOzFm7YOjrdDK8vQhhffUOy1ZGCw== X-Received: by 2002:a05:6e02:1a0e:b0:35d:59b3:2f7d with SMTP id s14-20020a056e021a0e00b0035d59b32f7dmr40919ild.18.1704229740602; Tue, 02 Jan 2024 13:09:00 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:00 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v4 19/24] of: irq: Add default implementation for of_irq_to_resource() Date: Tue, 2 Jan 2024 14:07:43 -0700 Message-ID: <20240102140734.v4.19.I31d4dd6a7e5a3e5eee05c87b358e63cd1aa0e467@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to of_irq_to_resource_table(), add a default implementation of of_irq_to_resource() for systems that don't have CONFIG_OF_IRQ defined. Acked-by: Rob Herring Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Rob's Ack tag from v2 include/linux/of_irq.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index d6d3eae2f1452..0d73b2ca92d31 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -34,8 +34,6 @@ static inline int of_irq_parse_oldworld(const struct devi= ce_node *device, int in =20 extern int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *ou= t_irq); extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data= ); -extern int of_irq_to_resource(struct device_node *dev, int index, - struct resource *r); =20 #ifdef CONFIG_OF_IRQ extern void of_irq_init(const struct of_device_id *matches); @@ -44,6 +42,7 @@ extern int of_irq_parse_one(struct device_node *device, i= nt index, extern int of_irq_count(struct device_node *dev); extern int of_irq_get(struct device_node *dev, int index); extern int of_irq_get_byname(struct device_node *dev, const char *name); +extern int of_irq_to_resource(struct device_node *dev, int index, struct r= esource *r); extern int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs); extern struct device_node *of_irq_find_parent(struct device_node *child); @@ -76,6 +75,11 @@ static inline int of_irq_get_byname(struct device_node *= dev, const char *name) { return 0; } +static inline int of_irq_to_resource(struct device_node *dev, int index, + struct resource *r) +{ + return 0; +} static inline int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs) { --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45E2818ED5 for ; Tue, 2 Jan 2024 21:09:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PcMWXXwG" Received: by mail-io1-f47.google.com with SMTP id ca18e2360f4ac-7b7fb34265fso491742739f.3 for ; Tue, 02 Jan 2024 13:09:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229741; x=1704834541; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yuhkCzL2l+Es2a6yZtXMYTtf834z1coLX69xx0eVIxw=; b=PcMWXXwGKxi3lOnc4PVx41Mbqm//fWa3Q8P5FK/aWfOfM4ABtshA+gXmY6cY5tkNqe A8sIKKRrVMk2Wgz+YPZcl7R+2GAF0KdMU6rHV5xr1AJt55NCYK65MqZ7LBZzmpSh0iC2 qwsim/jG2f+82HVKObdmWlOw9oG0hMp41Y5Cg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229741; x=1704834541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yuhkCzL2l+Es2a6yZtXMYTtf834z1coLX69xx0eVIxw=; b=KnLDm2vCvl/Dffv31Fzhgn3E3Ebwy5BFAsVPRgvRjLgx9YQLn9wygLexpPtVpOTHmv fInLxsbP9NPEBz3uaJNUgPAQuqOtLXNwJD7dccFMII7R7hvYa244haA0TFR6ViKXk8R6 dYKQco9l9tEl4fvQzhnXC1cmxeRx4XX58iD2MCsUextUWxp27N+vhBjvLHoi0N0r3sZ9 o0np4GRQaJGxKk1NSM7IAjJMQFOKr5Bha1/yyxbFWuvdDcWAHlzjhaWdI3x5mJrAyTrT wuRjRvZA5EP8MDLggyTBiR+wYzb/TMWYouSsngtFAqdV0wBd0g/8Yuge/J+PpC6DNTN8 +xLg== X-Gm-Message-State: AOJu0YwH0eHZPn4HmfdGE7wRDcNKOLK/up3uX8QNg0h8eTjgoqZRbNZr axCY05uiQfuGod8we9ms/xqY3dstBMIAkStE+48Au/u7qjOZ X-Google-Smtp-Source: AGHT+IFp2QttZwtW1kCru0qHHoHoT70NG6O1ERnMyBH3znA+Ew+qlRfeZfzdwG/Vk/iKKPZKXXki8w== X-Received: by 2002:a05:6602:1492:b0:7b7:be85:23c with SMTP id a18-20020a056602149200b007b7be85023cmr25585003iow.30.1704229741350; Tue, 02 Jan 2024 13:09:01 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:01 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v4 20/24] of: irq: Remove extern from function declarations Date: Tue, 2 Jan 2024 14:07:44 -0700 Message-ID: <20240102140734.v4.20.I319e781c11e6352eb5b6c408dc20bd54a720edbf@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The extern keyword is implicit for function declarations. Remove it where possible and adjust the line wrapping accordingly. Acked-by: Rob Herring Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Rob's Ack tag from v2 Changes in v2: -New patch include/linux/of_irq.h | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index 0d73b2ca92d31..a130dcbc4bb45 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -32,27 +32,26 @@ static inline int of_irq_parse_oldworld(const struct de= vice_node *device, int in } #endif /* CONFIG_PPC32 && CONFIG_PPC_PMAC */ =20 -extern int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *ou= t_irq); -extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data= ); +int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq); +unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data); =20 #ifdef CONFIG_OF_IRQ -extern void of_irq_init(const struct of_device_id *matches); -extern int of_irq_parse_one(struct device_node *device, int index, - struct of_phandle_args *out_irq); -extern int of_irq_count(struct device_node *dev); -extern int of_irq_get(struct device_node *dev, int index); -extern int of_irq_get_byname(struct device_node *dev, const char *name); -extern int of_irq_to_resource(struct device_node *dev, int index, struct r= esource *r); -extern int of_irq_to_resource_table(struct device_node *dev, - struct resource *res, int nr_irqs); -extern struct device_node *of_irq_find_parent(struct device_node *child); -extern struct irq_domain *of_msi_get_domain(struct device *dev, +void of_irq_init(const struct of_device_id *matches); +int of_irq_parse_one(struct device_node *device, int index, + struct of_phandle_args *out_irq); +int of_irq_count(struct device_node *dev); +int of_irq_get(struct device_node *dev, int index); +int of_irq_get_byname(struct device_node *dev, const char *name); +int of_irq_to_resource(struct device_node *dev, int index, struct resource= *r); +int of_irq_to_resource_table(struct device_node *dev, struct resource *res, + int nr_irqs); +struct device_node *of_irq_find_parent(struct device_node *child); +struct irq_domain *of_msi_get_domain(struct device *dev, struct device_node *np, enum irq_domain_bus_token token); -extern struct irq_domain *of_msi_map_get_device_domain(struct device *dev, - u32 id, - u32 bus_token); -extern void of_msi_configure(struct device *dev, struct device_node *np); +struct irq_domain *of_msi_map_get_device_domain(struct device *dev, u32 id, + u32 bus_token); +void of_msi_configure(struct device *dev, struct device_node *np); u32 of_msi_map_id(struct device *dev, struct device_node *msi_np, u32 id_i= n); #else static inline void of_irq_init(const struct of_device_id *matches) @@ -117,7 +116,7 @@ static inline u32 of_msi_map_id(struct device *dev, * implements it differently. However, the prototype is the same for all, * so declare it here regardless of the CONFIG_OF_IRQ setting. */ -extern unsigned int irq_of_parse_and_map(struct device_node *node, int ind= ex); +unsigned int irq_of_parse_and_map(struct device_node *node, int index); =20 #else /* !CONFIG_OF && !CONFIG_SPARC */ static inline unsigned int irq_of_parse_and_map(struct device_node *dev, --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5986319472 for ; Tue, 2 Jan 2024 21:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="VTa2leDx" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7ba8f139522so493862939f.1 for ; Tue, 02 Jan 2024 13:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229742; x=1704834542; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/6j1jotrF6PIPGIyj1YNZnkSmwkK1WAFrbZbjbyI7go=; b=VTa2leDxBK9KlSyJAN+wQVXeA1P9mITLlz8byiLbkbleOsU2gLTU7X0nQz3gcCCSE0 wj/aQkuDG9REKxEHVAzkvWZ/OldAVYC4tkeCsOvgyWxv2QPLLgy8aelwkID87NWiFtzW +YHSpuj+3e2XnAHEZjOe4kTixkYZQnfUHEn40= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229742; x=1704834542; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/6j1jotrF6PIPGIyj1YNZnkSmwkK1WAFrbZbjbyI7go=; b=GCQOgvu1hEQN9mW/7awOK3p72pCMmfqXmid60xFui1Z45wXu9Kz51JC3RMIrNsi2Pa N4UtMQ2URyfhXtHm5G0J6BA+s2sgu6dI4Ai7qNFgHexlvZjd/b55DN4oAAe0pLO4Ox7O HRoioUtOavQ+AtCwQIkhl0RFLOOjjUydF8A+EUNlLtlJV98UEEyHscf4Br4csVTd677t l/C9ikSlZevterovI1y/GgI4TWIOveC/IYPqkLF2DCFsp2iYnixhDWf77ZmzQI6FHkp2 +l0ufpqiUyGI3LMJaRUDwo9F+wGqCWTu3V1svq9XnZJ2+xVcbJRnl+7gWZXRTurfce68 XHXQ== X-Gm-Message-State: AOJu0YwzmjKQXqqx0E3cGQsJe09dhUOU3LY02LOUsOvwhvzXotGxaeB/ 6+f3RRQgdXau/ep1h95fswlge0YHQVN524HBL6WQvJ30wdYe X-Google-Smtp-Source: AGHT+IEnk7hkWBTpiE59//TC3J8Hc2YJfZJNZSBWZ/zM4jqFy4w9a/MURJc4iEaZLOWtCJ4vPXcb4Q== X-Received: by 2002:a05:6602:19cf:b0:7ba:8706:3413 with SMTP id ba15-20020a05660219cf00b007ba87063413mr23570270iob.41.1704229742417; Tue, 02 Jan 2024 13:09:02 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:02 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , Sakari Ailus , Daniel Scally , Frank Rowand , Greg Kroah-Hartman , Heikki Krogerus , Len Brown , "Rafael J. Wysocki" , Rob Herring , devicetree@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH v4 21/24] device property: Modify fwnode irq_get() to use resource Date: Tue, 2 Jan 2024 14:07:45 -0700 Message-ID: <20240102140734.v4.21.I38ac58ab04985a404ed6551eb5813fa7841ef410@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The underlying ACPI and OF subsystems provide their own APIs which provide IRQ information as a struct resource. This allows callers to get more information about the IRQ by looking at the resource flags. For example, whether or not an IRQ is wake capable. Suggested-by: Andy Shevchenko Reviewed-by: Sakari Ailus Signed-off-by: Mark Hasemeyer Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring --- Changes in v4: -Add Sakari's Reviewed-by tag from v2 -Remove ioport.h dependency in fwnode.h -Use Andy's @linux.intel.com email Changes in v3: -Add Suggested-by tag -Initialize struct resource to 0 on stack -EXPORT_SYMBOL()->EXPORT_SYMBOL_GPL() -Remove extra space in commit message -Reformat fwnode_irq_get_resource() declaration Changes in v2: -New patch drivers/acpi/property.c | 11 +++++------ drivers/base/property.c | 32 +++++++++++++++++++++++++------- drivers/of/property.c | 8 ++++---- include/linux/fwnode.h | 8 +++++--- include/linux/property.h | 2 ++ 5 files changed, 41 insertions(+), 20 deletions(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index a6ead5204046b..891fff5a16797 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -1627,17 +1627,16 @@ static int acpi_fwnode_graph_parse_endpoint(const s= truct fwnode_handle *fwnode, return 0; } =20 -static int acpi_fwnode_irq_get(const struct fwnode_handle *fwnode, - unsigned int index) +static int acpi_fwnode_irq_get_resource(const struct fwnode_handle *fwnode= , unsigned int index, + struct resource *r) { - struct resource res; int ret; =20 - ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, &res); + ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, r); if (ret) return ret; =20 - return res.start; + return r->start; } =20 #define DECLARE_ACPI_FWNODE_OPS(ops) \ @@ -1664,7 +1663,7 @@ static int acpi_fwnode_irq_get(const struct fwnode_ha= ndle *fwnode, acpi_graph_get_remote_endpoint, \ .graph_get_port_parent =3D acpi_fwnode_get_parent, \ .graph_parse_endpoint =3D acpi_fwnode_graph_parse_endpoint, \ - .irq_get =3D acpi_fwnode_irq_get, \ + .irq_get_resource =3D acpi_fwnode_irq_get_resource, \ }; \ EXPORT_SYMBOL_GPL(ops) =20 diff --git a/drivers/base/property.c b/drivers/base/property.c index a1b01ab420528..441899171d19d 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -1046,6 +1046,29 @@ void __iomem *fwnode_iomap(struct fwnode_handle *fwn= ode, int index) } EXPORT_SYMBOL(fwnode_iomap); =20 +/** + * fwnode_irq_get_resource - Get IRQ directly from a fwnode and populate + * the resource struct + * @fwnode: Pointer to the firmware node + * @index: Zero-based index of the IRQ + * @r: Pointer to resource to populate with IRQ information. + * + * Return: Linux IRQ number on success. Negative errno on failure. + */ +int fwnode_irq_get_resource(const struct fwnode_handle *fwnode, unsigned i= nt index, + struct resource *r) +{ + int ret; + + ret =3D fwnode_call_int_op(fwnode, irq_get_resource, index, r); + /* We treat mapping errors as invalid case */ + if (ret =3D=3D 0) + return -EINVAL; + + return ret; +} +EXPORT_SYMBOL_GPL(fwnode_irq_get_resource); + /** * fwnode_irq_get - Get IRQ directly from a fwnode * @fwnode: Pointer to the firmware node @@ -1055,14 +1078,9 @@ EXPORT_SYMBOL(fwnode_iomap); */ int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index) { - int ret; + struct resource r =3D {}; =20 - ret =3D fwnode_call_int_op(fwnode, irq_get, index); - /* We treat mapping errors as invalid case */ - if (ret =3D=3D 0) - return -EINVAL; - - return ret; + return fwnode_irq_get_resource(fwnode, index, &r); } EXPORT_SYMBOL(fwnode_irq_get); =20 diff --git a/drivers/of/property.c b/drivers/of/property.c index afdaefbd03f61..864ea5fa5702b 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1425,10 +1425,10 @@ static void __iomem *of_fwnode_iomap(struct fwnode_= handle *fwnode, int index) #endif } =20 -static int of_fwnode_irq_get(const struct fwnode_handle *fwnode, - unsigned int index) +static int of_fwnode_irq_get_resource(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r) { - return of_irq_get(to_of_node(fwnode), index); + return of_irq_to_resource(to_of_node(fwnode), index, r); } =20 static int of_fwnode_add_links(struct fwnode_handle *fwnode) @@ -1469,7 +1469,7 @@ const struct fwnode_operations of_fwnode_ops =3D { .graph_get_port_parent =3D of_fwnode_graph_get_port_parent, .graph_parse_endpoint =3D of_fwnode_graph_parse_endpoint, .iomap =3D of_fwnode_iomap, - .irq_get =3D of_fwnode_irq_get, + .irq_get_resource =3D of_fwnode_irq_get_resource, .add_links =3D of_fwnode_add_links, }; EXPORT_SYMBOL_GPL(of_fwnode_ops); diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h index 2a72f55d26eb8..b82c9c072bcc9 100644 --- a/include/linux/fwnode.h +++ b/include/linux/fwnode.h @@ -9,12 +9,13 @@ #ifndef _LINUX_FWNODE_H_ #define _LINUX_FWNODE_H_ =20 -#include -#include #include #include +#include +#include =20 struct fwnode_operations; +struct resource; struct device; =20 /* @@ -164,7 +165,8 @@ struct fwnode_operations { int (*graph_parse_endpoint)(const struct fwnode_handle *fwnode, struct fwnode_endpoint *endpoint); void __iomem *(*iomap)(struct fwnode_handle *fwnode, int index); - int (*irq_get)(const struct fwnode_handle *fwnode, unsigned int index); + int (*irq_get_resource)(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r); int (*add_links)(struct fwnode_handle *fwnode); }; =20 diff --git a/include/linux/property.h b/include/linux/property.h index e6516d0b7d52a..685ba72a8ce9e 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -190,6 +190,8 @@ struct fwnode_handle *fwnode_handle_get(struct fwnode_h= andle *fwnode); void fwnode_handle_put(struct fwnode_handle *fwnode); =20 int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index); +int fwnode_irq_get_resource(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r); int fwnode_irq_get_byname(const struct fwnode_handle *fwnode, const char *= name); =20 unsigned int device_get_child_node_count(const struct device *dev); --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A636199BE for ; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:03 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Sakari Ailus , Andy Shevchenko , Daniel Scally , Greg Kroah-Hartman , Heikki Krogerus , "Rafael J. Wysocki" , linux-acpi@vger.kernel.org Subject: [PATCH v4 22/24] device property: Update functions to use EXPORT_SYMBOL_GPL() Date: Tue, 2 Jan 2024 14:07:46 -0700 Message-ID: <20240102140734.v4.22.I186bc5737c5ac4c3a5a7a91e9ec75645e723ca7b@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the exported functions use EXPORT_SYMBOL() instead of EXPORT_SYMBOL_GPL() and are inconsistent with the other exported functions in the module. The underlying APCI/OF struct fwnode_operations implementations are also exported via EXPORT_SYMBOL_GPL(). Update them to use the EXPORT_SYMBOL_GPL() macro. Suggested-by: Sakari Ailus Reviewed-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer Reviewed-by: Sakari Ailus --- Changes in v4: -EXPORT_SYMBOL->EXPORT_SYMBOL() -Add Andy's Reviewed-by tag Changes in v3: -New patch drivers/base/property.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/base/property.c b/drivers/base/property.c index 441899171d19d..4f686516cac82 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -1044,7 +1044,7 @@ void __iomem *fwnode_iomap(struct fwnode_handle *fwno= de, int index) { return fwnode_call_ptr_op(fwnode, iomap, index); } -EXPORT_SYMBOL(fwnode_iomap); +EXPORT_SYMBOL_GPL(fwnode_iomap); =20 /** * fwnode_irq_get_resource - Get IRQ directly from a fwnode and populate @@ -1082,7 +1082,7 @@ int fwnode_irq_get(const struct fwnode_handle *fwnode= , unsigned int index) =20 return fwnode_irq_get_resource(fwnode, index, &r); } -EXPORT_SYMBOL(fwnode_irq_get); +EXPORT_SYMBOL_GPL(fwnode_irq_get); =20 /** * fwnode_irq_get_byname - Get IRQ from a fwnode using its name @@ -1110,7 +1110,7 @@ int fwnode_irq_get_byname(const struct fwnode_handle = *fwnode, const char *name) =20 return fwnode_irq_get(fwnode, index); } -EXPORT_SYMBOL(fwnode_irq_get_byname); +EXPORT_SYMBOL_GPL(fwnode_irq_get_byname); =20 /** * fwnode_graph_get_next_endpoint - Get next endpoint firmware node @@ -1355,7 +1355,7 @@ int fwnode_graph_parse_endpoint(const struct fwnode_h= andle *fwnode, =20 return fwnode_call_int_op(fwnode, graph_parse_endpoint, endpoint); } -EXPORT_SYMBOL(fwnode_graph_parse_endpoint); +EXPORT_SYMBOL_GPL(fwnode_graph_parse_endpoint); =20 const void *device_get_match_data(const struct device *dev) { --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B1E119BAF for ; Tue, 2 Jan 2024 21:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="UfHrPRyq" Received: by mail-io1-f44.google.com with SMTP id ca18e2360f4ac-7b7a9f90f34so534023839f.2 for ; Tue, 02 Jan 2024 13:09:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229744; x=1704834544; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Hw1xlFNdgkxULgKG3GwEV3Tvyifb1Pre98NYX4zJtY=; b=UfHrPRyq1K9c0fjROBFDROpkjVV6Z50HJqMAJpG8fOpr/uhXpbzrD1pKOfcXkEQa+s mm2PgWG4g6H+26K96NqcZttpagvkW34EJW8+cbLAZQEo6MA35vUcGEwSUvQ/cWX/+oJ7 Sl3uYn4dTikDMei4/omb3FJyPq5XSGvZRlgZQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229744; x=1704834544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Hw1xlFNdgkxULgKG3GwEV3Tvyifb1Pre98NYX4zJtY=; b=qSwaUCEJrqk34CarG6D4Oa9tRxvHE5+ujsjzR5rpIH9PrkoZaa+J70gviA3eINNykg nlA67Oj4TAp3qySeX0TlZwgSDWgzHaElA2qt0q9NPXyoORtlBnmrP76b6yMEcJsRtz/7 JMx7PVzu2rHH16UtLYmN5HvPkJQxPxs7+NF4mjurIEnXdez6YsaK9er2PrsKwX6maQ6r e5bm6tk55aMQsVaSmwGPqNy4A1cLOTE/WQnrgFgzGbUdH5f6R371g9qqEJmTVjKznOhm Fdyj2LOTTVWSix+jATnY89o9Cx/JpV8ciM75fSAPY7WAUEc3Xz/U+s+mYVha082gpPCk NLtA== X-Gm-Message-State: AOJu0YyRax78fdLRSFPSEo/wn3lpF1fIQeJ3QoGgvgHPLizGVUMZzUDO 1yLgP1hwO0CRsvuLm0CqDQHNzYIgM5JneTUMwQ/WKNj0uuJ1 X-Google-Smtp-Source: AGHT+IGAcEK3EYkLyXzYhh0D70uGgywH+FK/tVqwGL/00V/2ysJdiNcQHdqv0vUPAVh1zNTtSWFZiw== X-Received: by 2002:a05:6602:e03:b0:7ba:a232:30fe with SMTP id gp3-20020a0566020e0300b007baa23230femr13087873iob.20.1704229744185; Tue, 02 Jan 2024 13:09:04 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:03 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , David Gow , Greg Kroah-Hartman , Mark Brown , "Rafael J. Wysocki" , Takashi Iwai , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Subject: [PATCH v4 23/24] platform: Modify platform_get_irq_optional() to use resource Date: Tue, 2 Jan 2024 14:07:47 -0700 Message-ID: <20240102140734.v4.23.Ife9ebad2bbfbab3a05e90040f344d750aa0aac7e@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unify handling of ACPI, GPIO, devictree, and platform resource interrupts in platform_get_irq_optional(). Each of these subsystems provide their own APIs which provide IRQ information as a struct resource. This simplifies the logic of the function and allows callers to get more information about the IRQ by looking at the resource flags. For example, whether or not an IRQ is wake capable. Signed-off-by: Mark Hasemeyer --- Changes in v4: -platform_get_irq_optional() returns 0 on success Changes in v3: -Remove PTR_ERR check -Move platform_res assignment -Check for irq =3D=3D 0 to trigger WARN msg -Refactor error handling of acpi_dev_get_gpio_irq_resource() to be consistent with fwnode_irq_get_resource() -Remove extra blank lines -Initialize struct resource on stack Changes in v2: -irq->IRQ -Remove cast to struct resource -Conform to get_optional() function naming -Revert move of irq_get_irq_data() -Add NULL check on struct resource* -Use fwnode to retrieve IRQ for DT/ACPI drivers/base/platform.c | 90 +++++++++++++++++++++------------ include/linux/platform_device.h | 3 ++ 2 files changed, 61 insertions(+), 32 deletions(-) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 10c5779634182..8a42b48922e68 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -151,50 +151,45 @@ EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource_byna= me); #endif /* CONFIG_HAS_IOMEM */ =20 /** - * platform_get_irq_optional - get an optional IRQ for a device + * platform_get_irq_resource_optional - get an optional IRQ for a device a= nd + * populate the resource struct * @dev: platform device * @num: IRQ number index + * @r: pointer to resource to populate with IRQ information. * * Gets an IRQ for a platform device. Device drivers should check the retu= rn - * value for errors so as to not pass a negative integer value to the - * request_irq() APIs. This is the same as platform_get_irq(), except that= it - * does not print an error message if an IRQ can not be obtained. + * value for errors. If no error is returned, the IRQ can be found in r->s= tart. * * For example:: * - * int irq =3D platform_get_irq_optional(pdev, 0); - * if (irq < 0) - * return irq; + * int res =3D platform_get_irq_resource_optional(pdev, 0, &res); + * if (!res) + * return res.start; * - * Return: non-zero IRQ number on success, negative error number on failur= e. + * Return: 0 on success, negative error number on failure. */ -int platform_get_irq_optional(struct platform_device *dev, unsigned int nu= m) +int platform_get_irq_resource_optional(struct platform_device *dev, + unsigned int num, struct resource *r) { int ret; + + if (!r) + return -EINVAL; + #ifdef CONFIG_SPARC /* sparc does not have irqs represented as IORESOURCE_IRQ resources */ if (!dev || num >=3D dev->archdata.num_irqs) goto out_not_found; - ret =3D dev->archdata.irqs[num]; + *r =3D DEFINE_RES_IRQ(dev->archdata.irqs[num]); + ret =3D 0; goto out; #else struct fwnode_handle *fwnode =3D dev_fwnode(&dev->dev); - struct resource *r; =20 - if (is_of_node(fwnode)) { - ret =3D of_irq_get(to_of_node(fwnode), num); - if (ret > 0 || ret =3D=3D -EPROBE_DEFER) - goto out; - } - - r =3D platform_get_resource(dev, IORESOURCE_IRQ, num); - if (is_acpi_device_node(fwnode)) { - if (r && r->flags & IORESOURCE_DISABLED) { - ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), num, r); - if (ret) - goto out; - } - } + ret =3D fwnode_irq_get_resource(fwnode, num, r); + ret =3D ret < 0 ? ret : 0; + if (!ret || ret =3D=3D -EPROBE_DEFER) + goto out; =20 /* * The resources may pass trigger flags to the irqs that need @@ -202,7 +197,9 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) * IORESOURCE_BITS correspond 1-to-1 to the IRQF_TRIGGER* * settings. */ - if (r && r->flags & IORESOURCE_BITS) { + struct resource *platform_res =3D platform_get_resource(dev, IORESOURCE_I= RQ, num); + + if (platform_res && platform_res->flags & IORESOURCE_BITS) { struct irq_data *irqd; =20 irqd =3D irq_get_irq_data(r->start); @@ -211,8 +208,9 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) irqd_set_trigger_type(irqd, r->flags & IORESOURCE_BITS); } =20 - if (r) { - ret =3D r->start; + if (platform_res) { + *r =3D *platform_res; + ret =3D 0; goto out; } =20 @@ -224,9 +222,9 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) * allows a common code path across either kind of resource. */ if (num =3D=3D 0 && is_acpi_device_node(fwnode)) { - ret =3D acpi_dev_gpio_irq_get(to_acpi_device_node(fwnode), num); + ret =3D acpi_dev_get_gpio_irq_resource(to_acpi_device_node(fwnode), NULL= , num, r); /* Our callers expect -ENXIO for missing IRQs. */ - if (ret >=3D 0 || ret =3D=3D -EPROBE_DEFER) + if (!ret || ret =3D=3D -EPROBE_DEFER) goto out; } =20 @@ -234,11 +232,11 @@ int platform_get_irq_optional(struct platform_device = *dev, unsigned int num) out_not_found: ret =3D -ENXIO; out: - if (WARN(!ret, "0 is an invalid IRQ number\n")) + if (WARN(!ret && !r->start, "0 is an invalid IRQ number\n")) return -EINVAL; return ret; } -EXPORT_SYMBOL_GPL(platform_get_irq_optional); +EXPORT_SYMBOL_GPL(platform_get_irq_resource_optional); =20 /** * platform_get_irq - get an IRQ for a device @@ -270,6 +268,34 @@ int platform_get_irq(struct platform_device *dev, unsi= gned int num) } EXPORT_SYMBOL_GPL(platform_get_irq); =20 +/** + * platform_get_irq_optional - get an optional IRQ for a device + * @dev: platform device + * @num: IRQ number index + * + * Gets an IRQ for a platform device. Device drivers should check the retu= rn + * value for errors so as to not pass a negative integer value to the + * request_irq() APIs. This is the same as platform_get_irq(), except that= it + * does not print an error message if an IRQ can not be obtained. + * + * For example:: + * + * int irq =3D platform_get_irq_optional(pdev, 0); + * if (irq < 0) + * return irq; + * + * Return: non-zero IRQ number on success, negative error number on failur= e. + */ +int platform_get_irq_optional(struct platform_device *dev, unsigned int nu= m) +{ + int ret; + struct resource r =3D {}; + + ret =3D platform_get_irq_resource_optional(dev, num, &r); + return ret ?: r.start; +} +EXPORT_SYMBOL_GPL(platform_get_irq_optional); + /** * platform_irq_count - Count the number of IRQs a platform device uses * @dev: platform device diff --git a/include/linux/platform_device.h b/include/linux/platform_devic= e.h index 7a41c72c19591..2117f817d9c9c 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -102,6 +102,9 @@ devm_platform_ioremap_resource_byname(struct platform_d= evice *pdev, =20 extern int platform_get_irq(struct platform_device *, unsigned int); extern int platform_get_irq_optional(struct platform_device *, unsigned in= t); +extern int platform_get_irq_resource_optional(struct platform_device *dev, + unsigned int num, + struct resource *r); extern int platform_irq_count(struct platform_device *); extern int devm_platform_get_irqs_affinity(struct platform_device *dev, struct irq_affinity *affd, --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 04:10:03 2024 Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B2E1A27D for ; Tue, 2 Jan 2024 21:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PAfFIwoc" Received: by mail-io1-f51.google.com with SMTP id ca18e2360f4ac-7ba903342c2so711978739f.3 for ; Tue, 02 Jan 2024 13:09:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229745; x=1704834545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+gYVKYJQzeswl0d2/E7tMkWp3ZqYQjIB7uAjyZVlcw4=; b=PAfFIwocWHybLVBVF3+pQWecm7obgM9gBARpFcuydHBhTwMegiEn/TSeOryKURawSN pOo6iyAsT+RsEpJ+nvuQ1JoMuNfsH5ny7QrkENStE3bVViI0pCcZUCftQFNfDx/9/rWn lx7k6pgCzbZ078uPHvFt3AJlScXJgOQ5xJn+o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229745; x=1704834545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+gYVKYJQzeswl0d2/E7tMkWp3ZqYQjIB7uAjyZVlcw4=; b=Sw8pQfu0C16PW1GlKdjU/IY3YvlBfEc/UDjER77dk2QxTPn9+z3hccuhcmYNmX+xuL AhpQEfPc9zozLIrioWyCxsfgqaF2p5ADKLoJl5f6rLzW7EFDyr+7Ky8L+N/u0PtFr1cg XkdZrpc9LZ7b7j93t8V6LhawKqOdR+YjhaC9k3PEuKCPNGigMowxHONxwE9PSoQazYCO P+frsrtp7p5IJ7yoDlGvijKp6E5nEa69blhYiAC7fIAGpuMeE7kBEU7PQpvI0bGtuIH1 HpWN2W4Ga7ScQdfKJI8pPT6YPBy0N/8I6X+l/SlM28i//D2ICVY46P/192wLbC4nJY8T QCqA== X-Gm-Message-State: AOJu0YwZJjC314jb1hh5WIkWJ/OVq9NrAFbjkTTOMeUZy6wFLyRLbSaX YhRGv4NajC9KcNZPI9IoJLb6e9Bof0FN5Gy2kSgLPgLAYJIH X-Google-Smtp-Source: AGHT+IFpMHUTbdSYjgTU7VYDGXbneJXB8oWhsCE6H0YwNdwQa4e5a0gLz60xS9+mXFMJ6HitoHxZdg== X-Received: by 2002:a05:6602:2985:b0:7ba:ccbb:750d with SMTP id o5-20020a056602298500b007baccbb750dmr18015759ior.12.1704229745012; Tue, 02 Jan 2024 13:09:05 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:09:04 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Benson Leung , Bhanu Prakash Maiya , Chen-Yu Tsai , Guenter Roeck , Prashant Malani , Rob Barnes , Stephen Boyd , chrome-platform@lists.linux.dev Subject: [PATCH v4 24/24] platform/chrome: cros_ec: Use PM subsystem to manage wakeirq Date: Tue, 2 Jan 2024 14:07:48 -0700 Message-ID: <20240102140734.v4.24.Ieee574a0e94fbaae01fd6883ffe2ceeb98d7df28@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros ec driver is manually managing the wake IRQ by calling enable_irq_wake()/disable_irq_wake() during suspend/resume. Modify the driver to use the power management subsystem to manage the wakeirq. Rather than assuming that the IRQ is wake capable, use the underlying firmware/device tree to determine whether or not to enable it as a wake source. Some Chromebooks rely solely on the ec_sync pin to wake the AP but do not specify the interrupt as wake capable in the ACPI _CRS. For LPC/ACPI based systems a DMI quirk is introduced listing boards whose firmware should not be trusted to provide correct wake capable values. For device tree base systems, it is not an issue as the relevant device tree entries have been updated and DTS is built from source for each ChromeOS update. Acked-by: Tzung-Bi Shih Signed-off-by: Mark Hasemeyer --- Changes in v4: -Rebase on linux-next -See each patch for patch specific changes -Add Tzung-Bi's Ack tag -Drop dev_err() during cros_ec_uart_probe() -Initalize struct resource on stack -Update error handling for platform_get_irq_resource_optional() Changes in v3: -Rebase on linux-next -See each patch for patch specific changes -Remove MODULE_DEVICE_TABLE -Drop "cros_ec _" prefix from should_force_irq_wake_capable() -Drop use of dev_err_probe() to be consistent with existing conventions in the driver -Drop *spi argument from cros_ec_spi_dt_probe() -Drop null device_node check from cros_ec_spi_dt_probe() -Add trailing commas to DMI table -Drop redundant "!=3D NULL" in should_force_irq_wake_capable() -Use str_yes_no() to print irq wake capability -Move irqwake handling from the interface specific modules to cros_ec.c Changes in v2: -Rebase on linux-next -Add cover letter -See each patch for patch specific changes -Look for 'wakeup-source' property in cros_ec_spi.c drivers/platform/chrome/cros_ec.c | 48 +++++++++++++++++---- drivers/platform/chrome/cros_ec_lpc.c | 40 ++++++++++++++--- drivers/platform/chrome/cros_ec_spi.c | 15 ++++--- drivers/platform/chrome/cros_ec_uart.c | 14 ++++-- include/linux/platform_data/cros_ec_proto.h | 4 +- 5 files changed, 94 insertions(+), 27 deletions(-) diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cr= os_ec.c index badc68bbae8cc..080b479f39a94 100644 --- a/drivers/platform/chrome/cros_ec.c +++ b/drivers/platform/chrome/cros_ec.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 @@ -168,6 +169,35 @@ static int cros_ec_ready_event(struct notifier_block *= nb, return NOTIFY_DONE; } =20 +static int enable_irq_for_wake(struct cros_ec_device *ec_dev) +{ + struct device *dev =3D ec_dev->dev; + int ret =3D device_init_wakeup(dev, true); + + if (ret) { + dev_err(dev, "Failed to enable device for wakeup"); + return ret; + } + ret =3D dev_pm_set_wake_irq(dev, ec_dev->irq); + if (ret) + device_init_wakeup(dev, false); + + return ret; +} + +static int disable_irq_for_wake(struct cros_ec_device *ec_dev) +{ + int ret; + struct device *dev =3D ec_dev->dev; + + dev_pm_clear_wake_irq(dev); + ret =3D device_init_wakeup(dev, false); + if (ret) + dev_err(dev, "Failed to disable device for wakeup"); + + return ret; +} + /** * cros_ec_register() - Register a new ChromeOS EC, using the provided inf= o. * @ec_dev: Device to register. @@ -221,6 +251,13 @@ int cros_ec_register(struct cros_ec_device *ec_dev) ec_dev->irq, err); goto exit; } + dev_dbg(dev, "IRQ: %i, wake_capable: %s\n", ec_dev->irq, + str_yes_no(ec_dev->irq_wake)); + if (ec_dev->irq_wake) { + err =3D enable_irq_for_wake(ec_dev); + if (err) + goto exit; + } } =20 /* Register a platform device for the main EC instance */ @@ -313,6 +350,8 @@ EXPORT_SYMBOL(cros_ec_register); */ void cros_ec_unregister(struct cros_ec_device *ec_dev) { + if (ec_dev->irq_wake) + disable_irq_for_wake(ec_dev); platform_device_unregister(ec_dev->pd); platform_device_unregister(ec_dev->ec); mutex_destroy(&ec_dev->lock); @@ -353,12 +392,6 @@ EXPORT_SYMBOL(cros_ec_suspend_prepare); =20 static void cros_ec_disable_irq(struct cros_ec_device *ec_dev) { - struct device *dev =3D ec_dev->dev; - if (device_may_wakeup(dev)) - ec_dev->wake_enabled =3D !enable_irq_wake(ec_dev->irq); - else - ec_dev->wake_enabled =3D false; - disable_irq(ec_dev->irq); ec_dev->suspended =3D true; } @@ -440,9 +473,6 @@ static void cros_ec_enable_irq(struct cros_ec_device *e= c_dev) ec_dev->suspended =3D false; enable_irq(ec_dev->irq); =20 - if (ec_dev->wake_enabled) - disable_irq_wake(ec_dev->irq); - /* * Let the mfd devices know about events that occur during * suspend. This way the clients know what to do with them. diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrom= e/cros_ec_lpc.c index f0f3d3d561572..0204593d7b1c9 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -48,6 +48,27 @@ struct lpc_driver_ops { =20 static struct lpc_driver_ops cros_ec_lpc_ops =3D { }; =20 +static const struct dmi_system_id untrusted_fw_irq_wake_capable[] =3D { + { + .ident =3D "Brya", + .matches =3D { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"), + }, + }, + { + .ident =3D "Brask", + .matches =3D { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brask"), + }, + }, + { } +}; + +static bool should_force_irq_wake_capable(void) +{ + return dmi_first_match(untrusted_fw_irq_wake_capable); +} + /* * A generic instance of the read function of struct lpc_driver_ops, used = for * the LPC EC. @@ -353,8 +374,9 @@ static int cros_ec_lpc_probe(struct platform_device *pd= ev) struct acpi_device *adev; acpi_status status; struct cros_ec_device *ec_dev; + struct resource r =3D {}; u8 buf[2] =3D {}; - int irq, ret; + int ret; =20 /* * The Framework Laptop (and possibly other non-ChromeOS devices) @@ -428,12 +450,16 @@ static int cros_ec_lpc_probe(struct platform_device *= pdev) * Some boards do not have an IRQ allotted for cros_ec_lpc, * which makes ENXIO an expected (and safe) scenario. */ - irq =3D platform_get_irq_optional(pdev, 0); - if (irq > 0) - ec_dev->irq =3D irq; - else if (irq !=3D -ENXIO) { - dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq); - return irq; + ret =3D platform_get_irq_resource_optional(pdev, 0, &r); + if (!ret) { + ec_dev->irq =3D r.start; + if (should_force_irq_wake_capable()) + ec_dev->irq_wake =3D true; + else + ec_dev->irq_wake =3D r.flags & IORESOURCE_IRQ_WAKECAPABLE; + } else if (ret !=3D -ENXIO) { + dev_err(dev, "couldn't retrieve IRQ number (%d)\n", ret); + return ret; } =20 ret =3D cros_ec_register(ec_dev); diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrom= e/cros_ec_spi.c index 3e88cc92e8192..102cdc3d1956d 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,7 @@ * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that * is sent when we want to turn off CS at the end of a transaction. * @high_pri_worker: Used to schedule high priority work. + * @irq_wake: Whether or not irq assertion should wake the system. */ struct cros_ec_spi { struct spi_device *spi; @@ -77,6 +79,7 @@ struct cros_ec_spi { unsigned int start_of_msg_delay; unsigned int end_of_msg_delay; struct kthread_worker *high_pri_worker; + bool irq_wake; }; =20 typedef int (*cros_ec_xfer_fn_t) (struct cros_ec_device *ec_dev, @@ -689,9 +692,10 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device = *ec_dev, return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_cmd_xfer_spi); } =20 -static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device= *dev) +static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi) { - struct device_node *np =3D dev->of_node; + struct spi_device *spi =3D ec_spi->spi; + struct device_node *np =3D spi->dev.of_node; u32 val; int ret; =20 @@ -702,6 +706,8 @@ static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec= _spi, struct device *dev) ret =3D of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val); if (!ret) ec_spi->end_of_msg_delay =3D val; + + ec_spi->irq_wake =3D spi->irq > 0 && of_property_present(np, "wakeup-sour= ce"); } =20 static void cros_ec_spi_high_pri_release(void *worker) @@ -754,12 +760,13 @@ static int cros_ec_spi_probe(struct spi_device *spi) return -ENOMEM; =20 /* Check for any DT properties */ - cros_ec_spi_dt_probe(ec_spi, dev); + cros_ec_spi_dt_probe(ec_spi); =20 spi_set_drvdata(spi, ec_dev); ec_dev->dev =3D dev; ec_dev->priv =3D ec_spi; ec_dev->irq =3D spi->irq; + ec_dev->irq_wake =3D ec_spi->irq_wake; ec_dev->cmd_xfer =3D cros_ec_cmd_xfer_spi; ec_dev->pkt_xfer =3D cros_ec_pkt_xfer_spi; ec_dev->phys_name =3D dev_name(&ec_spi->spi->dev); @@ -780,8 +787,6 @@ static int cros_ec_spi_probe(struct spi_device *spi) return err; } =20 - device_init_wakeup(&spi->dev, true); - return 0; } =20 diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chro= me/cros_ec_uart.c index 68d80559fddc2..5de346a078745 100644 --- a/drivers/platform/chrome/cros_ec_uart.c +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -69,6 +69,7 @@ struct response_info { * @serdev: serdev uart device we are connected to. * @baudrate: UART baudrate of attached EC device. * @flowcontrol: UART flowcontrol of attached device. + * @irq_wake: Whether or not irq assertion should wake the system. * @irq: Linux IRQ number of associated serial device. * @response: Response info passing between cros_ec_uart_pkt_xfer() * and cros_ec_uart_rx_bytes() @@ -77,6 +78,7 @@ struct cros_ec_uart { struct serdev_device *serdev; u32 baudrate; u8 flowcontrol; + bool irq_wake; u32 irq; struct response_info response; }; @@ -224,8 +226,10 @@ static int cros_ec_uart_resource(struct acpi_resource = *ares, void *data) static int cros_ec_uart_acpi_probe(struct cros_ec_uart *ec_uart) { int ret; + struct resource irqres; LIST_HEAD(resources); - struct acpi_device *adev =3D ACPI_COMPANION(&ec_uart->serdev->dev); + struct device *dev =3D &ec_uart->serdev->dev; + struct acpi_device *adev =3D ACPI_COMPANION(dev); =20 ret =3D acpi_dev_get_resources(adev, &resources, cros_ec_uart_resource, e= c_uart); if (ret < 0) @@ -234,12 +238,12 @@ static int cros_ec_uart_acpi_probe(struct cros_ec_uar= t *ec_uart) acpi_dev_free_resource_list(&resources); =20 /* Retrieve GpioInt and translate it to Linux IRQ number */ - ret =3D acpi_dev_gpio_irq_get(adev, 0); + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); if (ret < 0) return ret; =20 - ec_uart->irq =3D ret; - dev_dbg(&ec_uart->serdev->dev, "IRQ number %d\n", ec_uart->irq); + ec_uart->irq =3D irqres.start; + ec_uart->irq_wake =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; =20 return 0; } @@ -293,6 +297,7 @@ static int cros_ec_uart_probe(struct serdev_device *ser= dev) ec_dev->dev =3D dev; ec_dev->priv =3D ec_uart; ec_dev->irq =3D ec_uart->irq; + ec_dev->irq_wake =3D ec_uart->irq_wake; ec_dev->cmd_xfer =3D NULL; ec_dev->pkt_xfer =3D cros_ec_uart_pkt_xfer; ec_dev->din_size =3D sizeof(struct ec_host_response) + @@ -301,6 +306,7 @@ static int cros_ec_uart_probe(struct serdev_device *ser= dev) =20 serdev_device_set_client_ops(serdev, &cros_ec_uart_client_ops); =20 + /* Register a new cros_ec device */ return cros_ec_register(ec_dev); } =20 diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/pl= atform_data/cros_ec_proto.h index 8865e350c12a5..0fb2781b602d6 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -100,6 +100,7 @@ struct cros_ec_command { * @proto_version: The protocol version used for this device. * @priv: Private data. * @irq: Interrupt to use. + * @irq_wake: Whether or not irq assertion should wake the system. * @id: Device id. * @din: Input buffer (for data from EC). This buffer will always be * dword-aligned and include enough space for up to 7 word-alignment @@ -115,7 +116,6 @@ struct cros_ec_command { * performance advantage to using dword. * @din_size: Size of din buffer to allocate (zero to use static din). * @dout_size: Size of dout buffer to allocate (zero to use static dout). - * @wake_enabled: True if this device can wake the system from sleep. * @suspended: True if this device had been suspended. * @cmd_xfer: Send command to EC and get response. * Returns the number of bytes received if the communication @@ -169,11 +169,11 @@ struct cros_ec_device { u16 proto_version; void *priv; int irq; + bool irq_wake; u8 *din; u8 *dout; int din_size; int dout_size; - bool wake_enabled; bool suspended; int (*cmd_xfer)(struct cros_ec_device *ec, struct cros_ec_command *msg); --=20 2.43.0.472.g3155946c3a-goog