From nobody Fri Sep 20 05:55:50 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0857E18C07 for ; Tue, 2 Jan 2024 21:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="G/dP0i3f" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7ba8f139522so493859439f.1 for ; Tue, 02 Jan 2024 13:08:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1704229737; x=1704834537; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=17sTLQMT2wthv6A1NoR1+c8v3q9aB7n6ZqwH4HJJEV0=; b=G/dP0i3fJD0GauZiZhHTIMDLCqWdj0PmuwNf+pRtfpGVkOOxze1QGiQHgR8CJXkzQ0 M1eOOs20S4ff2isiJd9MsA1GwnWU0ZaMmDK6mVPekj7tWiRLCYxMiGDsFQg1tacsJCqK 7IJ10o14ZlZJ7KSVfc6p/qi8iz7hntt+wkNKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704229737; x=1704834537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=17sTLQMT2wthv6A1NoR1+c8v3q9aB7n6ZqwH4HJJEV0=; b=aLIqPqdsgdrJJ0YU0oKY7Gdou0Fjuwdf+OYFjZC6CSZ7kNxXLHd75KQbFCBLfyky2W RVJjaqGtlLgpRpgVcgeGBU9iC29tImMpa6RI7LKtXjVM3afH4RprdsnQkgCMJcmbpHkQ qw9VM1aZybyA7YmPZI4JHeahdXsQomIao34WtizGKcc7dyyh+XJRWIXCr3yzXaZ03eBl zWApVXSF9RkK6iinKGroLb8G3hVEtZgtVNZWfqukyyJoKzO/r4XoCsIKWHwITH2z8/ic xB9y7DqyqhtpI21oDL+oycmne8Rz1uf191oIpdi8lQ+aAC9itJnY8uBpqk8xLqkxctpO 2hzw== X-Gm-Message-State: AOJu0YyyYOCDvH0JC0SVxCu/fqnXwT65mcHuHQwuIt/WmtsDTeKhSbcg nJy+rDYVP7UezXnA3Tv0I4kTRdaoQ1dwy1jfnwnr/pXL+feI X-Google-Smtp-Source: AGHT+IG15JicEnj5m9+AYHheVx6jq8nHGYdtkF3GHDFBR8wkn+8r3oGMHOzGhdudxknyHLeWlKuuSA== X-Received: by 2002:a05:6602:19cf:b0:7ba:8706:3413 with SMTP id ba15-20020a05660219cf00b007ba87063413mr23570133iob.41.1704229737084; Tue, 02 Jan 2024 13:08:57 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id bo18-20020a056638439200b0046993034c91sm6956978jab.77.2024.01.02.13.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 13:08:56 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Sudeep Holla , AngeloGioacchino Del Regno , Rob Herring , Andy Shevchenko , Krzysztof Kozlowski , Konrad Dybcio , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Douglas Anderson , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v4 15/24] arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source Date: Tue, 2 Jan 2024 14:07:39 -0700 Message-ID: <20240102140734.v4.15.I7ea3f53272c9b7cd77633adfd18058ba443eed96@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20240102210820.2604667-1-markhas@chromium.org> References: <20240102210820.2604667-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by: Douglas Anderson Signed-off-by: Mark Hasemeyer --- Changes in v4: -Add Douglas's Reviewed-by tag from v2 review Changes in v3: -Update commit message to provide details of the motivation behind the change Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index 9ea6636125ad9..2ba4ea60cb147 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index ebae545c587c4..fbfac7534d3c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog