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[34.76.131.216]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c350900b0040d5aca25f1sm8615807wmq.17.2023.12.28.04.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Dec 2023 04:58:14 -0800 (PST) From: Tudor Ambarus To: peter.griffin@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, arnd@arndb.de, semen.protsenko@linaro.org Cc: andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, kernel-team@android.com, Tudor Ambarus Subject: [PATCH v2 05/12] tty: serial: samsung: set UPIO_MEM32 iotype for gs101 Date: Thu, 28 Dec 2023 12:57:58 +0000 Message-ID: <20231228125805.661725-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231228125805.661725-1-tudor.ambarus@linaro.org> References: <20231228125805.661725-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. Instead of specifying the reg-io-width =3D 4 everywhere, for each node, the requirement should be deduced from the compatible. Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. Update the uart info name to be GS101 specific in order to differentiate from the other exynos platforms. All the other settings are not changed. exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data because the iotype restriction is gs101 specific and there was no other user of exynos_fifoszdt_serial_drv_data. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: new patch drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_= tty.c index 97ce4b2424af..938127179acf 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos8= 50_serial_drv_data =3D { .fifosize =3D { 256, 64, 64, 64 }, }; =20 -/* - * Common drv_data struct for platforms that specify samsung,uart-fifosize= in - * device tree. - */ -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_dat= a =3D { - EXYNOS_COMMON_SERIAL_DRV_DATA(), +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data =3D { + .info =3D { + .name =3D "Google GS101 UART", + .type =3D TYPE_S3C6400, + .port_type =3D PORT_S3C6400, + .iotype =3D UPIO_MEM32, + .has_divslot =3D 1, + .rx_fifomask =3D S5PV210_UFSTAT_RXMASK, + .rx_fifoshift =3D S5PV210_UFSTAT_RXSHIFT, + .rx_fifofull =3D S5PV210_UFSTAT_RXFULL, + .tx_fifofull =3D S5PV210_UFSTAT_TXFULL, + .tx_fifomask =3D S5PV210_UFSTAT_TXMASK, + .tx_fifoshift =3D S5PV210_UFSTAT_TXSHIFT, + .def_clk_sel =3D S3C2410_UCON_CLKSEL0, + .num_clks =3D 1, + .clksel_mask =3D 0, + .clksel_shift =3D 0, + }, + .def_cfg =3D { + .ucon =3D S5PV210_UCON_DEFAULT, + .ufcon =3D S5PV210_UFCON_DEFAULT, + .has_fracval =3D 1, + }, + /* samsung,uart-fifosize must be specified in the device tree. */ .fifosize =3D { 0 }, }; =20 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data) #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data) -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data) +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data) =20 #else #define EXYNOS4210_SERIAL_DRV_DATA NULL #define EXYNOS5433_SERIAL_DRV_DATA NULL #define EXYNOS850_SERIAL_DRV_DATA NULL -#define EXYNOS_FIFOSZDT_DRV_DATA NULL +#define GS101_SERIAL_DRV_DATA NULL #endif =20 #ifdef CONFIG_ARCH_APPLE @@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial= _driver_ids[] =3D { .driver_data =3D (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA, }, { .name =3D "gs101-uart", - .driver_data =3D (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA, + .driver_data =3D (kernel_ulong_t)GS101_SERIAL_DRV_DATA, }, { }, }; @@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_matc= h[] =3D { { .compatible =3D "axis,artpec8-uart", .data =3D ARTPEC8_SERIAL_DRV_DATA }, { .compatible =3D "google,gs101-uart", - .data =3D EXYNOS_FIFOSZDT_DRV_DATA }, + .data =3D GS101_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); --=20 2.43.0.472.g3155946c3a-goog