From nobody Wed Dec 17 11:33:40 2025 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34DEC6AAD; Thu, 28 Dec 2023 10:48:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3BSAmIbD51892688, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3BSAmIbD51892688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 28 Dec 2023 18:48:18 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.32; Thu, 28 Dec 2023 18:48:18 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Thu, 28 Dec 2023 18:48:18 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2375.32 via Frontend Transport; Thu, 28 Dec 2023 18:48:17 +0800 From: Tzuyi Chang To: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , TY Chang Subject: [PATCH v5 2/2] Add GPIO support for Realtek DHC(Digital Home Center) RTD SoCs. Date: Thu, 28 Dec 2023 18:48:00 +0800 Message-ID: <20231228104800.24913-3-tychang@realtek.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231228104800.24913-1-tychang@realtek.com> References: <20231228104800.24913-1-tychang@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Content-Type: text/plain; charset="utf-8" This driver enables configuration of GPIO direction, GPIO values, GPIO debounce settings and handles GPIO interrupts. Signed-off-by: Tzuyi Chang Reviewed-by: Linus Walleij --- v4 to v5 change: 1. Add comment for the counter-intuitive number 31. 2. Convert to use cleanup API. 3. Convert to use module_platform_driver() macro. 4. Simplify some of the code as suggested in patch v4. 5. Add more description in the Kconfig. v3 to v4 change: 1. Remove the size check for the offset array. 2. Add the debounce callback to get values, register offsets and shifts= for each chip. 3. Conducted a review of the critical section, employing raw_spinlock_t= for locking purposes. 4. Use irqd_to_hwirq to get hwirq. 5. Add gpiochip_enable_irq/gpiochip_disable_irq to fulfill the immutabi= lity requirements. v2 to v3 change: 1. Remove generic compatible and use SoC-specific compatible instead. 2. Add the missing descriptions for the rtd_gpio_info structure members. 3. Assign gpio_chip fwnode. v1 to v2 change: 1. Remove legacy headers. 2. Transitioned from OF API to platform_device API. 3. Use u8 for the offset member within the rtd_gpio_info structure. 4. Record the size of each array within the rtd_gpio_info structure and implement checks to prevent out-of-bounds access. 5. Use GPIOLIB_IRQCHIP helpers to register interrupts. 6. Use dynamic allocation for GPIO base. --- drivers/gpio/Kconfig | 13 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rtd.c | 604 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 618 insertions(+) create mode 100644 drivers/gpio/gpio-rtd.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b3a133ed31ee..4c6bae8dc789 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -553,6 +553,19 @@ config GPIO_ROCKCHIP help Say yes here to support GPIO on Rockchip SoCs. =20 +config GPIO_RTD + tristate "Realtek DHC GPIO support" + depends on ARCH_REALTEK + default y + select GPIOLIB_IRQCHIP + help + This option enables support for GPIOs found on Realtek DHC(Digital + Home Center) SoCs family, including RTD1295, RTD1315E, RTD1319, + RTD1319D, RTD1395, RTD1619 and RTD1619B. + + Say yes here to support GPIO functionality and GPIO interrupt on + Realtek DHC SoCs. + config GPIO_SAMA5D2_PIOBU tristate "SAMA5D2 PIOBU GPIO support" depends on MFD_SYSCON diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index eb73b5d633eb..16bb40717e87 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -137,6 +137,7 @@ obj-$(CONFIG_GPIO_RDC321X) +=3D gpio-rdc321x.o obj-$(CONFIG_GPIO_REALTEK_OTTO) +=3D gpio-realtek-otto.o obj-$(CONFIG_GPIO_REG) +=3D gpio-reg.o obj-$(CONFIG_GPIO_ROCKCHIP) +=3D gpio-rockchip.o +obj-$(CONFIG_GPIO_RTD) +=3D gpio-rtd.o obj-$(CONFIG_ARCH_SA1100) +=3D gpio-sa1100.o obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) +=3D gpio-sama5d2-piobu.o obj-$(CONFIG_GPIO_SCH311X) +=3D gpio-sch311x.o diff --git a/drivers/gpio/gpio-rtd.c b/drivers/gpio/gpio-rtd.c new file mode 100644 index 000000000000..a7939bd0aa56 --- /dev/null +++ b/drivers/gpio/gpio-rtd.c @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC gpio driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTD_GPIO_DEBOUNCE_1US 0 +#define RTD_GPIO_DEBOUNCE_10US 1 +#define RTD_GPIO_DEBOUNCE_100US 2 +#define RTD_GPIO_DEBOUNCE_1MS 3 +#define RTD_GPIO_DEBOUNCE_10MS 4 +#define RTD_GPIO_DEBOUNCE_20MS 5 +#define RTD_GPIO_DEBOUNCE_30MS 6 + +/** + * struct rtd_gpio_info - Specific GPIO register information + * @name: GPIO device name + * @gpio_base: GPIO base number + * @num_gpios: The number of GPIOs + * @dir_offset: Offset for GPIO direction registers + * @dato_offset: Offset for GPIO data output registers + * @dati_offset: Offset for GPIO data input registers + * @ie_offset: Offset for GPIO interrupt enable registers + * @dp_offset: Offset for GPIO detection polarity registers + * @gpa_offset: Offset for GPIO assert interrupt status registers + * @gpda_offset: Offset for GPIO deassert interrupt status registers + * @deb_offset: Offset for GPIO debounce registers + * @deb_val: Register values representing the GPIO debounce time + * @get_deb_setval: Used to get the corresponding value for setting the de= bounce register + */ +struct rtd_gpio_info { + const char *name; + unsigned int gpio_base; + unsigned int num_gpios; + u8 *dir_offset; + u8 *dato_offset; + u8 *dati_offset; + u8 *ie_offset; + u8 *dp_offset; + u8 *gpa_offset; + u8 *gpda_offset; + u8 *deb_offset; + u8 *deb_val; + u8 (*get_deb_setval)(const struct rtd_gpio_info *info, + unsigned int offset, u8 deb_index, + u8 *reg_offset, u8 *shift); +}; + +struct rtd_gpio { + struct gpio_chip gpio_chip; + const struct rtd_gpio_info *info; + void __iomem *base; + void __iomem *irq_base; + unsigned int irqs[2]; + raw_spinlock_t lock; +}; + +static u8 rtd_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsign= ed int offset, + u8 deb_index, u8 *reg_offset, u8 *shift) +{ + *reg_offset =3D info->deb_offset[offset / 8]; + *shift =3D (offset % 8) * 4; + return info->deb_val[deb_index]; +} + +static u8 rtd1295_misc_gpio_get_deb_setval(const struct rtd_gpio_info *inf= o, unsigned int offset, + u8 deb_index, u8 *reg_offset, u8 *shift) +{ + *reg_offset =3D info->deb_offset[0]; + *shift =3D (offset % 8) * 4; + return info->deb_val[deb_index]; +} + +static u8 rtd1295_iso_gpio_get_deb_setval(const struct rtd_gpio_info *info= , unsigned int offset, + u8 deb_index, u8 *reg_offset, u8 *shift) +{ + *reg_offset =3D info->deb_offset[0]; + *shift =3D 0; + return info->deb_val[deb_index]; +} + +static const struct rtd_gpio_info rtd_iso_gpio_info =3D { + .name =3D "rtd_iso_gpio", + .gpio_base =3D 0, + .num_gpios =3D 82, + .dir_offset =3D (u8 []){ 0x0, 0x18, 0x2c }, + .dato_offset =3D (u8 []){ 0x4, 0x1c, 0x30 }, + .dati_offset =3D (u8 []){ 0x8, 0x20, 0x34 }, + .ie_offset =3D (u8 []){ 0xc, 0x24, 0x38 }, + .dp_offset =3D (u8 []){ 0x10, 0x28, 0x3c }, + .gpa_offset =3D (u8 []){ 0x8, 0xe0, 0x90 }, + .gpda_offset =3D (u8 []){ 0xc, 0xe4, 0x94 }, + .deb_offset =3D (u8 []){ 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c, + 0x60, 0x64, 0x68, 0x6c }, + .deb_val =3D (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 }, + .get_deb_setval =3D rtd_gpio_get_deb_setval, +}; + +static const struct rtd_gpio_info rtd1619_iso_gpio_info =3D { + .name =3D "rtd1619_iso_gpio", + .gpio_base =3D 0, + .num_gpios =3D 86, + .dir_offset =3D (u8 []){ 0x0, 0x18, 0x2c }, + .dato_offset =3D (u8 []){ 0x4, 0x1c, 0x30 }, + .dati_offset =3D (u8 []){ 0x8, 0x20, 0x34 }, + .ie_offset =3D (u8 []){ 0xc, 0x24, 0x38 }, + .dp_offset =3D (u8 []){ 0x10, 0x28, 0x3c }, + .gpa_offset =3D (u8 []){ 0x8, 0xe0, 0x90 }, + .gpda_offset =3D (u8 []){ 0xc, 0xe4, 0x94 }, + .deb_offset =3D (u8 []){ 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c, + 0x60, 0x64, 0x68, 0x6c }, + .deb_val =3D (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 }, + .get_deb_setval =3D rtd_gpio_get_deb_setval, +}; + +static const struct rtd_gpio_info rtd1395_iso_gpio_info =3D { + .name =3D "rtd1395_iso_gpio", + .gpio_base =3D 0, + .num_gpios =3D 57, + .dir_offset =3D (u8 []){ 0x0, 0x18 }, + .dato_offset =3D (u8 []){ 0x4, 0x1c }, + .dati_offset =3D (u8 []){ 0x8, 0x20 }, + .ie_offset =3D (u8 []){ 0xc, 0x24 }, + .dp_offset =3D (u8 []){ 0x10, 0x28 }, + .gpa_offset =3D (u8 []){ 0x8, 0xe0 }, + .gpda_offset =3D (u8 []){ 0xc, 0xe4 }, + .deb_offset =3D (u8 []){ 0x30, 0x34, 0x38, 0x3c, 0x40, 0x44, 0x48, 0x4c = }, + .deb_val =3D (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 }, + .get_deb_setval =3D rtd_gpio_get_deb_setval, +}; + +static const struct rtd_gpio_info rtd1295_misc_gpio_info =3D { + .name =3D "rtd1295_misc_gpio", + .gpio_base =3D 0, + .num_gpios =3D 101, + .dir_offset =3D (u8 []){ 0x0, 0x4, 0x8, 0xc }, + .dato_offset =3D (u8 []){ 0x10, 0x14, 0x18, 0x1c }, + .dati_offset =3D (u8 []){ 0x20, 0x24, 0x28, 0x2c }, + .ie_offset =3D (u8 []){ 0x30, 0x34, 0x38, 0x3c }, + .dp_offset =3D (u8 []){ 0x40, 0x44, 0x48, 0x4c }, + .gpa_offset =3D (u8 []){ 0x40, 0x44, 0xa4, 0xb8 }, + .gpda_offset =3D (u8 []){ 0x54, 0x58, 0xa8, 0xbc}, + .deb_offset =3D (u8 []){ 0x50 }, + .deb_val =3D (u8 []){ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }, + .get_deb_setval =3D rtd1295_misc_gpio_get_deb_setval, +}; + +static const struct rtd_gpio_info rtd1295_iso_gpio_info =3D { + .name =3D "rtd1295_iso_gpio", + .gpio_base =3D 101, + .num_gpios =3D 35, + .dir_offset =3D (u8 []){ 0x0, 0x18 }, + .dato_offset =3D (u8 []){ 0x4, 0x1c }, + .dati_offset =3D (u8 []){ 0x8, 0x20 }, + .ie_offset =3D (u8 []){ 0xc, 0x24 }, + .dp_offset =3D (u8 []){ 0x10, 0x28 }, + .gpa_offset =3D (u8 []){ 0x8, 0xe0 }, + .gpda_offset =3D (u8 []){ 0xc, 0xe4 }, + .deb_offset =3D (u8 []){ 0x14 }, + .deb_val =3D (u8 []){ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }, + .get_deb_setval =3D rtd1295_iso_gpio_get_deb_setval, +}; + +static int rtd_gpio_dir_offset(struct rtd_gpio *data, unsigned int offset) +{ + return data->info->dir_offset[offset / 32]; +} + +static int rtd_gpio_dato_offset(struct rtd_gpio *data, unsigned int offset) +{ + return data->info->dato_offset[offset / 32]; +} + +static int rtd_gpio_dati_offset(struct rtd_gpio *data, unsigned int offset) +{ + return data->info->dati_offset[offset / 32]; +} + +static int rtd_gpio_ie_offset(struct rtd_gpio *data, unsigned int offset) +{ + return data->info->ie_offset[offset / 32]; +} + +static int rtd_gpio_dp_offset(struct rtd_gpio *data, unsigned int offset) +{ + return data->info->dp_offset[offset / 32]; +} + + +static int rtd_gpio_gpa_offset(struct rtd_gpio *data, unsigned int offset) +{ + /* Each GPIO assert interrupt status register contains 31 GPIOs. */ + return data->info->gpa_offset[offset / 31]; +} + +static int rtd_gpio_gpda_offset(struct rtd_gpio *data, unsigned int offset) +{ + /* Each GPIO deassert interrupt status register contains 31 GPIOs. */ + return data->info->gpda_offset[offset / 31]; +} + +static int rtd_gpio_set_debounce(struct gpio_chip *chip, unsigned int offs= et, + unsigned int debounce) +{ + struct rtd_gpio *data =3D gpiochip_get_data(chip); + u8 deb_val, deb_index, reg_offset, shift; + unsigned int write_en; + u32 val; + + switch (debounce) { + case 1: + deb_index =3D RTD_GPIO_DEBOUNCE_1US; + break; + case 10: + deb_index =3D RTD_GPIO_DEBOUNCE_10US; + break; + case 100: + deb_index =3D RTD_GPIO_DEBOUNCE_100US; + break; + case 1000: + deb_index =3D RTD_GPIO_DEBOUNCE_1MS; + break; + case 10000: + deb_index =3D RTD_GPIO_DEBOUNCE_10MS; + break; + case 20000: + deb_index =3D RTD_GPIO_DEBOUNCE_20MS; + break; + case 30000: + deb_index =3D RTD_GPIO_DEBOUNCE_30MS; + break; + default: + return -ENOTSUPP; + } + + deb_val =3D data->info->get_deb_setval(data->info, offset, deb_index, &re= g_offset, &shift); + write_en =3D BIT(shift + 3); + val =3D (deb_val << shift) | write_en; + + guard(raw_spinlock_irqsave)(&data->lock); + writel_relaxed(val, data->base + reg_offset); + + return 0; +} + +static int rtd_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + int debounce; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + return gpiochip_generic_config(chip, offset, config); + case PIN_CONFIG_INPUT_DEBOUNCE: + debounce =3D pinconf_to_config_argument(config); + return rtd_gpio_set_debounce(chip, offset, debounce); + default: + return -ENOTSUPP; + } +} + +static void rtd_gpio_set(struct gpio_chip *chip, unsigned int offset, int = value) +{ + struct rtd_gpio *data =3D gpiochip_get_data(chip); + u32 mask =3D BIT(offset % 32); + int dato_reg_offset; + u32 val; + + dato_reg_offset =3D rtd_gpio_dato_offset(data, offset); + + guard(raw_spinlock_irqsave)(&data->lock); + + val =3D readl_relaxed(data->base + dato_reg_offset); + if (value) + val |=3D mask; + else + val &=3D ~mask; + writel_relaxed(val, data->base + dato_reg_offset); +} + +static int rtd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rtd_gpio *data =3D gpiochip_get_data(chip); + int dato_reg_offset =3D rtd_gpio_dato_offset(data, offset); + int dati_reg_offset =3D rtd_gpio_dati_offset(data, offset); + int dir_reg_offset =3D rtd_gpio_dir_offset(data, offset); + int dat_reg_offset; + u32 val; + + guard(raw_spinlock_irqsave)(&data->lock); + + val =3D readl_relaxed(data->base + dir_reg_offset); + dat_reg_offset =3D (val & BIT(offset % 32)) ? dato_reg_offset : dati_reg_= offset; + val =3D readl_relaxed(data->base + dat_reg_offset); + + return !!(val & BIT(offset % 32)); +} + +static int rtd_gpio_get_direction(struct gpio_chip *chip, unsigned int off= set) +{ + struct rtd_gpio *data =3D gpiochip_get_data(chip); + int reg_offset; + u32 val; + + reg_offset =3D rtd_gpio_dir_offset(data, offset); + val =3D readl_relaxed(data->base + reg_offset); + if (val & BIT(offset % 32)) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +} + +static int rtd_gpio_set_direction(struct gpio_chip *chip, unsigned int off= set, bool out) +{ + struct rtd_gpio *data =3D gpiochip_get_data(chip); + u32 mask =3D BIT(offset % 32); + int reg_offset; + u32 val; + + reg_offset =3D rtd_gpio_dir_offset(data, offset); + + guard(raw_spinlock_irqsave)(&data->lock); + + val =3D readl_relaxed(data->base + reg_offset); + if (out) + val |=3D mask; + else + val &=3D ~mask; + writel_relaxed(val, data->base + reg_offset); + + return 0; +} + +static int rtd_gpio_direction_input(struct gpio_chip *chip, unsigned int o= ffset) +{ + return rtd_gpio_set_direction(chip, offset, false); +} + +static int rtd_gpio_direction_output(struct gpio_chip *chip, unsigned int = offset, int value) +{ + rtd_gpio_set(chip, offset, value); + + return rtd_gpio_set_direction(chip, offset, true); +} + +static bool rtd_gpio_check_ie(struct rtd_gpio *data, int irq) +{ + int mask =3D BIT(irq % 32); + int ie_reg_offset; + u32 enable; + + ie_reg_offset =3D rtd_gpio_ie_offset(data, irq); + enable =3D readl_relaxed(data->base + ie_reg_offset); + + return enable & mask; +} + +static void rtd_gpio_irq_handle(struct irq_desc *desc) +{ + int (*get_reg_offset)(struct rtd_gpio *gpio, unsigned int offset); + struct rtd_gpio *data =3D irq_desc_get_handler_data(desc); + struct irq_domain *domain =3D data->gpio_chip.irq.domain; + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int irq =3D irq_desc_get_irq(desc); + unsigned long status; + int reg_offset, i, j; + unsigned int hwirq; + + if (irq =3D=3D data->irqs[0]) + get_reg_offset =3D &rtd_gpio_gpa_offset; + else if (irq =3D=3D data->irqs[1]) + get_reg_offset =3D &rtd_gpio_gpda_offset; + + chained_irq_enter(chip, desc); + + /* Each GPIO interrupt status register contains 31 GPIOs. */ + for (i =3D 0; i < data->info->num_gpios; i +=3D 31) { + reg_offset =3D get_reg_offset(data, i); + + /* + * Bit 0 is the write_en bit, bit 0 to 31 corresponds to 31 GPIOs. + * When bit 0 is set to 0, write 1 to the other bits to clear the status. + * When bit 0 is set to 1, write 1 to the other bits to set the status. + */ + status =3D readl_relaxed(data->irq_base + reg_offset); + status &=3D ~BIT(0); + writel_relaxed(status, data->irq_base + reg_offset); + + for_each_set_bit(j, &status, 32) { + hwirq =3D i + j - 1; + if (rtd_gpio_check_ie(data, hwirq)) { + int girq =3D irq_find_mapping(domain, hwirq); + u32 irq_type =3D irq_get_trigger_type(girq); + + if ((irq =3D=3D data->irqs[1]) && (irq_type !=3D IRQ_TYPE_EDGE_BOTH)) + break; + generic_handle_domain_irq(domain, hwirq); + } + } + } + + chained_irq_exit(chip, desc); +} + +static void rtd_gpio_enable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + /* Bit 0 is write_en and bit 1 to 31 is correspond to 31 GPIOs. */ + u32 clr_mask =3D BIT(hwirq % 31) << 1; + + u32 ie_mask =3D BIT(hwirq % 32); + int gpda_reg_offset; + int gpa_reg_offset; + int ie_reg_offset; + u32 val; + + ie_reg_offset =3D rtd_gpio_ie_offset(data, hwirq); + gpa_reg_offset =3D rtd_gpio_gpa_offset(data, hwirq); + gpda_reg_offset =3D rtd_gpio_gpda_offset(data, hwirq); + + gpiochip_enable_irq(gc, hwirq); + + guard(raw_spinlock_irqsave)(&data->lock); + + writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset); + writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset); + + val =3D readl_relaxed(data->base + ie_reg_offset); + val |=3D ie_mask; + writel_relaxed(val, data->base + ie_reg_offset); +} + +static void rtd_gpio_disable_irq(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 ie_mask =3D BIT(hwirq % 32); + int ie_reg_offset; + u32 val; + + ie_reg_offset =3D rtd_gpio_ie_offset(data, hwirq); + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + val =3D readl_relaxed(data->base + ie_reg_offset); + val &=3D ~ie_mask; + writel_relaxed(val, data->base + ie_reg_offset); + } + + gpiochip_disable_irq(gc, hwirq); +} + +static int rtd_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rtd_gpio *data =3D gpiochip_get_data(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u32 mask =3D BIT(hwirq % 32); + int dp_reg_offset; + bool polarity; + u32 val; + + dp_reg_offset =3D rtd_gpio_dp_offset(data, hwirq); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + polarity =3D 1; + break; + + case IRQ_TYPE_EDGE_FALLING: + polarity =3D 0; + break; + + case IRQ_TYPE_EDGE_BOTH: + polarity =3D 1; + break; + + default: + return -EINVAL; + } + + scoped_guard(raw_spinlock_irqsave, &data->lock) { + val =3D readl_relaxed(data->base + dp_reg_offset); + if (polarity) + val |=3D mask; + else + val &=3D ~mask; + writel_relaxed(val, data->base + dp_reg_offset); + } + + irq_set_handler_locked(d, handle_simple_irq); + + return 0; +} + +static const struct irq_chip rtd_gpio_irq_chip =3D { + .name =3D "rtd-gpio", + .irq_enable =3D rtd_gpio_enable_irq, + .irq_disable =3D rtd_gpio_disable_irq, + .irq_set_type =3D rtd_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE, +}; + +static int rtd_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct gpio_irq_chip *irq_chip; + struct rtd_gpio *data; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->irqs[0] =3D platform_get_irq(pdev, 0); + if (data->irqs[0] < 0) + return data->irqs[0]; + + data->irqs[1] =3D platform_get_irq(pdev, 1); + if (data->irqs[1] < 0) + return data->irqs[1]; + + data->info =3D device_get_match_data(dev); + if (!data->info) + return -EINVAL; + + raw_spin_lock_init(&data->lock); + + data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + data->irq_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(data->irq_base)) + return PTR_ERR(data->irq_base); + + data->gpio_chip.label =3D dev_name(dev); + data->gpio_chip.base =3D -1; + data->gpio_chip.ngpio =3D data->info->num_gpios; + data->gpio_chip.request =3D gpiochip_generic_request; + data->gpio_chip.free =3D gpiochip_generic_free; + data->gpio_chip.get_direction =3D rtd_gpio_get_direction; + data->gpio_chip.direction_input =3D rtd_gpio_direction_input; + data->gpio_chip.direction_output =3D rtd_gpio_direction_output; + data->gpio_chip.set =3D rtd_gpio_set; + data->gpio_chip.get =3D rtd_gpio_get; + data->gpio_chip.set_config =3D rtd_gpio_set_config; + data->gpio_chip.parent =3D dev; + + irq_chip =3D &data->gpio_chip.irq; + irq_chip->handler =3D handle_bad_irq; + irq_chip->default_type =3D IRQ_TYPE_NONE; + irq_chip->parent_handler =3D rtd_gpio_irq_handle; + irq_chip->parent_handler_data =3D data; + irq_chip->num_parents =3D 2; + irq_chip->parents =3D data->irqs; + + gpio_irq_chip_set_chip(irq_chip, &rtd_gpio_irq_chip); + + return devm_gpiochip_add_data(dev, &data->gpio_chip, data); +} + +static const struct of_device_id rtd_gpio_of_matches[] =3D { + { .compatible =3D "realtek,rtd1295-misc-gpio", .data =3D &rtd1295_misc_gp= io_info }, + { .compatible =3D "realtek,rtd1295-iso-gpio", .data =3D &rtd1295_iso_gpio= _info }, + { .compatible =3D "realtek,rtd1395-iso-gpio", .data =3D &rtd1395_iso_gpio= _info }, + { .compatible =3D "realtek,rtd1619-iso-gpio", .data =3D &rtd1619_iso_gpio= _info }, + { .compatible =3D "realtek,rtd1319-iso-gpio", .data =3D &rtd_iso_gpio_inf= o }, + { .compatible =3D "realtek,rtd1619b-iso-gpio", .data =3D &rtd_iso_gpio_in= fo }, + { .compatible =3D "realtek,rtd1319d-iso-gpio", .data =3D &rtd_iso_gpio_in= fo }, + { .compatible =3D "realtek,rtd1315e-iso-gpio", .data =3D &rtd_iso_gpio_in= fo }, + { } +}; +MODULE_DEVICE_TABLE(of, rtd_gpio_of_matches); + +static struct platform_driver rtd_gpio_platform_driver =3D { + .driver =3D { + .name =3D "gpio-rtd", + .of_match_table =3D rtd_gpio_of_matches, + }, + .probe =3D rtd_gpio_probe, +}; +module_platform_driver(rtd_gpio_platform_driver); + +MODULE_DESCRIPTION("Realtek DHC SoC gpio driver"); +MODULE_LICENSE("GPL v2"); --=20 2.43.0