From nobody Sat Dec 27 01:29:08 2025 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 500A96FA1 for ; Thu, 28 Dec 2023 01:42:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="HRrYqQ1M" Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-3bbc648bed4so789129b6e.3 for ; Wed, 27 Dec 2023 17:42:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1703727751; x=1704332551; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h+RheApEuJN9kaaLRvICyPNbTjOVIvY5kEzb7DbTZjA=; b=HRrYqQ1M7T0XagVlhzUysvM9h33SsHQx78QCtwD64qF9ARhh6CyP41vp/N/j33EgIU mNz6+to30yKSSb20LzoHL2cPnBQD8Hc2n2kxzurBvj0nDOYXzQqmMoq4or1RxJXI7jty lGlV3AMjF4i87DGQRnIciQRHVy3TlSz+aBC1sBA0cd6Dxq2kwU9cEqdhklsKaL7Sgw0C nTj8VqriRvejZYFmTOxTOpjNwfm2Sj5TNf0N6+7dGXPqcFamMPQyJnxsott79G3oAGdl FP4CNfENvZz6Ki9qM/3kZ4rEurusCICr72v/yheVsCFvxj5reqYatDQ8gDYbwMreoMn+ dOdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703727751; x=1704332551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h+RheApEuJN9kaaLRvICyPNbTjOVIvY5kEzb7DbTZjA=; b=BR8U5i6huZ1yvleX2OogpmSm2/2o/nEskffRezPqW1AkzDZCH7vLY62z/Mg0ZdP/Tv 0TyKT9+4IU8lL0HSxPd3xQ3PhO5dxaYKWVrPIiSuIFAcjMh4gz4LQrFzJ4PmAISpNjNU tPG5ilJPmMnmbBT8QcDmHXdqu72NpDu5Tqgs+IBAxmUJuOqmuOv+/+Gfj/E2XNBrgzmt 9wtX3M2Kndha7cBZZrPKgWMOpBPJ5SZqUAJ+Zni6bziiV2xPro7LYvACzwI67puQ36SQ +B2q17Rkr2PsloPrWOxFkfa/Lhrj0KmV6vl11hnLEk9tLgRcMkJ3CqjUPuEnryn1ybN1 8iVg== X-Gm-Message-State: AOJu0YzzD0AKZNSbltuz6W3GEPvc8zpu57LAElh74QCnpHrcTWHu6wHb ZoQJbR/eP5hiQ1L3A76FlqNGUbQODP42rA== X-Google-Smtp-Source: AGHT+IFlYg0OgNqHd1istrtt2UTcBedE87vqCIVNtp3f0Z5ptnzM2zYPRY9OCADmqV6QIO1pVX8ZnQ== X-Received: by 2002:a05:6808:6544:b0:3bb:b063:1afe with SMTP id fn4-20020a056808654400b003bbb0631afemr7698441oib.113.1703727751522; Wed, 27 Dec 2023 17:42:31 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id g24-20020aa78758000000b006d49ed3effasm7335440pfo.63.2023.12.27.17.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 17:42:31 -0800 (PST) From: Samuel Holland To: linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, x86@kernel.org, linux-riscv@lists.infradead.org, Christoph Hellwig Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, linux-arch@vger.kernel.org, Samuel Holland , WANG Xuerui Subject: [PATCH v2 07/14] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Date: Wed, 27 Dec 2023 17:41:57 -0800 Message-ID: <20231228014220.3562640-8-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231228014220.3562640-1-samuel.holland@sifive.com> References: <20231228014220.3562640-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LoongArch already provides kernel_fpu_begin() and kernel_fpu_end() in asm/fpu.h, so it only needs to add kernel_fpu_available() and export the CFLAGS adjustments. Acked-by: WANG Xuerui Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v1) arch/loongarch/Kconfig | 1 + arch/loongarch/Makefile | 5 ++++- arch/loongarch/include/asm/fpu.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index ee123820a476..65d4475565b8 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -15,6 +15,7 @@ config LOONGARCH select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_KCOV + select ARCH_HAS_KERNEL_FPU_SUPPORT if CPU_HAS_FPU select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PTE_SPECIAL diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile index 4ba8d67ddb09..1afe28feaba5 100644 --- a/arch/loongarch/Makefile +++ b/arch/loongarch/Makefile @@ -25,6 +25,9 @@ endif 32bit-emul =3D elf32loongarch 64bit-emul =3D elf64loongarch =20 +CC_FLAGS_FPU :=3D -mfpu=3D64 +CC_FLAGS_NO_FPU :=3D -msoft-float + ifdef CONFIG_DYNAMIC_FTRACE KBUILD_CPPFLAGS +=3D -DCC_USING_PATCHABLE_FUNCTION_ENTRY CC_FLAGS_FTRACE :=3D -fpatchable-function-entry=3D2 @@ -46,7 +49,7 @@ ld-emul =3D $(64bit-emul) cflags-y +=3D -mabi=3Dlp64s endif =20 -cflags-y +=3D -pipe -msoft-float +cflags-y +=3D -pipe $(CC_FLAGS_NO_FPU) LDFLAGS_vmlinux +=3D -static -n -nostdlib =20 # When the assembler supports explicit relocation hint, we must use it. diff --git a/arch/loongarch/include/asm/fpu.h b/arch/loongarch/include/asm/= fpu.h index c2d8962fda00..3177674228f8 100644 --- a/arch/loongarch/include/asm/fpu.h +++ b/arch/loongarch/include/asm/fpu.h @@ -21,6 +21,7 @@ =20 struct sigcontext; =20 +#define kernel_fpu_available() cpu_has_fpu extern void kernel_fpu_begin(void); extern void kernel_fpu_end(void); =20 --=20 2.42.0