From nobody Wed Nov 13 02:35:20 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 347806FBB; Wed, 27 Dec 2023 04:44:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="V/fDrH2i" Received: by mail.gandi.net (Postfix) with ESMTPSA id 0DB2C1C0003; Wed, 27 Dec 2023 04:44:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652263; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WfepgJ+5VGun3NQSb2IbwDYCOaF7C2dAvMgwMkGGlWA=; b=V/fDrH2iuylFWTdTg09rJ7ZzfilAQy2/LEVWjzM61UgEiM7ESgAJcn4HX91JaYXyZr19NQ /w53+57UQObJsiGBLRVAjWIKhDoj90rgEF7U30b1WlAxZwqlYF5HcMLv4JUZxZ0EjqhwGr JFehGf7A3586FeaflLx/skr/+2xPVzJRbuthx2nBv+9+4WduVjxLSPA4MdVyGGQwzivgzM vgo4v8u9YUY/MiXehk6yRf+YdfZhpV39pQKv2OS9XSORVzZgHV8U6/KSgMg1D7+ecSufwE fQm8WxSZw+8j8/0yJ4k3vWqvXCT4LW0Rs4ElVqmo4SIrpXbgPG+ZIiiREYfSuA== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 4/7] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Wed, 27 Dec 2023 07:43:44 +0300 Message-Id: <20231227044347.107291-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch on the MT7988 SoC. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ab9b291c7a5f..558784f830c2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2520,12 +2520,16 @@ static void mt7530_mac_port_get_caps(struct dsa_swi= tch *ds, int port, struct phylink_config *config) { switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + /* Port 5 which can be used as a CPU port supports rgmii with delays, + * mii, and gmii. + */ + case 5: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2533,7 +2537,8 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 6: /* 1st cpu port */ + /* Port 6 which can be used as a CPU port supports rgmii and trgmii. */ + case 6: __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2548,19 +2553,24 @@ static void mt7531_mac_port_get_caps(struct dsa_swi= tch *ds, int port, struct mt7530_priv *priv =3D ds->priv; =20 switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + /* Port 5 which can be used as a CPU port supports rgmii with delays on + * MT7531BE, sgmii/802.3z on MT7531AE. + */ + case 5: if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; =20 - case 6: /* 1st cpu port supports sgmii/8023z only */ + /* Port 6 which can be used as a CPU port supports sgmii/802.3z. */ + case 6: __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2579,11 +2589,13 @@ static void mt7988_mac_port_get_caps(struct dsa_swi= tch *ds, int port, phy_interface_zero(config->supported_interfaces); =20 switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; =20 + /* Port 6 which can be used as a CPU port is an internal 10G port. */ case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); @@ -2747,12 +2759,12 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, in= t port, unsigned int mode, u32 mcr_cur, mcr_new; =20 switch (port) { - case 0 ... 4: /* Internal phy */ + case 0 ... 4: if (state->interface !=3D PHY_INTERFACE_MODE_GMII && state->interface !=3D PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: if (priv->p5_interface =3D=3D state->interface) break; =20 @@ -2762,7 +2774,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p5_intf_sel !=3D P5_DISABLED) priv->p5_interface =3D state->interface; break; - case 6: /* 1st cpu port */ + case 6: if (priv->p6_interface =3D=3D state->interface) break; =20 --=20 2.40.1