From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38E1346B8; Wed, 27 Dec 2023 04:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="kx6c4ABZ" Received: by mail.gandi.net (Postfix) with ESMTPSA id 07E4F1C0003; Wed, 27 Dec 2023 04:44:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652249; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=icw9vOVwt7dw4ced30DqL2oi7ni+F+KZa3W/XTt3JM4=; b=kx6c4ABZ3oirOhfT2Cqv+0E3TLx0ftm3rRd0XB4uIp8sMUsTWk7Kn80tKCcODWV3NdaDtI twZ8uldX/Mt3+pJnZDK7DKCrljg2cAxA4Kq/QAg7HLPYQ0pRmZCev2hacMqFBKmR8lSsAp 7n3MQRhHhdBVRqXQmbSw7x83SDnGIIKfZGYi/batAMrWpPI/DeaFCY1QAVxLKMoioXbmcA oKubanng0GHjRotp5SsO5qV6kzv8xmg9mgq8EHT9pURIYLtI0ZrkHCjUHm09Ygu8di6D8H VGxfoym3bYv9NNbe5tAlHAC9Fvu0JgvNMIz9HykG0N1FcXZCtOyBoXAiyUQ4hg== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 1/7] net: dsa: mt7530: always trap frames to active CPU port on MT7530 Date: Wed, 27 Dec 2023 07:43:41 +0300 Message-Id: <20231227044347.107291-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap frames to, regardless of the affinity of the inbound user port. When multiple CPU ports are in use, if the DSA conduit interface is down, trapped frames won't be passed to the conduit interface. To make trapping frames work including this case, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT field to the numerically smallest CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add a comment to explain frame trapping for this switch. Currently, the driver doesn't support the use of multiple CPU ports so this is not necessarily a bug fix. Suggested-by: Vladimir Oltean Suggested-by: Russell King (Oracle) Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 391c4dbdff42..436d5c311be0 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1035,10 +1035,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); =20 - /* Set CPU port number */ - if (priv->id =3D=3D ID_MT7530 || priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that * is affine to the inbound user port. @@ -3075,6 +3071,38 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 +static void +mt753x_conduit_state_change(struct dsa_switch *ds, + const struct net_device *conduit, + bool operational) +{ + struct dsa_port *cpu_dp =3D conduit->dsa_ptr; + struct mt7530_priv *priv =3D ds->priv; + u8 mask; + int val =3D 0; + + /* Set the CPU port to trap frames to for MT7530. Trapped frames will be + * forwarded to the numerically smallest CPU port which the DSA conduit + * interface its affine to is up. + */ + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) + return; + + mask =3D BIT(cpu_dp->index); + + if (operational) + priv->active_cpu_ports |=3D mask; + else + priv->active_cpu_ports &=3D ~mask; + + if (priv->active_cpu_ports) + val =3D + CPU_EN | + CPU_PORT(__ffs((unsigned long)priv->active_cpu_ports)); + + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) { return 0; @@ -3130,6 +3158,7 @@ const struct dsa_switch_ops mt7530_switch_ops =3D { .phylink_mac_link_up =3D mt753x_phylink_mac_link_up, .get_mac_eee =3D mt753x_get_mac_eee, .set_mac_eee =3D mt753x_set_mac_eee, + .conduit_state_change =3D mt753x_conduit_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 17e42d30fff4..ebfb3a7acfcd 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -760,6 +760,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -786,6 +787,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + u8 active_cpu_ports; }; =20 struct mt7530_hw_vlan_entry { --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C404D569F; Wed, 27 Dec 2023 04:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="BB7iWsgu" Received: by mail.gandi.net (Postfix) with ESMTPSA id AE4CA1C0004; Wed, 27 Dec 2023 04:44:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652254; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F4rNKyLbk8MWNjAsn+rEBH47i5DIeKuQk4GsWa0qbg0=; b=BB7iWsgukbu4+am4cCFJNsqTP5daUDg0bMF3JB+lzH1TMEfof5B5/SGSPGZQA5OaGm6wgo SuxD18CFoHKb+f+TDidTXl2Q/PsXV8W3w++1rEQsMo4IDk0M6QuDoE+eMRPlfLCK0XuKot tWzmVY4YT1Qqnd7oojKifhobn+NY0UatVVMEr45mP6GmkU3QOmE00v8GvjMwQlewHo99+q Td2H+2PI364VLJgN9ZF9yvinJ3d+ARicyiCtYIfS1mbv0AXg6wqeZb4Oye234ss1yiOyTA EVpxA0jhe6PxF766mzCRtLeWaN2uoWeEUb+i6RrmbJCeTAUJ36TRrFq0q9tLvQ== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 2/7] net: dsa: mt7530: use p5_interface_select as data type for p5_intf_sel Date: Wed, 27 Dec 2023 07:43:42 +0300 Message-Id: <20231227044347.107291-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com Use the p5_interface_select enumeration as the data type for the p5_intf_sel field. This ensures p5_intf_sel can only take the values defined in the p5_interface_select enumeration. Remove the explicit assignment of 0 to P5_DISABLED as the first enum item is automatically assigned 0. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index ebfb3a7acfcd..9cbf18efa416 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -683,7 +683,7 @@ struct mt7530_port { =20 /* Port 5 interface select definitions */ enum p5_interface_select { - P5_DISABLED =3D 0, + P5_DISABLED, P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, @@ -776,7 +776,7 @@ struct mt7530_priv { bool mcm; phy_interface_t p6_interface; phy_interface_t p5_interface; - unsigned int p5_intf_sel; + enum p5_interface_select p5_intf_sel; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3729863D6; Wed, 27 Dec 2023 04:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="NFJbNk5h" Received: by mail.gandi.net (Postfix) with ESMTPSA id 515561C0002; Wed, 27 Dec 2023 04:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J+ex37yFdAPrDz0ymYAcjESW8NARVuInLRjbup1ig0M=; b=NFJbNk5hnjCKEh/ud3uNd4am+vy94EZtX0f5LdkhfxGL5aZrcG3WGWfN/RupHmaK0SNxsS xtbXItQrV8V8KYlsve4fh/3HG+gscJiHS22seVViA+vjhnLiTtGcsoRBBE5ohbDap53fSC hMpXv2v4WFScCOJmVxUuzzh3LiOCIDfhx3hfQaMZrgN7Uxb5aF28rgwBXeFqPyKN3KJsQr 5Cjugmp2lV2p/jUoH8yqTR14dBzvCxUyhjqOqBPq0YOr1MW2jiw1KGtuScWnvWMJ9Pug/8 jRa8iqDp0+O8G5B32YHrzYEEN3C+IMl/P7Mj9GvKH6L9NgTDXuxSXxpGE8LLxA== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 3/7] net: dsa: mt7530: store port 5 SGMII capability of MT7531 Date: Wed, 27 Dec 2023 07:43:43 +0300 Message-Id: <20231227044347.107291-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com Introduce the p5_sgmii field to store the information for whether port 5 has got SGMII or not. Instead of reading the MT7531_TOP_SIG_SR register multiple times, the register will be read once and the value will be stored on the p5_sgmii field. This saves unnecessary reads of the register. Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the switch is identified. Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the information. Address the code where mt7531_dual_sgmii_supported() is used. Get rid of mt7531_is_rgmii_port() which just prints the opposite of priv->p5_sgmii. Instead of calling mt7531_pll_setup() then returning, do not call it if port 5 is SGMII. Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to represent the mode that port 5 is being used in, not the hardware information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if port 5 is not dsa_is_unused_port(). Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530-mdio.c | 7 ++--- drivers/net/dsa/mt7530.c | 48 ++++++++++++----------------------- drivers/net/dsa/mt7530.h | 6 +++-- 3 files changed, 22 insertions(+), 39 deletions(-) diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c index 088533663b83..fa3ee85a99c1 100644 --- a/drivers/net/dsa/mt7530-mdio.c +++ b/drivers/net/dsa/mt7530-mdio.c @@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus =3D { }; =20 static int -mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii) +mt7531_create_sgmii(struct mt7530_priv *priv) { struct regmap_config *mt7531_pcs_config[2] =3D {}; struct phylink_pcs *pcs; struct regmap *regmap; int i, ret =3D 0; =20 - /* MT7531AE has two SGMII units for port 5 and port 6 - * MT7531BE has only one SGMII unit for port 6 - */ - for (i =3D dual_sgmii ? 0 : 1; i < 2; i++) { + for (i =3D priv->p5_sgmii ? 0 : 1; i < 2; i++) { mt7531_pcs_config[i] =3D devm_kzalloc(priv->dev, sizeof(struct regmap_config), GFP_KERNEL); diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 436d5c311be0..ab9b291c7a5f 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interf= ace_t interface) return 0; } =20 -static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) -{ - u32 val; - - val =3D mt7530_read(priv, MT7531_TOP_SIG_SR); - - return (val & PAD_DUAL_SGMII_EN) !=3D 0; -} - static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *priv) u32 xtal; u32 val; =20 - if (mt7531_dual_sgmii_supported(priv)) - return; - val =3D mt7530_read(priv, MT7531_CREV); top_sig =3D mt7530_read(priv, MT7531_TOP_SIG_SR); hwstrap =3D mt7530_read(priv, MT7531_HWTRAP); @@ -920,8 +908,6 @@ static const char *p5_intf_modes(unsigned int p5_interf= ace) return "PHY P4"; case P5_INTF_SEL_GMAC5: return "GMAC5"; - case P5_INTF_SEL_GMAC5_SGMII: - return "GMAC5_SGMII"; default: return "unknown"; } @@ -2470,6 +2456,12 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } =20 + /* MT7531AE has got two SGMII units. One for port 5, one for port 6. + * MT7531BE has got only one SGMII unit which is for port 6. + */ + val =3D mt7530_read(priv, MT7531_TOP_SIG_SR); + priv->p5_sgmii =3D !!(val & PAD_DUAL_SGMII_EN); + /* all MACs must be forced link-down before sw reset */ for (i =3D 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); @@ -2479,21 +2471,18 @@ mt7531_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); =20 - mt7531_pll_setup(priv); - - if (mt7531_dual_sgmii_supported(priv)) { - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5_SGMII; - + if (!priv->p5_sgmii) { + mt7531_pll_setup(priv); + } else { /* Let ds->user_mii_bus be able to access external phy. */ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, MT7531_EXT_P_MDC_11); mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, MT7531_EXT_P_MDIO_12); - } else { - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; } - dev_dbg(ds->dev, "P5 support %s interface\n", - p5_intf_modes(priv->p5_intf_sel)); + + if (!dsa_is_unused_port(ds, 5)) + priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; =20 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); @@ -2553,11 +2542,6 @@ static void mt7530_mac_port_get_caps(struct dsa_swit= ch *ds, int port, } } =20 -static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) -{ - return (port =3D=3D 5) && (priv->p5_intf_sel !=3D P5_INTF_SEL_GMAC5_SGMII= ); -} - static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -2570,7 +2554,7 @@ static void mt7531_mac_port_get_caps(struct dsa_switc= h *ds, int port, break; =20 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ - if (mt7531_is_rgmii_port(priv, port)) { + if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } @@ -2637,7 +2621,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *pri= v, u32 port, { u32 val; =20 - if (!mt7531_is_rgmii_port(priv, port)) { + if (priv->p5_sgmii) { dev_err(priv->dev, "RGMII mode is not available for port %d\n", port); return -EINVAL; @@ -2881,7 +2865,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int por= t) =20 switch (port) { case 5: - if (mt7531_is_rgmii_port(priv, port)) + if (!priv->p5_sgmii) interface =3D PHY_INTERFACE_MODE_RGMII; else interface =3D PHY_INTERFACE_MODE_2500BASEX; @@ -3033,7 +3017,7 @@ mt753x_setup(struct dsa_switch *ds) mt7530_free_irq_common(priv); =20 if (priv->create_sgmii) { - ret =3D priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); + ret =3D priv->create_sgmii(priv); if (ret && priv->irq) mt7530_free_irq(priv); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 9cbf18efa416..80060cc740d2 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -687,7 +687,6 @@ enum p5_interface_select { P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, - P5_INTF_SEL_GMAC5_SGMII, }; =20 struct mt7530_priv; @@ -756,6 +755,8 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN @@ -777,6 +778,7 @@ struct mt7530_priv { phy_interface_t p6_interface; phy_interface_t p5_interface; enum p5_interface_select p5_intf_sel; + bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; @@ -786,7 +788,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; - int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + int (*create_sgmii)(struct mt7530_priv *priv); u8 active_cpu_ports; }; =20 --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 347806FBB; Wed, 27 Dec 2023 04:44:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="V/fDrH2i" Received: by mail.gandi.net (Postfix) with ESMTPSA id 0DB2C1C0003; Wed, 27 Dec 2023 04:44:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652263; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WfepgJ+5VGun3NQSb2IbwDYCOaF7C2dAvMgwMkGGlWA=; b=V/fDrH2iuylFWTdTg09rJ7ZzfilAQy2/LEVWjzM61UgEiM7ESgAJcn4HX91JaYXyZr19NQ /w53+57UQObJsiGBLRVAjWIKhDoj90rgEF7U30b1WlAxZwqlYF5HcMLv4JUZxZ0EjqhwGr JFehGf7A3586FeaflLx/skr/+2xPVzJRbuthx2nBv+9+4WduVjxLSPA4MdVyGGQwzivgzM vgo4v8u9YUY/MiXehk6yRf+YdfZhpV39pQKv2OS9XSORVzZgHV8U6/KSgMg1D7+ecSufwE fQm8WxSZw+8j8/0yJ4k3vWqvXCT4LW0Rs4ElVqmo4SIrpXbgPG+ZIiiREYfSuA== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 4/7] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Wed, 27 Dec 2023 07:43:44 +0300 Message-Id: <20231227044347.107291-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch on the MT7988 SoC. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ab9b291c7a5f..558784f830c2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2520,12 +2520,16 @@ static void mt7530_mac_port_get_caps(struct dsa_swi= tch *ds, int port, struct phylink_config *config) { switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + /* Port 5 which can be used as a CPU port supports rgmii with delays, + * mii, and gmii. + */ + case 5: phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2533,7 +2537,8 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 6: /* 1st cpu port */ + /* Port 6 which can be used as a CPU port supports rgmii and trgmii. */ + case 6: __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2548,19 +2553,24 @@ static void mt7531_mac_port_get_caps(struct dsa_swi= tch *ds, int port, struct mt7530_priv *priv =3D ds->priv; =20 switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + /* Port 5 which can be used as a CPU port supports rgmii with delays on + * MT7531BE, sgmii/802.3z on MT7531AE. + */ + case 5: if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; =20 - case 6: /* 1st cpu port supports sgmii/8023z only */ + /* Port 6 which can be used as a CPU port supports sgmii/802.3z. */ + case 6: __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2579,11 +2589,13 @@ static void mt7988_mac_port_get_caps(struct dsa_swi= tch *ds, int port, phy_interface_zero(config->supported_interfaces); =20 switch (port) { - case 0 ... 4: /* Internal phy */ + /* Internal PHY */ + case 0 ... 4: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; =20 + /* Port 6 which can be used as a CPU port is an internal 10G port. */ case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); @@ -2747,12 +2759,12 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, in= t port, unsigned int mode, u32 mcr_cur, mcr_new; =20 switch (port) { - case 0 ... 4: /* Internal phy */ + case 0 ... 4: if (state->interface !=3D PHY_INTERFACE_MODE_GMII && state->interface !=3D PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: if (priv->p5_interface =3D=3D state->interface) break; =20 @@ -2762,7 +2774,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p5_intf_sel !=3D P5_DISABLED) priv->p5_interface =3D state->interface; break; - case 6: /* 1st cpu port */ + case 6: if (priv->p6_interface =3D=3D state->interface) break; =20 --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56167491; Wed, 27 Dec 2023 04:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="pbfdb9Zc" Received: by mail.gandi.net (Postfix) with ESMTPSA id AFD961C0005; Wed, 27 Dec 2023 04:44:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652268; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=65dnSrXOzOWi1yBmaxCyl5uIl8FJyuseOOIh7XCp6Nw=; b=pbfdb9ZckIq0GiF6ZQXcoPL9NYz5KTp/akQy1oM+OAntJ30kQlZiw6pwN+X4dsC+9U3YtF J71g4J37jWowhZ72DE0O6YwTyypqsGvP242XbLs2av7OJG7lEXCrdqQj6PhyAZOIB+0IE/ 9s0yxYbwgx9oyZQWhdGuDMPbfdT3pcgS36qQwzyFVFRkXlMLZhOa6UnHZoA0iZirn8L0Ps P9326Uh6Ftrxakq3sSrah0a9eyZFdij23CtsqlbSKonkhP82O00fuKd5zW7LeJJwqBMmql NJwSb8oLh4a85qBLryil8hdemUvaAYomlzScItjvrj7E90QAM4VJ45yU947Qsg== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 5/7] net: dsa: mt7530: improve code path for setting up port 5 Date: Wed, 27 Dec 2023 07:43:45 +0300 Message-Id: <20231227044347.107291-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5 is used as a CPU, DSA, or user port, mt7530_setup_port5() from mt753x_phylink_mac_config() won't run. That is because priv->p5_interface set on mt7530_setup_port5() will match state->interface on mt753x_phylink_mac_config() which will stop running mt7530_setup_port5() again. Therefore, mt7530_setup_port5() will never run from mt753x_phylink_mac_config(). Address this by not running mt7530_setup_port5() from mt7530_setup() if port 5 is used as a CPU, DSA, or user port. This driver isn't in the dsa_switches_apply_workarounds[] array so phylink will always be present. To keep the cases where port 5 isn't controlled by phylink working as before, preserve the mt7530_setup_port5() call from mt7530_setup(). Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when "priv" is allocated. Move setting the interface to a more specific location. It's supposed to be overwritten if PHY muxing is detected. Improve the comment which explains the process. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 558784f830c2..bf6c59ecc489 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2308,16 +2308,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; =20 /* Setup port 5 */ - priv->p5_intf_sel =3D P5_DISABLED; - interface =3D PHY_INTERFACE_MODE_NA; - if (!dsa_is_unused_port(ds, 5)) { priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; - ret =3D of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); - if (ret && ret !=3D -ENODEV) - return ret; } else { - /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. + * Set priv->p5_intf_sel to the appropriate value if PHY muxing + * is detected. + */ + interface =3D PHY_INTERFACE_MODE_NA; + for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2348,6 +2347,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } + + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB @@ -2358,8 +2359,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ =20 - mt7530_setup_port5(ds, interface); - /* Flush the FDB table */ ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FC29D26B; Wed, 27 Dec 2023 04:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="O+NbHwlQ" Received: by mail.gandi.net (Postfix) with ESMTPSA id 62E1D1C0006; Wed, 27 Dec 2023 04:44:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Yq8FPR2LuMZyALJszWpCeHHckLAPDv/7+vYZcgFAtMY=; b=O+NbHwlQGumS7TsEOQr9BI9W/qAdYrT25uhKxHnbDp/6iBiFPtfRnlV/0F6b1nbfwhTWoT u2vYueKcYpUpw5Pr39+fRIlu4PyumjW/2rRanqAFAqojNwUfDFT1L1ll4wneNf83ZtLcsn 736eO/i5HT/mjys/KN8ZHI4LtHXm99iy6woUe/odmouV4neBPhbcp+UEB6e8p8n/ZquCqQ nO9++Mx8uADhqjY7UIKNJUfzVCxpWxckEZw1E9FRpE4bcmMOWVRpjHyO0LIjPcK6REUjof EJmTqMesQ05kZdaNsk05SoOeiQER89KrSOAhZhjeqoQLs8Md98z6maOdzCnx6g== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 6/7] net: dsa: mt7530: do not set priv->p5_interface on mt7530_setup_port5() Date: Wed, 27 Dec 2023 07:43:46 +0300 Message-Id: <20231227044347.107291-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com priv->p5_interface and priv->p6_interface are for use on the MT7531 switch. They prevent the CPU ports of MT7531 to be configured again. They are useless for MT7530. Therefore, remove setting priv->p5_interface for MT7530. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index bf6c59ecc489..07c5f1c6d036 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -978,8 +978,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, intf_sel=3D%s, phy-mode=3D%s\n= ", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); =20 - priv->p5_interface =3D interface; - unlock_exit: mutex_unlock(&priv->reg_mutex); } --=20 2.40.1 From nobody Thu Nov 14 05:05:39 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BDF0EAFD; Wed, 27 Dec 2023 04:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arinc9.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arinc9.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=arinc9.com header.i=@arinc9.com header.b="ES/9BjMk" Received: by mail.gandi.net (Postfix) with ESMTPSA id 0DEED1C0007; Wed, 27 Dec 2023 04:44:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1703652278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YCZIbkTLfmiSszqRUWdE3uv72vBPQhPeE1uqn8XXA8k=; b=ES/9BjMkXaCK3b66k00HkJeL+EOUGYJISv3f6Gom5VwI/njRkTwfwxfzNZVBwXM6ZtJ/hN irPbSiSwIfVJumUkk0UtinwO04rq8ZUWhG1jd2lBYX0xNzzsz8Eu22Zia6wS0EbqmtFpct AmEV9VPvFBvVdVxrD5VsjXy7XRMHQ/MbS4uA8msq7zglmY0ic4qCHYmaQhSzAVTlYQVAsm 8Gn1thUlWJATffyIJOC5ibSAG3PqK4LSp8UZHOr1nJdM3PioYdM+dJZVE8fxesTZMQLDh9 4QNSQTsr+QkwQXYn+Cs8U+mg2q1Mnc9YD63pDO7L+AVhTzdd1Qeodud3zuEWSw== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next v2 7/7] net: dsa: mt7530: do not run mt7530_setup_port5() if port 5 is disabled Date: Wed, 27 Dec 2023 07:43:47 +0300 Message-Id: <20231227044347.107291-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231227044347.107291-1-arinc.unal@arinc9.com> References: <20231227044347.107291-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com There's no need to run all the code on mt7530_setup_port5() if port 5 is disabled. The only case for calling mt7530_setup_port5() from mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from mt7530_setup_port5(). Stop initialising the interface variable as the remaining cases will always call mt7530_setup_port5() with it initialised. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 07c5f1c6d036..0c3b2b75f106 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -942,9 +942,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &=3D ~MHWTRAP_P5_DIS; break; - case P5_DISABLED: - interface =3D PHY_INTERFACE_MODE_NA; - break; default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); @@ -2313,8 +2310,6 @@ mt7530_setup(struct dsa_switch *ds) * Set priv->p5_intf_sel to the appropriate value if PHY muxing * is detected. */ - interface =3D PHY_INTERFACE_MODE_NA; - for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2346,7 +2341,9 @@ mt7530_setup(struct dsa_switch *ds) break; } =20 - mt7530_setup_port5(ds, interface); + if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB --=20 2.40.1