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[178.235.179.28]) by smtp.gmail.com with ESMTPSA id ka12-20020a170907920c00b00a26ac57b951sm6245712ejb.23.2023.12.27.14.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:17:36 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:17:19 +0100 Subject: [PATCH 1/4] PCI: qcom: Reshuffle reset logic in 2_7_0 .init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231227-topic-8280_pcie-v1-1-095491baf9e4@linaro.org> References: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> In-Reply-To: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Philipp Zabel , Stanimir Varbanov , Andrew Murray , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703715452; l=2311; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Y85jS3ioUk1DQv8qH2gvXdl3T2x3NSOAYdPJTx3pyQM=; b=hoXqb4uT3vpTCXfQv6VngPZNtLPyrOIl3j8S1277XzoP0A9AZ2jiqAbd2P3bhkGsgoYh1p5+k 5ue8mA0U803CdHHnSBa93k4XkY3BdR9CeA7LBCBucFfkLjuLg/uUtYK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= At least on SC8280XP, if the PCIe reset is asserted, the corresponding AUX_CLK will be stuck at 'off'. Assert the reset (which may end up being a NOP if it was previously asserted) and de-assert it back *before* turning on the clocks to avoid such cases. In addition to that, in case the clock bulk enable fails, assert the RC reset back, as the hardware is in an unknown state at best. Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") Signed-off-by: Konrad Dybcio --- drivers/pci/controller/dwc/pcie-qcom.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 11c80555d975..1c5ab8c4ff39 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -900,27 +900,27 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pci= e) return ret; } =20 - ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret < 0) - goto err_disable_regulators; - + /* Assert the reset to hold the RC in a known state */ ret =3D reset_control_assert(res->rst); if (ret) { dev_err(dev, "reset assert failed (%d)\n", ret); - goto err_disable_clocks; + goto err_disable_regulators; } - usleep_range(1000, 1500); =20 + /* GCC_PCIE_n_AUX_CLK won't come up if the reset is asserted */ ret =3D reset_control_deassert(res->rst); if (ret) { dev_err(dev, "reset deassert failed (%d)\n", ret); - goto err_disable_clocks; + goto err_disable_regulators; } - /* Wait for reset to complete, required on SM8450 */ usleep_range(1000, 1500); =20 + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret < 0) + goto err_assert_reset; + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 @@ -951,8 +951,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 return 0; -err_disable_clocks: - clk_bulk_disable_unprepare(res->num_clks, res->clks); + +err_assert_reset: + reset_control_assert(res->rst); err_disable_regulators: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); =20 --=20 2.43.0 From nobody Fri Dec 26 23:22:36 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 383C64879E for ; Wed, 27 Dec 2023 22:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SzFB0SoH" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-40d60ad5f0bso6406015e9.0 for ; Wed, 27 Dec 2023 14:17:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703715458; x=1704320258; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XL9QepTktwRzfZ1qfRmphE2ZEXra95fLycdHekby0tw=; b=SzFB0SoHfO6lnGAoYKGzsl3LyvoA6zou9C9a1N9/RGZHVPq/qEZzGvy9BaHFI+rDG2 Qn4Q9xR+8UfeZhsxpyfvNHKwWV7ZjIE4BKOZd23Rnp43CaGGCZM1JyfPbdCNlF2Slpav pC9gNcJ8JOY2QsZZBj0uQZYOFOdj/jFw3EE3cIMMVH37A6HZYrtij9pwfHO/VsXK1tl7 2xUiS4fwpGr4Hb67G5iZfbV8Eq7Bpa7rMcCKcyTQipG0WsY03LzU/lCc2D9tWC/Q5j8f 2LxFmOuJIBBVtiDYhNNAdX6gIkq+/MgYYvywbYjwDUKXU2WWxHch8ao/M9+P+iHz8GAl 9wuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703715458; x=1704320258; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XL9QepTktwRzfZ1qfRmphE2ZEXra95fLycdHekby0tw=; b=QNFblFSBSTflDjuKI74be4YF3dvwuHxeYfYHeKzVZXtMLrfJMG9Tl68em/niVUzg+G rmGkdzQFaA4PCCOdzM3g7TkxyeKRCObXQU6BUFc6O+HGjYaYQm3/TMyS8R5O8h6WNSnL D7nnARKrBl9XIw9INju82sWuV1rNfKExioGMmnCm7JiePvhk8Jefm3SN0NDpDECVsYUT KV6cQ5H+VLv7ZlHz9FQCv9IGo6ewzjj0Vub+9yubDWyD6bWiwQz6TOLMDP9M1kUX5mu/ Cyq+dTwADFX5x/taipZxf5lP7mRF1xfUG0L8rT8JfFaDaUCCjPwr5r7JPqOWrUAWMWyg /OWw== X-Gm-Message-State: AOJu0YybTS/uRBgLKA4N6OirFDNTFtfNFphzKiClpQyQXw7c9kNGTrDx f6I/BbIiDGpabT8F5DGxFO9KVtaPYvY7vQ== X-Google-Smtp-Source: AGHT+IFKSca7nTTTQLFFlnwqXjCbtcDKKbUOZbqtSZT1icxeWa+sWDrNIIqnQWtn+IzsLjf8TSfnyA== X-Received: by 2002:a05:600c:3d0f:b0:40d:43cf:275d with SMTP id bh15-20020a05600c3d0f00b0040d43cf275dmr5306262wmb.95.1703715458571; Wed, 27 Dec 2023 14:17:38 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id ka12-20020a170907920c00b00a26ac57b951sm6245712ejb.23.2023.12.27.14.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:17:38 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:17:20 +0100 Subject: [PATCH 2/4] PCI: qcom: Cache last icc bandwidth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231227-topic-8280_pcie-v1-2-095491baf9e4@linaro.org> References: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> In-Reply-To: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Philipp Zabel , Stanimir Varbanov , Andrew Murray , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703715452; l=1504; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qF9x2W0s+UbihjgEpXNx/tQIgEfBt4CokexyeClTC+s=; b=Ut2csbDk7i4ucgHp6UiLrRct7RJZYvkH0BNoyJ8o1AoM6NSg7odFU8uAlhMsvQEgQQw386KHm heme3d3SgUKDZ8ZSDcx8Df6lN0kgFUqgL2+0+7MI/sZqxjzPzB0J705 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In preparation for shutting down the RC, cache the last interconnect bandwidth vote to allow for icc tag setting. Signed-off-by: Konrad Dybcio --- drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 1c5ab8c4ff39..a02dc197c495 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -240,6 +240,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + u32 last_bw; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1387,6 +1388,8 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return ret; } =20 + pcie->last_bw =3D QCOM_PCIE_LINK_SPEED_TO_BW(1); + return 0; } =20 @@ -1415,6 +1418,8 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pc= ie) dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); } + + pcie->last_bw =3D width * QCOM_PCIE_LINK_SPEED_TO_BW(speed); } =20 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) @@ -1578,6 +1583,8 @@ static int qcom_pcie_suspend_noirq(struct device *dev) return ret; } =20 + pcie->last_bw =3D kBps_to_icc(1); + /* * Turn OFF the resources only for controllers without active PCIe * devices. For controllers with active devices, the resources are kept --=20 2.43.0 From nobody Fri Dec 26 23:22:36 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E036448CD3 for ; Wed, 27 Dec 2023 22:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fvL3cTvl" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5555ac4314eso936986a12.0 for ; Wed, 27 Dec 2023 14:17:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703715460; x=1704320260; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Qv1f3IGwStmHyloSnSBvki0PIRsmiqgftIEyyglb5rc=; b=fvL3cTvl8xoQCcbsfR86wsmEn3TW0hbGFsoXD5wOkUN/O91Gq+IjY3n+vxgnyD2ZDX qhA8lbuU8qTUBgtDmXRwb4K6qSvNTNnQZFcFffdhxqBCQSEm8Ak0ASXdfFzseSxMe/39 YixBJLk6UVKHE1MNC5k2eqtxdHlr40LcvhmLTWvJzXgfOK1RYfbPjD0nwquNmhUNqqcm IAc+V8mAR5LCIENEd5iWa6BCIDmyIIv5sdJRI5yXSgRte0sE6RT1fWPh5GEFB6hCSOYX nYxTh+0k/LgkUKkwfJmY7+U/jDwCZW5EwgyN1X42xnVEb+Dv428kcPO/NEWZeCN1TIJu T58g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703715460; x=1704320260; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qv1f3IGwStmHyloSnSBvki0PIRsmiqgftIEyyglb5rc=; b=twCFh+teWGiCfWURKB8g+CC/nwY1CsBbsOzrudN2vPxo/h3+mTbP3jInDowM9Rk/gv tDDQLldGyPmXdxbUHjoOUH1i/31hCCJM2q2oeD7B/Vx7wRhRI1AOma+RbOHsWVRqBmxP UPA3IEdSz300TMqOFauWeKZ2SW7ikUc13RuH6ENrSvfThh8NOaGGZzdFBG1C+zi7A+V9 ImwFOMRkIodPGBuQF/aG+d/zdh6aDY1wES4Y4t0SsgFFLgF4+WRG8TWeNfXe3MDstJox HyhSKwqRN7gazDk2zT7XhZFp5RyvX05FcuQ28wehw8y2wmj8T91gbnaUCJpNnZ9EyjNS uf8w== X-Gm-Message-State: AOJu0Yx1NFhDL7xqJ6Azg4XMIZdwn+LCn1iXqRZU9EbCcKG2ZTvt0lOD BjWM2JkVxlUz3zBKQDpukTJJNQEcfSFIZQ== X-Google-Smtp-Source: AGHT+IEjDQu21xE/LPMlU62SFkip9Wm7Icngx8+XC8yCL5jhIVQvu5IRS8ODafE/Dqc3D1LdIZBM0Q== X-Received: by 2002:a17:906:6dd1:b0:a23:67d2:917e with SMTP id j17-20020a1709066dd100b00a2367d2917emr3472572ejt.49.1703715460247; Wed, 27 Dec 2023 14:17:40 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id ka12-20020a170907920c00b00a26ac57b951sm6245712ejb.23.2023.12.27.14.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:17:39 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:17:21 +0100 Subject: [PATCH 3/4] PCI: qcom: Read back PARF_LTSSM register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231227-topic-8280_pcie-v1-3-095491baf9e4@linaro.org> References: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> In-Reply-To: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Philipp Zabel , Stanimir Varbanov , Andrew Murray , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703715452; l=809; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SCdDoH6C4jQKG683KeNay0sGQ+ywn+l9rUD6/n0edxY=; b=5d7QgU89R2lgV1XIURi/gtDcJ2KsWZR9axUKhgApYl0LlE+UkpwW+FizXcSBfdubNhkkb/oop XAMjodXAI+FB9TyZR5HK4o5sVnLxz7aenGFYtzPk3DTqzr6bSb3Ntru X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= To ensure write completion, read the PARF_LTSSM register after setting the LTSSM enable bit before polling for "link up". Signed-off-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index a02dc197c495..3d77269e70da 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -540,6 +540,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pc= ie *pcie) val =3D readl(pcie->parf + PARF_LTSSM); val |=3D LTSSM_EN; writel(val, pcie->parf + PARF_LTSSM); + readl(pcie->parf + PARF_LTSSM); } =20 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) --=20 2.43.0 From nobody Fri Dec 26 23:22:36 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F178A495DE for ; Wed, 27 Dec 2023 22:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G0d0lnHw" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-40d60a96533so6545605e9.1 for ; Wed, 27 Dec 2023 14:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703715462; x=1704320262; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JMW6ukEiM+bQd9qassIFQqfy72BMmAOOOw/d3jPA85w=; b=G0d0lnHwgcAIcmyksM9VgnpL/7oBNggZdwQO8Ia25EBTIfUHEFl6w4rGAW3MytS86u HtX95vYLFOl39FMS/bVQ7y6tvsVNBfySVjrFiXiPnrfrYkN8VktBBvRnPmL20SuVHIS+ NbhEk1dJ6HdD2nAfZXiO9jJ3UHTK4yQelZONJ7RlJRIPkkdTGVbmTGZGYQ/VjPQRT9YZ KqpkYNZ9szjsItVFMxKvX7RcB8yllEc9mPU/RptdmK1xOrCnLqGfOvGVOWULwnJvuXyN /EfMQEWgetUUcbDrQrd6PZjAyQGAAwqEzMwAI7yvBEXcMqN2fQHHwPEQ8x18/1Dp00hA vIBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703715462; x=1704320262; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JMW6ukEiM+bQd9qassIFQqfy72BMmAOOOw/d3jPA85w=; b=TxAyWyFNFMtYox8DcyA0vMNTcDdJnYaKIumxfRc2PaeysTu8yHl07mgauek9txtEYE NpFt1+n18jMxxcwfc5iPDSQMM0t/DFsF59Z1t41VpwxiyBmEUnpdw6k0WNWz4wFKpXwu Bb4dzEstRs1FUH4tQGatAnNc4cx0vZFCEJ0p40o6JRVtqyb7hGYQoinxlIz5QnX9Y8fL J7E4makXMvj6ZzkkhZoJQnhZNwjx4IzeQA6XmJEV95AQuaPlSWEcrXyoTQD2KfUEl7oU 1/qPe9aFrdWXhJo2p3vSCa6ZiMI7/JZURDAtu3hN9YgWZ8Oluam1kmKv0lCbU8gCqxH2 /9tQ== X-Gm-Message-State: AOJu0YwDlJjIsE29Wdk6j+SxL+mVef/GkBaq6/NeXW8XZAO5M61+AsCD sAwM7GeaBcH57vddS7VY5I5mUYDqgPMZZQ== X-Google-Smtp-Source: AGHT+IEr15ffMgiQ3ANHhn07jb1hFR1fa4gU3lzjq5kUeQ+ddpFRXVz7e5oRD0tOd8r2C+rfmkD7hw== X-Received: by 2002:a05:600c:17c5:b0:40c:23f2:c12d with SMTP id y5-20020a05600c17c500b0040c23f2c12dmr5990327wmo.153.1703715462252; Wed, 27 Dec 2023 14:17:42 -0800 (PST) Received: from [10.167.154.1] (178235179028.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.28]) by smtp.gmail.com with ESMTPSA id ka12-20020a170907920c00b00a26ac57b951sm6245712ejb.23.2023.12.27.14.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Dec 2023 14:17:41 -0800 (PST) From: Konrad Dybcio Date: Wed, 27 Dec 2023 23:17:22 +0100 Subject: [PATCH 4/4] PCI: qcom: Implement RC shutdown/power up Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231227-topic-8280_pcie-v1-4-095491baf9e4@linaro.org> References: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> In-Reply-To: <20231227-topic-8280_pcie-v1-0-095491baf9e4@linaro.org> To: Manivannan Sadhasivam , Bjorn Andersson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Philipp Zabel , Stanimir Varbanov , Andrew Murray , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Bjorn Andersson X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703715452; l=8228; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SOHIxQch7KXN/NGvpDtApiAK8bsu3Kt0tHCXPIEY/a0=; b=xVcIdOfd/R7LBqRnVfBIvqWNV9w5aFC1KSyhcHiWwrzFkZhRInKUsu+Sd0pgORsK7kjNqLb7t QjPMlmRMzR7DcWsREhyibEnaO9tpu+uo+5rhSL+Z7jpgINJZP/23Rb+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Currently, we've only been minimizing the power draw while keeping the RC up at all times. This is suboptimal, as it draws a whole lot of power and prevents the SoC from power collapsing. Implement full shutdown and re-initialization to allow for powering off the controller. This is mainly intended for v1_9_0 (sc8280xp), but the hardware is rather similar across the board. More platform-specific details may be added in the future as necessary. Co-developed-by: Bjorn Andersson Signed-off-by: Konrad Dybcio --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 132 +++++++++++++++++++++++++----= ---- 2 files changed, 102 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 5ac021dbd46a..591c4109ed62 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -268,6 +268,7 @@ config PCIE_DW_PLAT_EP config PCIE_QCOM bool "Qualcomm PCIe controller (host mode)" depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=3Dn depends on PCI_MSI select PCIE_DW_HOST select CRC8 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 3d77269e70da..a9e24fcd1f66 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -30,13 +30,18 @@ #include #include #include +#include =20 #include "../../pci.h" #include "pcie-designware.h" =20 +#include +#include + /* PARF registers */ #define PARF_SYS_CTRL 0x00 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 @@ -80,7 +85,10 @@ #define L1_CLK_RMV_DIS BIT(1) =20 /* PARF_PM_CTRL register fields */ -#define REQ_NOT_ENTR_L1 BIT(5) +#define REQ_NOT_ENTR_L1 BIT(5) /* "Prevent L0->L1" */ + +/* PARF_PM_STTS register fields */ +#define PM_ENTER_L23 BIT(5) =20 /* PARF_PCS_DEEMPH register fields */ #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) @@ -122,6 +130,7 @@ =20 /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) =20 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -244,6 +253,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + bool soc_is_rpmh; }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -273,6 +283,24 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } =20 +static int qcom_pcie_stop_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u32 ret_l23, val; + + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pcie->elbi + ELBI_SYS_CTRL); + readl(pcie->elbi + ELBI_SYS_CTRL); + + ret_l23 =3D readl_poll_timeout(pcie->parf + PARF_PM_STTS, val, + val & PM_ENTER_L23, 10000, 100000); + if (ret_l23) { + dev_err(pci->dev, "Failed to enter L2/L3\n"); + return -ETIMEDOUT; + } + + return 0; +} + static void qcom_pcie_clear_hpc(struct dw_pcie *pci) { u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -991,9 +1019,19 @@ static void qcom_pcie_host_post_init_2_7_0(struct qco= m_pcie *pcie) static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; + u32 val; + + /* Disable PCIe clocks and resets */ + val =3D readl(pcie->parf + PARF_PHY_CTRL); + val |=3D PHY_TEST_PWR_DOWN; + writel(val, pcie->parf + PARF_PHY_CTRL); + readl(pcie->parf + PARF_PHY_CTRL); =20 clk_bulk_disable_unprepare(res->num_clks, res->clks); =20 + reset_control_assert(res->rst); + usleep_range(2000, 2500); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } =20 @@ -1553,6 +1591,9 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) goto err_phy_exit; } =20 + /* If the soc features RPMh, cmd_db must have been prepared by now */ + pcie->soc_is_rpmh =3D !cmd_db_ready(); + qcom_pcie_icc_update(pcie); =20 if (pcie->mhi) @@ -1569,60 +1610,89 @@ static int qcom_pcie_probe(struct platform_device *= pdev) return ret; } =20 -static int qcom_pcie_suspend_noirq(struct device *dev) +static int qcom_pcie_resume_noirq(struct device *dev) { struct qcom_pcie *pcie =3D dev_get_drvdata(dev); int ret; =20 /* - * Set minimum bandwidth required to keep data path functional during - * suspend. + * Undo the tag change from qcom_pcie_suspend_noirq first in case + * RPM(h) spontaneously decides to power collapse the platform based + * on other inputs. */ - ret =3D icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); + icc_set_tag(pcie->icc_mem, pcie->soc_is_rpmh ? QCOM_ICC_TAG_ALWAYS : RPM_= ALWAYS_TAG); + /* Flush the tag change */ + ret =3D icc_set_bw(pcie->icc_mem, 0, pcie->last_bw); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(pcie->pci->dev, "failed to set interconnect bandwidth: %d\n", re= t); return ret; } =20 - pcie->last_bw =3D kBps_to_icc(1); + /* Only check this now to make sure the icc vote is in before going furht= er. */ + if (!pcie->suspended) + return 0; =20 - /* - * Turn OFF the resources only for controllers without active PCIe - * devices. For controllers with active devices, the resources are kept - * ON and the link is expected to be in L0/L1 (sub)states. - * - * Turning OFF the resources for controllers with active PCIe devices - * will trigger access violation during the end of the suspend cycle, - * as kernel tries to access the PCIe devices config space for masking - * MSIs. - * - * Also, it is not desirable to put the link into L2/L3 state as that - * implies VDD supply will be removed and the devices may go into - * powerdown state. This will affect the lifetime of the storage devices - * like NVMe. - */ - if (!dw_pcie_link_up(pcie->pci)) { - qcom_pcie_host_deinit(&pcie->pci->pp); - pcie->suspended =3D true; - } + ret =3D qcom_pcie_host_init(&pcie->pci->pp); + if (ret) + goto revert_icc_tag; + + dw_pcie_setup_rc(&pcie->pci->pp); + + ret =3D qcom_pcie_start_link(pcie->pci); + if (ret) + goto deinit_host; + + /* Ignore the retval, the devices may come up later. */ + dw_pcie_wait_for_link(pcie->pci); + + qcom_pcie_icc_update(pcie); + + pcie->suspended =3D false; =20 return 0; + +deinit_host: + qcom_pcie_host_deinit(&pcie->pci->pp); +revert_icc_tag: + icc_set_tag(pcie->icc_mem, pcie->soc_is_rpmh ? QCOM_ICC_TAG_WAKE : RPM_AC= TIVE_TAG); + /* Ignore the retval, failing here would be tragic anyway.. */ + icc_set_bw(pcie->icc_mem, 0, pcie->last_bw); + + return ret; } =20 -static int qcom_pcie_resume_noirq(struct device *dev) +static int qcom_pcie_suspend_noirq(struct device *dev) { struct qcom_pcie *pcie =3D dev_get_drvdata(dev); int ret; =20 - if (pcie->suspended) { - ret =3D qcom_pcie_host_init(&pcie->pci->pp); + if (pcie->suspended) + return 0; + + if (dw_pcie_link_up(pcie->pci)) { + ret =3D qcom_pcie_stop_link(pcie->pci); if (ret) return ret; + } =20 - pcie->suspended =3D false; + qcom_pcie_host_deinit(&pcie->pci->pp); + + /* + * The PCIe RC may be covertly accessed by the secure firmware on sleep e= xit. + * Use the WAKE bucket to let RPMh pull the plug on PCIe in sleep, + * but guarantee it comes back for resume. + */ + icc_set_tag(pcie->icc_mem, pcie->soc_is_rpmh ? QCOM_ICC_TAG_WAKE : RPM_AC= TIVE_TAG); + /* Flush the tag change */ + ret =3D icc_set_bw(pcie->icc_mem, 0, pcie->last_bw); + if (ret) { + dev_err(pcie->pci->dev, "failed to set interconnect bandwidth: %d\n", re= t); + + /* Revert everything and hope the next icc_set_bw goes through.. */ + return qcom_pcie_resume_noirq(dev); } =20 - qcom_pcie_icc_update(pcie); + pcie->suspended =3D true; =20 return 0; } --=20 2.43.0