From nobody Fri Dec 19 11:30:23 2025 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFA2845C13; Wed, 27 Dec 2023 16:24:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Kj7sUyPS" Received: by mail.gandi.net (Postfix) with ESMTPSA id 1B8E5FF815; Wed, 27 Dec 2023 16:24:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1703694248; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PHw8m05DOzdhKocLz6vovvFnXaDaWYDfUcSk4DXmRVM=; b=Kj7sUyPSUKiUuzGhIbKJ5A3pPmxu89lfjopkVLMeOPGD2QBsopdL6YmMPUr8t5hx8pcAF0 +lD/9tlIKqF6ksJ7ZBCP+NYiNYciHN3F3z1QpBdJm+AqdLpPi4vhCejrIoqJWiLq4ip3Tl UanQcHSN/dqgkNCdVBKTtcMnA8+cz0De5SnLMMDt2HS/8sgp2FHiO0/L7BOUxiidl0CDyG cYVbUNLQ1oXC0fUBGHSu8yIEARy+iQlokbmdGxpbCdXf8hlanvSlynaaExCpt2XEwKZSm9 azIe4n63+VvAiTefbJV7I/ar4YO6M0o/SMyCaB32M78jNEe1IuRRF9PuN5HoIQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 27 Dec 2023 17:23:56 +0100 Subject: [PATCH v2 6/6] MIPS: mobileye: eyeq5: use OLB clocks controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231227-mbly-clk-v2-6-a05db63c380f@bootlin.com> References: <20231227-mbly-clk-v2-0-a05db63c380f@bootlin.com> In-Reply-To: <20231227-mbly-clk-v2-0-a05db63c380f@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com We add the clock controller inside the OLB syscon region and removed previous fixed devicetree nodes representing PLLs exposed by the clock controller. Two quirks are present: - The OLB node is moved prior to UARTs, as platform device probe scheduling is dependent on devicetree ordering. - The core0-timer-clk fixed clock is created to feed the GIC timer. It requires a clock earlier than platform bus type initialisation (and therefore platform device init). Signed-off-by: Th=C3=A9o Lebrun --- .../{eyeq5-fixed-clocks.dtsi =3D> eyeq5-clocks.dtsi} | 54 ++++++++--------= ------ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 23 +++++---- 2 files changed, 34 insertions(+), 43 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mip= s/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 89% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c6..bbdaa399e408 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,26 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ =20 -/ { - /* Fixed clock */ - pll_cpu: pll-cpu { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1500000000>; - }; +#include =20 - pll_vdi: pll-vdi { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <1280000000>; - }; - - pll_per: pll-per { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <2000000000>; - }; - - pll_ddr0: pll-ddr0 { +/ { +/* Fixed clock */ + xtal: xtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; - clock-frequency =3D <1857210000>; + clock-frequency =3D <30000000>; }; =20 - pll_ddr1: pll-ddr1 { + core0_timer_clk: core0-timer-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; - clock-frequency =3D <1857210000>; + clock-frequency =3D <1500000000>; }; =20 /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_cpu>; + clocks =3D <&clocks EQ5C_PLL_CPU>; #clock-cells =3D <0>; clock-div =3D <1>; clock-mult =3D <1>; @@ -101,7 +85,7 @@ mem_clk: mem-clk { }; occ_isram: occ-isram { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_cpu>; + clocks =3D <&clocks EQ5C_PLL_CPU>; #clock-cells =3D <0>; clock-div =3D <2>; clock-mult =3D <1>; @@ -115,7 +99,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */ }; occ_dbu: occ-dbu { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_cpu>; + clocks =3D <&clocks EQ5C_PLL_CPU>; #clock-cells =3D <0>; clock-div =3D <10>; clock-mult =3D <1>; @@ -130,7 +114,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu = */ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_vdi>; + clocks =3D <&clocks EQ5C_PLL_VDI>; #clock-cells =3D <0>; clock-div =3D <2>; clock-mult =3D <1>; @@ -144,7 +128,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ }; occ_can_ser: occ-can-ser { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_vdi>; + clocks =3D <&clocks EQ5C_PLL_VDI>; #clock-cells =3D <0>; clock-div =3D <16>; clock-mult =3D <1>; @@ -158,7 +142,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ }; i2c_ser_clk: i2c-ser-clk { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_vdi>; + clocks =3D <&clocks EQ5C_PLL_VDI>; #clock-cells =3D <0>; clock-div =3D <20>; clock-mult =3D <1>; @@ -166,7 +150,7 @@ i2c_ser_clk: i2c-ser-clk { /* PLL_PER derivatives */ occ_periph: occ-periph { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <16>; clock-mult =3D <1>; @@ -225,7 +209,7 @@ gpio_clk: gpio-clk { }; emmc_sys_clk: emmc-sys-clk { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <10>; clock-mult =3D <1>; @@ -233,7 +217,7 @@ emmc_sys_clk: emmc-sys-clk { }; ccf_ctrl_clk: ccf-ctrl-clk { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <4>; clock-mult =3D <1>; @@ -241,7 +225,7 @@ ccf_ctrl_clk: ccf-ctrl-clk { }; occ_mjpeg_core: occ-mjpeg-core { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <2>; clock-mult =3D <1>; @@ -265,7 +249,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpe= g_gen */ }; fcmu_a_clk: fcmu-a-clk { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <20>; clock-mult =3D <1>; @@ -273,7 +257,7 @@ fcmu_a_clk: fcmu-a-clk { }; occ_pci_sys: occ-pci-sys { compatible =3D "fixed-factor-clock"; - clocks =3D <&pll_per>; + clocks =3D <&clocks EQ5C_PLL_PER>; #clock-cells =3D <0>; clock-div =3D <8>; clock-mult =3D <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mo= bileye/eyeq5.dtsi index d32da8fabe5a..23c67ffbad5b 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -7,7 +7,7 @@ =20 /memreserve/ 0x40000000 0xc0000000; /* DDR32 */ =20 -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" =20 / { #address-cells =3D <2>; @@ -42,6 +42,19 @@ soc: soc { ranges; compatible =3D "simple-bus"; =20 + olb: olb@e00000 { + compatible =3D "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg =3D <0 0xe00000 0x0 0x400>; + reg-io-width =3D <4>; + + clocks: clock-controller { + compatible =3D "mobileye,eyeq5-clk"; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + }; + uart0: serial@800000 { compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0 0x800000 0x0 0x1000>; @@ -72,12 +85,6 @@ uart2: serial@a00000 { clock-names =3D "uartclk", "apb_pclk"; }; =20 - olb: olb@e00000 { - compatible =3D "mobileye,eyeq5-olb", "syscon", "simple-mfd"; - reg =3D <0 0xe00000 0x0 0x400>; - reg-io-width =3D <4>; - }; - gic: interrupt-controller@140000 { compatible =3D "mti,gic"; reg =3D <0x0 0x140000 0x0 0x20000>; @@ -95,7 +102,7 @@ gic: interrupt-controller@140000 { timer { compatible =3D "mti,gic-timer"; interrupts =3D ; - clocks =3D <&core0_clk>; + clocks =3D <&core0_timer_clk>; }; }; }; --=20 2.43.0