From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1593E4432 for ; Tue, 26 Dec 2023 19:22:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lg6zEGOV" Received: by mail-io1-f50.google.com with SMTP id ca18e2360f4ac-7b7fdde8b26so206711539f.1 for ; Tue, 26 Dec 2023 11:22:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618522; x=1704223322; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DpqenrRUC6bjM3FBUQeM6IW1qxia9n9naxBupjAv3uo=; b=lg6zEGOVJELIYZP8LcIUqeyWpjIYPc2ZgojXQgmoqL5txatFJtk/ELRg86mTlcJrAY 22xSDZciqMVfDmYi+JudnojpMsLhfQskc4E4qDHnRBbNHsZ4FfnMyt6NwqiXgRy3kMLF EoZ9/WMDZhexTgoIQzLvp6bxk7lmt0XCwdFcw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618522; x=1704223322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DpqenrRUC6bjM3FBUQeM6IW1qxia9n9naxBupjAv3uo=; b=Y453cvDYWseHD/Gn9rnbChnuQU0aANrqXjBV93FCi5MQI14Fv2hJ9IAZnpcHtMPJN0 csVhGgfZCIi8nw6T8V6Ze8NivllfE/kweJqLRNgXowdjmakntPsZcaUZjOtqJycDWAeJ w/+eSyQHVuqsQDYK5tzEYmbutKPnZ9ze3Y208qbzn367WVf//f0Vk1cH1wmOoKV2irQl f/NYQdkoemAyJV4EDFDH91JSidaITEhooudzVTiuKHMZdGH6e7IkI/1UUvTnrfAA1QKn j0hla64T7mvIC+KWNGQWoOmWYv6zhOlpeJ6a+T3tw6FRZyi6ALlDUlf9uQidtboCaSw0 3h3w== X-Gm-Message-State: AOJu0Ywy36OLB2GKT44PNOjnfDFjisFKx8iLVESvr9qsIyjJOt7FCQvz rJR7bBtDTfVC8jmayilnkKuFPavf4YdNoC09TolwOtQ7hc5e X-Google-Smtp-Source: AGHT+IEnaakr4yflxOfeuRigCCOhCiNNEjEufMoK0+OASnyXoZd6Lu/qchJ7FyR+kZgyYfKQ+nYn2w== X-Received: by 2002:a6b:ef14:0:b0:7bb:818:9eeb with SMTP id k20-20020a6bef14000000b007bb08189eebmr401147ioh.37.1703618522186; Tue, 26 Dec 2023 11:22:02 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:01 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , AKASHI Takahiro , Andrew Morton , Andy Shevchenko , Baoquan He , Greg Kroah-Hartman Subject: [PATCH v3 01/24] resource: Add DEFINE_RES_*_NAMED_FLAGS macro Date: Tue, 26 Dec 2023 12:21:05 -0700 Message-ID: <20231226122113.v3.1.I59b56ebd2f303784031c27bbb1529cf6ef71ba16@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In some cases, it would be nice to instantiate a struct resource with custom flags. For example, creating an IRQ resource with a flag that marks the interrupt as wake capable. Add a set of macros to provide custom flag arguments. Suggested-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer Reviewed-by: Andy Shevchenko --- Changes in v3: -New patch include/linux/ioport.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/include/linux/ioport.h b/include/linux/ioport.h index db7fe25f33700..a44e73ca058a8 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -163,28 +163,38 @@ enum { .desc =3D IORES_DESC_NONE, \ } =20 +#define DEFINE_RES_IO_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_IO) #define DEFINE_RES_IO_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_IO) + DEFINE_RES_IO_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_IO(_start, _size) \ DEFINE_RES_IO_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_MEM_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_MEM) #define DEFINE_RES_MEM_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_MEM) + DEFINE_RES_MEM_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_MEM(_start, _size) \ DEFINE_RES_MEM_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_REG_NAMED_FLAGS(_start, _size, _name, _flags) \ + DEFINE_RES_NAMED((_start), (_size), (_name), (_flags) | IORESOURCE_REG) #define DEFINE_RES_REG_NAMED(_start, _size, _name) \ - DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_REG) + DEFINE_RES_REG_NAMED_FLAGS((_start), (_size), (_name), 0) #define DEFINE_RES_REG(_start, _size) \ DEFINE_RES_REG_NAMED((_start), (_size), NULL) =20 +#define DEFINE_RES_IRQ_NAMED_FLAGS(_irq, _name, _flags) \ + DEFINE_RES_NAMED((_irq), 1, (_name), (_flags) | IORESOURCE_IRQ) #define DEFINE_RES_IRQ_NAMED(_irq, _name) \ - DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ) + DEFINE_RES_IRQ_NAMED_FLAGS((_irq), (_name), 0) #define DEFINE_RES_IRQ(_irq) \ DEFINE_RES_IRQ_NAMED((_irq), NULL) =20 +#define DEFINE_RES_DMA_NAMED_FLAGS(_dma, _name, _flags) \ + DEFINE_RES_NAMED((_dma), 1, (_name), (_flags) | IORESOURCE_DMA) #define DEFINE_RES_DMA_NAMED(_dma, _name) \ - DEFINE_RES_NAMED((_dma), 1, (_name), IORESOURCE_DMA) + DEFINE_RES_DMA_NAMED_FLAGS((_dma), (_name), 0) #define DEFINE_RES_DMA(_dma) \ DEFINE_RES_DMA_NAMED((_dma), NULL) =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-il1-f180.google.com (mail-il1-f180.google.com [209.85.166.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1C514C98 for ; Tue, 26 Dec 2023 19:22:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lvB4bEwh" Received: by mail-il1-f180.google.com with SMTP id e9e14a558f8ab-35fc6eb9075so11377175ab.1 for ; Tue, 26 Dec 2023 11:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618524; x=1704223324; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KWSLh74Sjb1tnv40s7SuHViSbHQs5lvDO8AcO/YGKCU=; b=lvB4bEwh8SzCjHd25S6XOlpwpVCpAz8icWVBXvruNofgp/9Zz42hlBEogjopzaeH1D MJLKuLZoVAf1Bf3sU9YeaoI4jcx0/tbgBLIaJ9BKh+7VSCtMBCtasXDp8VlBqesCk4ZW 7upaiqdH4jiySA5UnJ687sjvAbGn5mVgQij1w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618524; x=1704223324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KWSLh74Sjb1tnv40s7SuHViSbHQs5lvDO8AcO/YGKCU=; b=mu4ypv5ZfgzHOzFKdDxiFTGG4EnmzwrzXa2JWh3DDdc7RlOQB/bT/JIY36gYkuyzdH bBxb2vWvv4kWPQ8vB+XUdk43B/E/BN3r4gcYiQ9PgZ00FVRguNIW9thKz1UKgTVCclWN KTqZaR3ORJ5oJXTg08AeLOd5YvsvvTPeeOTMaCe/OrGueGPl2la1xUpYNnHVQDqmdfiJ Wk6Thz/s3fyYMG4FjgkvA3PeZUrtI0BpLgTgV8K2Rzc2raN33vcRrtvcT6wYQ8RrvDfN IgWjsMpvMuXwnkcZhDp+vXRNjkigBwOu7tvIQx2JxdDlnER0+Uvq4nT+dxyGrN339q8l f8PQ== X-Gm-Message-State: AOJu0Yxfc88AYb4bDC8RfKikiAYy/LHJeP5w+Zu5QJY6/wHJaft3mpR6 X+rBH7O8tRiaINt0z6PRdjX9iBat3GTPBSDtim6RubbwOH1W X-Google-Smtp-Source: AGHT+IGDCtaOFBQfliLMWuw+Bp0lLVTZeCWzg9u2yDUWIqDNp8kfxPkAF10al2bkUVOApEziXN9uEA== X-Received: by 2002:a05:6e02:144a:b0:360:193:f434 with SMTP id p10-20020a056e02144a00b003600193f434mr1829834ilo.28.1703618523868; Tue, 26 Dec 2023 11:22:03 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:03 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , Bartosz Golaszewski , Len Brown , Linus Walleij , Mika Westerberg , "Rafael J. Wysocki" , Wolfram Sang , linux-acpi@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH v3 02/24] gpiolib: acpi: Modify acpi_dev_irq_wake_get_by() to use resource Date: Tue, 26 Dec 2023 12:21:06 -0700 Message-ID: <20231226122113.v3.2.Ifd0903f1c351e84376d71dbdadbd43931197f5ea@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Other information besides wake capability can be provided about GPIO IRQs such as triggering, polarity, and sharability. Use resource flags to provide this information to the caller if they want it. This should keep the API more robust over time as flags are added, modified, or removed. It also more closely matches acpi_irq_get() which take a resource as an argument. Rename the function to acpi_dev_get_gpio_irq_resource() to better describe the function's new behavior. Signed-off-by: Mark Hasemeyer --- Changes in v3: -Use DEFINE_RES_NAMED macro -Add acpi_gpio_info.shareable doc Changes in v2: -Remove explicit cast to struct resource -irq -> IRQ drivers/gpio/gpiolib-acpi.c | 27 ++++++++++++++++++--------- drivers/i2c/i2c-core-acpi.c | 10 ++++++++-- include/linux/acpi.h | 23 ++++++++++------------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c index 88066826d8e5b..24232534a9cdf 100644 --- a/drivers/gpio/gpiolib-acpi.c +++ b/drivers/gpio/gpiolib-acpi.c @@ -99,6 +99,7 @@ struct acpi_gpio_chip { * @pin_config: pin bias as provided by ACPI * @polarity: interrupt polarity as provided by ACPI * @triggering: triggering type as provided by ACPI + * @shareable: share type as provided by ACPI (shared vs exclusive). * @wake_capable: wake capability as provided by ACPI * @debounce: debounce timeout as provided by ACPI * @quirks: Linux specific quirks as provided by struct acpi_gpio_mapping @@ -111,6 +112,7 @@ struct acpi_gpio_info { int polarity; int triggering; bool wake_capable; + bool shareable; unsigned int debounce; unsigned int quirks; }; @@ -760,6 +762,7 @@ static int acpi_populate_gpio_lookup(struct acpi_resour= ce *ares, void *data) lookup->info.debounce =3D agpio->debounce_timeout; lookup->info.gpioint =3D gpioint; lookup->info.wake_capable =3D acpi_gpio_irq_is_wake(&lookup->info.adev->= dev, agpio); + lookup->info.shareable =3D agpio->shareable =3D=3D ACPI_SHARED; =20 /* * Polarity and triggering are only specified for GpioInt @@ -1004,11 +1007,11 @@ struct gpio_desc *acpi_find_gpio(struct fwnode_hand= le *fwnode, } =20 /** - * acpi_dev_gpio_irq_wake_get_by() - Find GpioInt and translate it to Linu= x IRQ number + * acpi_dev_get_gpio_irq_resource() - Find GpioInt and populate resource s= truct * @adev: pointer to a ACPI device to get IRQ from * @name: optional name of GpioInt resource * @index: index of GpioInt resource (starting from %0) - * @wake_capable: Set to true if the IRQ is wake capable + * @r: pointer to resource to populate with IRQ information. * * If the device has one or more GpioInt resources, this function can be * used to translate from the GPIO offset in the resource to the Linux IRQ @@ -1023,10 +1026,12 @@ struct gpio_desc *acpi_find_gpio(struct fwnode_hand= le *fwnode, * The GPIO is considered wake capable if the GpioInt resource specifies * SharedAndWake or ExclusiveAndWake. * - * Return: Linux IRQ number (> %0) on success, negative errno on failure. + * IRQ number will be available in the resource structure. + * + * Return: 0 on success, negative errno on failure. */ -int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, const char *na= me, int index, - bool *wake_capable) +int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev, const char *n= ame, int index, + struct resource *r) { int idx, i; unsigned int irq_flags; @@ -1045,6 +1050,7 @@ int acpi_dev_gpio_irq_wake_get_by(struct acpi_device = *adev, const char *name, in if (info.gpioint && idx++ =3D=3D index) { unsigned long lflags =3D GPIO_LOOKUP_FLAGS_DEFAULT; enum gpiod_flags dflags =3D GPIOD_ASIS; + unsigned long res_flags; char label[32]; int irq; =20 @@ -1084,16 +1090,19 @@ int acpi_dev_gpio_irq_wake_get_by(struct acpi_devic= e *adev, const char *name, in } =20 /* avoid suspend issues with GPIOs when systems are using S3 */ - if (wake_capable && acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) - *wake_capable =3D info.wake_capable; + if (info.wake_capable && !(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0= )) + info.wake_capable =3D false; =20 - return irq; + res_flags =3D acpi_dev_irq_flags(info.triggering, info.polarity, + info.shareable, info.wake_capable); + *r =3D DEFINE_RES_NAMED(irq, 1, NULL, res_flags); + return 0; } =20 } return -ENOENT; } -EXPORT_SYMBOL_GPL(acpi_dev_gpio_irq_wake_get_by); +EXPORT_SYMBOL_GPL(acpi_dev_get_gpio_irq_resource); =20 static acpi_status acpi_gpio_adr_space_handler(u32 function, acpi_physical_address address, diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c index d6037a3286690..8126a87baf3d4 100644 --- a/drivers/i2c/i2c-core-acpi.c +++ b/drivers/i2c/i2c-core-acpi.c @@ -203,6 +203,7 @@ int i2c_acpi_get_irq(struct i2c_client *client, bool *w= ake_capable) { struct acpi_device *adev =3D ACPI_COMPANION(&client->dev); struct list_head resource_list; + struct resource irqres; struct i2c_acpi_irq_context irq_ctx =3D { .irq =3D -ENOENT, }; @@ -217,8 +218,13 @@ int i2c_acpi_get_irq(struct i2c_client *client, bool *= wake_capable) =20 acpi_dev_free_resource_list(&resource_list); =20 - if (irq_ctx.irq =3D=3D -ENOENT) - irq_ctx.irq =3D acpi_dev_gpio_irq_wake_get(adev, 0, &irq_ctx.wake_capabl= e); + if (irq_ctx.irq =3D=3D -ENOENT) { + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); + if (ret) + return ret; + irq_ctx.irq =3D irqres.start; + irq_ctx.wake_capable =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; + } =20 if (irq_ctx.irq < 0) return irq_ctx.irq; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 118a18b7ff844..83aa2fa8e81fc 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1221,8 +1221,8 @@ bool acpi_gpio_get_irq_resource(struct acpi_resource = *ares, struct acpi_resource_gpio **agpio); bool acpi_gpio_get_io_resource(struct acpi_resource *ares, struct acpi_resource_gpio **agpio); -int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, const char *na= me, int index, - bool *wake_capable); +int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev, const char *n= ame, int index, + struct resource *r); #else static inline bool acpi_gpio_get_irq_resource(struct acpi_resource *ares, struct acpi_resource_gpio **agpio) @@ -1234,28 +1234,25 @@ static inline bool acpi_gpio_get_io_resource(struct= acpi_resource *ares, { return false; } -static inline int acpi_dev_gpio_irq_wake_get_by(struct acpi_device *adev, = const char *name, - int index, bool *wake_capable) +static inline int acpi_dev_get_gpio_irq_resource(struct acpi_device *adev,= const char *name, + int index, struct resource *r) { return -ENXIO; } #endif =20 -static inline int acpi_dev_gpio_irq_wake_get(struct acpi_device *adev, int= index, - bool *wake_capable) +static inline int acpi_dev_gpio_irq_get_by(struct acpi_device *adev, const= char *name, int index) { - return acpi_dev_gpio_irq_wake_get_by(adev, NULL, index, wake_capable); -} + struct resource r; + int ret; =20 -static inline int acpi_dev_gpio_irq_get_by(struct acpi_device *adev, const= char *name, - int index) -{ - return acpi_dev_gpio_irq_wake_get_by(adev, name, index, NULL); + ret =3D acpi_dev_get_gpio_irq_resource(adev, name, index, &r); + return ret ?: r.start; } =20 static inline int acpi_dev_gpio_irq_get(struct acpi_device *adev, int inde= x) { - return acpi_dev_gpio_irq_wake_get_by(adev, NULL, index, NULL); + return acpi_dev_gpio_irq_get_by(adev, NULL, index); } =20 /* Device properties */ --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B68DA523D for ; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:04 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Mika Westerberg , Wolfram Sang , linux-acpi@vger.kernel.org, linux-i2c@vger.kernel.org Subject: [PATCH v3 03/24] i2c: acpi: Modify i2c_acpi_get_irq() to use resource Date: Tue, 26 Dec 2023 12:21:07 -0700 Message-ID: <20231226122113.v3.3.Ib65096357993ff602e7dd0000dd59a36571c48d8@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The i2c_acpi_irq_context structure provides redundant information that can be provided with struct resource. Refactor i2c_acpi_get_irq() to use struct resource instead of struct i2c_acpi_irq_context. Suggested-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer --- Changes in v3: -Add Suggested-by -Check resource flags for valid irq -Drop error pointer check -Invert error checking logic in i2c_acpi_get_irq() -Drop redundant 0 in struct resource init -Drop unnecessary check for irq > 0 when setting I2C_CLIENT_WAKE Changes in v2: -New patch drivers/i2c/i2c-core-acpi.c | 43 ++++++++++++++----------------------- drivers/i2c/i2c-core-base.c | 6 +++--- drivers/i2c/i2c-core.h | 4 ++-- 3 files changed, 21 insertions(+), 32 deletions(-) diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c index 8126a87baf3d4..e48bb24b72127 100644 --- a/drivers/i2c/i2c-core-acpi.c +++ b/drivers/i2c/i2c-core-acpi.c @@ -175,64 +175,53 @@ static int i2c_acpi_do_lookup(struct acpi_device *ade= v, =20 static int i2c_acpi_add_irq_resource(struct acpi_resource *ares, void *dat= a) { - struct i2c_acpi_irq_context *irq_ctx =3D data; - struct resource r; + struct resource *r =3D data; =20 - if (irq_ctx->irq > 0) + if (r->flags) return 1; =20 - if (!acpi_dev_resource_interrupt(ares, 0, &r)) + if (!acpi_dev_resource_interrupt(ares, 0, r)) return 1; =20 - irq_ctx->irq =3D i2c_dev_irq_from_resources(&r, 1); - irq_ctx->wake_capable =3D r.flags & IORESOURCE_IRQ_WAKECAPABLE; + i2c_dev_irq_from_resources(r, 1); =20 return 1; /* No need to add resource to the list */ } =20 /** - * i2c_acpi_get_irq - get device IRQ number from ACPI + * i2c_acpi_get_irq - get device IRQ number from ACPI and populate resource * @client: Pointer to the I2C client device - * @wake_capable: Set to true if the IRQ is wake capable + * @r: resource with populated IRQ information * * Find the IRQ number used by a specific client device. * * Return: The IRQ number or an error code. */ -int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_capable) +int i2c_acpi_get_irq(struct i2c_client *client, struct resource *r) { struct acpi_device *adev =3D ACPI_COMPANION(&client->dev); struct list_head resource_list; - struct resource irqres; - struct i2c_acpi_irq_context irq_ctx =3D { - .irq =3D -ENOENT, - }; int ret; =20 + if (!r) + return -EINVAL; + INIT_LIST_HEAD(&resource_list); =20 ret =3D acpi_dev_get_resources(adev, &resource_list, - i2c_acpi_add_irq_resource, &irq_ctx); + i2c_acpi_add_irq_resource, r); if (ret < 0) return ret; =20 acpi_dev_free_resource_list(&resource_list); =20 - if (irq_ctx.irq =3D=3D -ENOENT) { - ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); - if (ret) - return ret; - irq_ctx.irq =3D irqres.start; - irq_ctx.wake_capable =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; - } - - if (irq_ctx.irq < 0) - return irq_ctx.irq; + if (!r->flags) + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, r); =20 - if (wake_capable) - *wake_capable =3D irq_ctx.wake_capable; + if (!r->flags) + return ret; =20 - return irq_ctx.irq; + return r->start; } =20 static int i2c_acpi_get_info(struct acpi_device *adev, diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index 3bd48d4b6318f..0339c298ba50b 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -513,10 +513,10 @@ static int i2c_device_probe(struct device *dev) if (irq =3D=3D -EINVAL || irq =3D=3D -ENODATA) irq =3D of_irq_get(dev->of_node, 0); } else if (ACPI_COMPANION(dev)) { - bool wake_capable; + struct resource r =3D {}; =20 - irq =3D i2c_acpi_get_irq(client, &wake_capable); - if (irq > 0 && wake_capable) + irq =3D i2c_acpi_get_irq(client, &r); + if (r.flags & IORESOURCE_IRQ_WAKECAPABLE) client->flags |=3D I2C_CLIENT_WAKE; } if (irq =3D=3D -EPROBE_DEFER) { diff --git a/drivers/i2c/i2c-core.h b/drivers/i2c/i2c-core.h index 05b8b8dfa9bdd..b5dc559c49d11 100644 --- a/drivers/i2c/i2c-core.h +++ b/drivers/i2c/i2c-core.h @@ -61,11 +61,11 @@ static inline int __i2c_check_suspended(struct i2c_adap= ter *adap) #ifdef CONFIG_ACPI void i2c_acpi_register_devices(struct i2c_adapter *adap); =20 -int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_capable); +int i2c_acpi_get_irq(struct i2c_client *client, struct resource *r); #else /* CONFIG_ACPI */ static inline void i2c_acpi_register_devices(struct i2c_adapter *adap) { } =20 -static inline int i2c_acpi_get_irq(struct i2c_client *client, bool *wake_c= apable) +static inline int i2c_acpi_get_irq(struct i2c_client *client, struct resou= rce *r) { return 0; } --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3292538A for ; Tue, 26 Dec 2023 19:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Cy/CqcB3" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7bafda3999cso21319039f.0 for ; Tue, 26 Dec 2023 11:22:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618525; x=1704223325; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:05 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v3 04/24] dt-bindings: power: Clarify wording for wakeup-source property Date: Tue, 26 Dec 2023 12:21:08 -0700 Message-ID: <20231226122113.v3.4.I1016a45ac9e8daf8a9ebc9854ab90ec3542e7c30@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The wording in the current documentation is a little strong. The intention was not to fix any particular interrupt as wakeup capable but leave those details to the device. It wasn't intended to enforce any rules as what can be or can't be a wakeup interrupt. Soften the wording to not mandate that the 'wakeup-source' property be used, and clarify what it means when an interrupt is marked (or not marked) for wakeup. Link: https://lore.kernel.org/all/ZYAjxxHcCOgDVMTQ@bogus/ Link: https://lore.kernel.org/all/CAL_Jsq+MYwOG40X26cYmO9EkZ9xqWrXDi03MaRfx= nV-+VGkXWQ@mail.gmail.com/ Signed-off-by: Mark Hasemeyer --- Changes in v3: -Update commit title prefixes Changes in v2: -New patch .../bindings/power/wakeup-source.txt | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/power/wakeup-source.txt b/Do= cumentation/devicetree/bindings/power/wakeup-source.txt index 697333a56d5e2..75bc20b95688f 100644 --- a/Documentation/devicetree/bindings/power/wakeup-source.txt +++ b/Documentation/devicetree/bindings/power/wakeup-source.txt @@ -3,16 +3,20 @@ Specifying wakeup capability for devices =20 Any device nodes ---------------- -Nodes that describe devices which has wakeup capability must contain an +Nodes that describe devices which have wakeup capability may contain a "wakeup-source" boolean property. =20 -Also, if device is marked as a wakeup source, then all the primary -interrupt(s) can be used as wakeup interrupt(s). +If the device is marked as a wakeup-source, interrupt wake capability depe= nds +on the device specific "interrupt-names" property. If no interrupts are la= beled +as wake capable, then it is up to the device to determine which interrupts= can +wake the system. =20 -However if the devices have dedicated interrupt as the wakeup source -then they need to specify/identify the same using device specific -interrupt name. In such cases only that interrupt can be used as wakeup -interrupt. +However if a device has a dedicated interrupt as the wakeup source, then it +needs to specify/identify it using a device specific interrupt name. In su= ch +cases only that interrupt can be used as a wakeup interrupt. + +While various legacy interrupt names exist, new devices should use "wakeup= " as +the canonical interrupt name. =20 List of legacy properties and respective binding document --------------------------------------------------------- --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D208F4F8 for ; Tue, 26 Dec 2023 19:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PbeqUeut" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7bb0a93b7c7so5128339f.2 for ; Tue, 26 Dec 2023 11:22:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618526; x=1704223326; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9rsZne3Du//Ba4tQVuy5o6whq4EULCeTIrjLPCPwLmw=; b=PbeqUeutUGm76q78UEDh2my6snYS1o26/wLzk83OYI0Iq0FYVbRaTFkkWvYmq466A3 Q3uhC9vIwUyiTIVDAgETxRMaLSUshEhL+1GwSZ5KKGXCGUv+3hFf73iUF20Lqd1wn9ql UR9UuiDjOR5fyGCab8ZZ7Y7lq19iJojYsn3E8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618526; x=1704223326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9rsZne3Du//Ba4tQVuy5o6whq4EULCeTIrjLPCPwLmw=; b=Zaim9JMhELg9aWrWTvJpJk/s048H2AdW0Kj27Ni/wMnTenrSOz4e5sZnSLMZ282bT3 rdCEN47F+K5WKdjVVoArdwY5zJclIuIpm5FIbI8UgaeKza7YY6VuovtnqAhjP4/6wFH0 4k9L5pOIImgLnMCNnVYonUXJrD/ZxdhtuYiK4wZxNJIKsproZYNmCiMvEVbSGMkNzvPF /9+uZfbY4nJwtCz+vJrYaFxxtpx48gKYcL780ZGukwchLPB5SgnRe1KS1reZRBcCiPFC qwX2L0g8hbT8p3kzX/tmE/KGQogOulan4UrXFGubS4RHyZLprq0AsegtmqgCm3L/ri7U p6Cw== X-Gm-Message-State: AOJu0YzVwLn/+rpz4Vcjlz/QTVSetsvMoppzSFmdu3Z4f+oKlfoiAKim r2eo/E57b7YesAAshiQPNDPYM8N0Qlm5r19lulbQhaBQgaQ9 X-Google-Smtp-Source: AGHT+IHs1QYIWBfAJ7Y5I9JjqcChVhSW1Ns/FLlrlDgrSy48A7jEaduIJBcEhsZZObOO6KB70LTa+w== X-Received: by 2002:a5e:8b0c:0:b0:7ba:fcc0:e03e with SMTP id g12-20020a5e8b0c000000b007bafcc0e03emr1029520iok.14.1703618526626; Tue, 26 Dec 2023 11:22:06 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:06 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alexandre TORGUE , Andre Przywara , Conor Dooley , Enric Balletbo i Serra , Jonathan Hunter , Krzysztof Kozlowski , Manivannan Sadhasivam , Michal Simek , Nick Hawkins , Rob Herring , Thierry Reding , Tony Lindgren , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 05/24] ARM: dts: tegra: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:09 -0700 Message-ID: <20231226122113.v3.5.Ia598792a1386cca61844068be03c3ccec9e81753@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/nvidia/tegra124-venice2.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dt= s/nvidia/tegra124-nyan.dtsi index a2ee371802004..8125c1b3e8d79 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ cros_ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/= dts/nvidia/tegra124-venice2.dts index 3924ee385dee0..df98dc2a67b85 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ cros_ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7712E10787 for ; Tue, 26 Dec 2023 19:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="P3pr2sOR" Received: by mail-io1-f52.google.com with SMTP id ca18e2360f4ac-7b7fe0ae57bso282932639f.0 for ; Tue, 26 Dec 2023 11:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618527; x=1704223327; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0beT1lRwobeT/udVDQveaOigS7b6fLoDcuD/SsK5GZQ=; b=P3pr2sOR9z0/tXAJUanFzFtyCpxX8jbcbdKNQdMmTG63pnUrHJmnd9rcLN/9j4KNrm fGXf88rKXmH4Rfw7N0WObjnLgxNWHzedNvqDHWRWEjBkO5vpbAyUBpQDjQeDX2Nm1l49 ltSzlD1/qd4tCRX4flNFw9NKlkBNryfXG/Rto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618527; x=1704223327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0beT1lRwobeT/udVDQveaOigS7b6fLoDcuD/SsK5GZQ=; b=cEQe+1X6gNY0kHjrujRXRpcpgUUAvHkr4niCIjNq5AjHWpKYjhZ8iHI/sChxcMHtwV xyJKPxeCRoA9xE3QtO2fhIXwxztOOPOjFaUYrm8BNXPvEgPL8mhCus2p4zCDYC9YxFIv EvWtUccMkz+1pF1vHgsa1HewMawPfqWTcvhM3/CCJIO1beokOX5EMykO99n+kcuTk+WE /rjs6SnIO64Z6w8EUpXrmIJEzYXbrdM/8Qd8TbNMc6fTU4ofCzzcA6D+/pr4euVKOOPW iaNeee6zdAqA+nCRNKYMwhaANPwNPfOsEF4PXXGbTCROauwgVUFzalzczJeQIXbWFqcH 17ow== X-Gm-Message-State: AOJu0YxtEUp6ohEoMC0f14MjMkrctT6LuKhf0LTrFlv0pZ+lFxbCD8QY 0Ay8cvrxTGbqPSId0lGjwwlnAUEQ3TAhLLSAeJzgLINbnEZw X-Google-Smtp-Source: AGHT+IGADxqOdqzCrh+kKQobH0CySQymMukyoXwB9KeUWYmRE9fqJHH6xGioz00eswrRyG6LPpu5FQ== X-Received: by 2002:a6b:5a15:0:b0:7ba:b0d7:20e5 with SMTP id o21-20020a6b5a15000000b007bab0d720e5mr9733427iob.0.1703618527498; Tue, 26 Dec 2023 11:22:07 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:07 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 06/24] ARM: dts: rockchip: rk3288: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:10 -0700 Message-ID: <20231226122113.v3.6.I8249df4df0b7d12fb68ea1e69f84ca589c574bb1@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arc= h/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 092316be67f74..1554fe36e60fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -112,6 +112,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_int>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D68E1096D for ; Tue, 26 Dec 2023 19:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lKxoWkTJ" Received: by mail-io1-f51.google.com with SMTP id ca18e2360f4ac-7b7fdde8b26so206716739f.1 for ; Tue, 26 Dec 2023 11:22:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618528; x=1704223328; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=thrF0ILWTbiGFQaiH41yQtWJ81V5Pd2rM8k0MkABtdQ=; b=lKxoWkTJ/tP5Ccz3HNM0UnoM+TK+LTRVr9GmxUZK+TzKAdbpKeT1vro64k64+VAD0O pFsaD+qJ9rUO9HSij2yaqD0zU7YDSz+y5YOiDPwLPZue/2B8gAySVSodZV9JmoP/bvOd fvFknw0VpFuiJ6HCvqCtHhj86sVge+WwnegFI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618528; x=1704223328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=thrF0ILWTbiGFQaiH41yQtWJ81V5Pd2rM8k0MkABtdQ=; b=dXxCKfpRb01Pf7HKEMIYZRO6eYPti7PPBrdAATBxX6oK3LWi4iLapW0mp4h9mCnmwY 6tsvq8jxr0P/ScGA2CYNxmJEL+EpmE8aw0TYlZBril2RtY8dxa3v1g093qvI2xCg5khJ 7V7voxnpYRrvu9m0sVQLcaUVGzFJD/2sLRiM6LuDDMNiB3h1kY+LwUZwinTxoTvZRVFd hmxyQJ7XT+HmfXb3FFhqiOWJOek938YHpp3vpP8Eqw80f+8/ZHQk+GP0Tpwfa01JZ76X n9ULyyK+kEcb4jakPdeO/ntg+xuPI8pYwFjdu8sBhycV/CjQ7am7iqRcAgTpeCc2ZKMj Mgtw== X-Gm-Message-State: AOJu0Yy1rI0mjkq46hEJ5iu6BrQEJPQFhvVIooCgT1dFH/1t0K/eyvT+ tJDxESOhhfnSBAbxO/Ti7ebw/MK9gtyJjL+rdeKJYSNbl50q X-Google-Smtp-Source: AGHT+IHP3cqF61lIxGXtlQrM4I81aWrz2Mcja1UYOJWo/ufdUqAFWvhIXG2CTqcyA9nGB6m/VVxrbw== X-Received: by 2002:a05:6602:3f8f:b0:7ba:9784:d96f with SMTP id fb15-20020a0566023f8f00b007ba9784d96fmr11764777iob.20.1703618528314; Tue, 26 Dec 2023 11:22:08 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:08 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 07/24] ARM: dts: samsung: exynos5420: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:11 -0700 Message-ID: <20231226122113.v3.7.I06b059021de1bf6103e60a73211f078f2af75d17@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts b/arch/arm/= boot/dts/samsung/exynos5420-peach-pit.dts index 4e757b6e28e1c..3759742d38cac 100644 --- a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ cros_ec: cros-ec@0 { reg =3D <0>; spi-max-frequency =3D <3125000>; google,has-vbc-nvram; + wakeup-source; =20 controller-data { samsung,spi-feedback-delay =3D <1>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-il1-f179.google.com (mail-il1-f179.google.com [209.85.166.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E5C710A31 for ; Tue, 26 Dec 2023 19:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Bk0PBuj3" Received: by mail-il1-f179.google.com with SMTP id e9e14a558f8ab-3600dc78bc0so3263445ab.2 for ; Tue, 26 Dec 2023 11:22:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618529; x=1704223329; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VEODyyeyprVfJRUjUtUcn0PH/jJY9TEHe0bos5Y4zHc=; b=Bk0PBuj3zKTP/LArK9YDe0mv7GUIt00/gfVPl240ojZ+vU9/0kiadYnEJLigw2zm3Q qQNm0qsp606kFMaXFuIQcYYrzpMPBeJ4FhODDBD7JOVDLILC3Q3yaCls3e4OsBUuoSww dVdOd4u0aEMWydzzirDdbT/0XUdhXnFiH5P4w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618529; x=1704223329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VEODyyeyprVfJRUjUtUcn0PH/jJY9TEHe0bos5Y4zHc=; b=Deh3DGgUOu64pXoC27CqqaoIp64IFb2eGPuiHcnOhAvzu3QmmGPd0uaZNIooT9KFlH ORHnly8YMst7BfL6mdkKOEutHV0zWZ4S7zmkQKDB4aMUd6JAvF9336ajDvs2CVIILuXH CK54yz3maWkZcBmcIxeuvqOnLmJPVs4BYx/x8xGhqK0CVwi5RvhyGFUN1yg/28eIhkCo 8E+ZYmF1wayo5H12Tlads0ba2WCJ0MMgL8QV3WS+wgD9uG3gUOrsK7YWIH17kAr3s4Sq 8HKjNNxji+XDbNjyFL2KcO9dzKUImPN/laxDEpviDH8P26ngOnUMDZf+9Oy4fBLeHXdo RFzA== X-Gm-Message-State: AOJu0YxXG8fsqxyZRTqpKCv1fgVd8ahL3vCls/DG3emqCkpuA97p6lpK NeRn+6Vfp3JMUntmZWnBN3TeRtABRLb7Gz4FujFHUiHrCLp5 X-Google-Smtp-Source: AGHT+IHa/0vFINH4R7TOUcFlOypJ6/So3v6QYpByaNG5AzpKzcz2ODJE44ZeU7zukq+ljzKdNZ5lIA== X-Received: by 2002:a05:6e02:1528:b0:360:17a7:1f28 with SMTP id i8-20020a056e02152800b0036017a71f28mr963152ilu.15.1703618529143; Tue, 26 Dec 2023 11:22:09 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:08 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Alim Akhtar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 08/24] ARM: dts: samsung: exynos5800: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:12 -0700 Message-ID: <20231226122113.v3.8.Idc995ce08a52ba4c5fde0685118ddf2873fc8acd@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/b= oot/dts/samsung/exynos5800-peach-pi.dts index f91bc4ae008e4..9bbbdce9103a6 100644 --- a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ cros_ec: cros-ec@0 { reg =3D <0>; spi-max-frequency =3D <3125000>; google,has-vbc-nvram; + wakeup-source; =20 controller-data { samsung,spi-feedback-delay =3D <1>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEB99111A8 for ; Tue, 26 Dec 2023 19:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BRVMLh/5" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7ba834684abso248667339f.2 for ; Tue, 26 Dec 2023 11:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618530; x=1704223330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=72Y9hKrM6wg7C/dkdJ1azVBKmo9vO5yjLJYb3Lbo8g8=; b=BRVMLh/5XH6oixuKamI/PIb5hC/lBLPhi6BkEogj5+8EKQdVa9IXllD7ZynnPt7ozp AcL1QPGuVoIJd59bU51BnN33FVw/1qMSgjnl1JueHW+F66qVjRKkxBuiQ2Lj0pR+t/iC RQsv8MRSJdxkyyHNgEcjIIJQu6vDH9d3Yp/A8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618530; x=1704223330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=72Y9hKrM6wg7C/dkdJ1azVBKmo9vO5yjLJYb3Lbo8g8=; b=Vi2oeUNhh8TR2Xga9u8RFlQ+XAnSY5UopDbPjcNk3In0Ha9lgrHcCDEUyE8arTPwqQ 9rYFY4YeZ+VJdxeB3MBykbHc+btJrvl7Gu5cxBgD2bN2oj9z606AndetZIQkfHQgqEZO 131HivI9OcF63wi0nrfd5UIlwl+xOeCeRfjk2tSxTANrERrZOXq332CeSRRhhJqrSL6i dMnq8WEYb3YEVXBRLwDTehxDXpyfQMt6DzAKMzrAsFkgdyJ/JD2VkNuSCDab2FVwexZ5 ECVVu/HeB5sP1SiHc30lnMnSlA1IU9OLgH59bdYIJlMABusBHo0ifYEKo0yP3WTKWm/j lrzg== X-Gm-Message-State: AOJu0Yz3cs9B4gvn8EgbJe5IUVYmyjkWVRc4RFL1sCbf0mWu6dgQuEPi Dd8plgHQYc7b0GVAvp0Ilhp5dOQ4AvCusJRD/v0cIJxAKW/F X-Google-Smtp-Source: AGHT+IF6JaIjJ+4nkw3XKAI7b2qhT+RLQRJF93my4pWqagV6xX2LpANA+cbIE30OOMeWGip9I5fCQg== X-Received: by 2002:a6b:d807:0:b0:7ba:9ad0:657f with SMTP id y7-20020a6bd807000000b007ba9ad0657fmr10906914iob.0.1703618529969; Tue, 26 Dec 2023 11:22:09 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:09 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 09/24] arm64: dts: mediatek: mt8173: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:13 -0700 Message-ID: <20231226122113.v3.9.Ic09ebe116c18e83cc1161f4bb073fea8043f03f3@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot= /dts/mediatek/mt8173-elm.dtsi index 8d614ac2c58ed..335aed42dc9e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1155,6 +1155,7 @@ cros_ec: ec@0 { spi-max-frequency =3D <12000000>; interrupts-extended =3D <&pio 0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay =3D <500>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel0 { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1E5512B6B for ; Tue, 26 Dec 2023 19:22:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="FcVKVBsB" Received: by mail-io1-f46.google.com with SMTP id ca18e2360f4ac-7baa8097064so145754639f.3 for ; Tue, 26 Dec 2023 11:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618530; x=1704223330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h7Ja8Mbk0Dn0paAcqtccJazS/+ZwMfvgkX5xOL8nKJI=; b=FcVKVBsBIzjgccnZnc3m9lv2bIKNpYvewrs/E69Du2Mn8jDtSWs5y7MHDy7NHjXOeb WGu6Jsm1uHbU1jwDHz6RzKPXq4EdtnKBYt8AJQLXzVrc5PmqMQbAITfwY0q1/2X6qO5D 6clq1Db/55aeiKwQAvlEzmpmNKuFzcSV3V0Tk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618530; x=1704223330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h7Ja8Mbk0Dn0paAcqtccJazS/+ZwMfvgkX5xOL8nKJI=; b=s+fzfL1w5gWgAwdw1wLo86Lhq7nkZGg+Zx2UcvY3Eq6/smbzmPTEsqmkUD91fmAkjF pyd7gNRO0yE2d5ftV2ytDBsKLSAEDrMDtfHI/aA3oicoJcv132t8ygFud+vcwFYkni8p OlzY9nnFTpV8rLhj7oox04FbEQZBqqD+IFBO4/0N4FTCtfOa2Tg9UDhMZY2MD15NUMPI g7pCal6nuIRe/cRPE5a1YGB32PPs6rrHJfn+0r9PJI+r1kV4ruwj4rOEnVxeKsnrGJ3g NsSA52Kmn2YgWnuU6yZ5f6SyDwMGu4a0PO+NN0RY0l9CaEfSS+1gJsj5l6p+ihpRhRwn LePA== X-Gm-Message-State: AOJu0YzIcMwwEuhiM8zwx+fR81eqcmQndfmBjdrGfsUhmDUYixlR8916 l/cco/qYI1FKAUmxmgD2HKMDpnkxjxuBJGNlUc1bFxzKjYgh X-Google-Smtp-Source: AGHT+IG8helE4u9r3GeIgnMcwM3YERloc3FZd47BOCTyom2igtFIusFh5HNKk7KvOaUbVJAxoSn/Dw== X-Received: by 2002:a05:6602:3e8b:b0:7ba:a650:13d1 with SMTP id el11-20020a0566023e8b00b007baa65013d1mr9133258iob.10.1703618530770; Tue, 26 Dec 2023 11:22:10 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:10 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 10/24] arm64: dts: mediatek: mt8183: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:14 -0700 Message-ID: <20231226122113.v3.10.Iba4a8b7e908989e57f7838a80013a4062be5e614@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 5506de83f61d4..08261164ab18d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -924,6 +924,7 @@ cros_ec: cros-ec@0 { interrupts-extended =3D <&pio 151 IRQ_TYPE_LEVEL_LOW>; pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_odl>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96CC912E72 for ; Tue, 26 Dec 2023 19:22:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="HkdKktzt" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7b7d55d7717so215336839f.2 for ; Tue, 26 Dec 2023 11:22:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618531; x=1704223331; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ESf+HP/4Pbj+l15SV7DO/QREg1e8QVEjr0ahdi8QujY=; b=HkdKktzt7nt59KOZ+FkuhhdJMdW/AYVTpAwHDp+g0xR53xj3f/gQ4CAHnwzEIMkwa5 u/N5xdQ3l4GBqemrSSn8+/ziF/c30zF7bKzttsUjPs+bWCp7znmxolHrfHVUFbwKB+on 71vjXxguhACFN+7kSGw+VEDxDEpEIyvjYJ/00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618531; x=1704223331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ESf+HP/4Pbj+l15SV7DO/QREg1e8QVEjr0ahdi8QujY=; b=UkG9NuwXoYibQfQa+uCA4QmIlQO7uugOK3aAxecE3105n+ZD2tk5u43eaC4OrUIaHS bG4EVW5aA/rkVFvRKLKZXVbDz7rnPjSqLaCAhVjgKH10oeKNR3hSHOLe+SoxD04APwTQ Bfw9rOaZhmowx052P8RQL9t+olunqj6sLsVq2dKrXth9yqHbjX3zcMzwrdPuqiiwP/aw joaxlo0yjq4Z3IodPaoK67++HN9b1xasXrlINc/35AWuTOpxpPptHMkDDuO9Lxl5RSZ9 vVaeMNfHeFaL+feSuoeC5mI9Pm+ILGCcNM/gPVqa1DPn1fibsXhBbBOSjEbu4jlX0xea SEVA== X-Gm-Message-State: AOJu0YxnubstiCZweRM6h5v3b0P3LXWMRhoJxVg7Qk8XB195O0J9b6LV K4hPqV/OmryKghjGSdhSRu9qMBWPHucyarpZ7z7f0BuXR+pG X-Google-Smtp-Source: AGHT+IHL8LG5CIj6VbEuHzPAo+E1eayG3+anqUkueUhwD4N1X/1qk2RhdEsAN0sRAt9MtvhT5qjugA== X-Received: by 2002:a6b:e714:0:b0:7ba:94cb:aa23 with SMTP id b20-20020a6be714000000b007ba94cbaa23mr8299937ioh.21.1703618531662; Tue, 26 Dec 2023 11:22:11 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:11 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 11/24] arm64: dts: mediatek: mt8192: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:15 -0700 Message-ID: <20231226122113.v3.11.Ibd330d26a00f5e219a7e448452769124833a9762@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index f2281250ac35d..ab44d382f757e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1332,6 +1332,7 @@ cros_ec: ec@0 { spi-max-frequency =3D <3000000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cros_ec_int>; + wakeup-source; =20 #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-il1-f175.google.com (mail-il1-f175.google.com [209.85.166.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BE8C13AC0 for ; Tue, 26 Dec 2023 19:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="KNBDXOTR" Received: by mail-il1-f175.google.com with SMTP id e9e14a558f8ab-35fe756e8dfso6892335ab.1 for ; Tue, 26 Dec 2023 11:22:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618532; x=1704223332; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0O8RtIP4pYk/I1CB5YssfqNJgeBGU8rziw+9z/3E58g=; b=KNBDXOTRa9TRuzLfjN0nENjKHo7jOEfo9jyUYKuYwTjmWVxgkSlM7d96c1C1xHhZjE 40ufDV2ONTWZialao6qgAmqbe4NQvnoynfLafu7HmIrRV8HUrvuNlJCh9uugL/Ls+gC+ tjRr8CtqrpJkg6K6pzxilcH/4NNZA3OpfvZUM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618532; x=1704223332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0O8RtIP4pYk/I1CB5YssfqNJgeBGU8rziw+9z/3E58g=; b=aPXdyyb54m4SlWtgE0Tbm0bScOEcGOYZViV8sPAQQEiGf9/EljT6kS6F731LVUPI+e g7X0BXx9aR9wCBqjjXViixyTBs03NyDdGnX9iM7HIz55gUpNSQd7sI373+Z5RdKYdUN6 qc/0RmtYdA4rF5YSbzY2HNBm1Y5B+dMxcsTWh5e+RXMI/EqhG+EukBnomCOMCoTfv5sF qLK6beHuExZt0qdwVcHgj6Z7iiVywT7u5lnKORFN7kcpgyhhAlhgc9Y50pcczf2yzFFJ pVZo8doCkZnH9NPPyBr/AE/yt4POmbpHE0t+1WXhVuNVZqNBPq1YTYTTU5rIO01CUL8G I7Vg== X-Gm-Message-State: AOJu0YzHvSzkF7vv21O4Dk3pmT6Nj4RPSWB8TNNeNHBD+Lf5Qy2v/RYa vwLRZOldKr2YeZhFPtUhFWvHOoDmPRvS1pyrRzf/nrIDqTlk X-Google-Smtp-Source: AGHT+IEPvjdPgLWnim9CRScF1zgDLSQesNC/8qGs5BHhtwyK/zW05fi43O35+h7z9keU2BUHrJr/5Q== X-Received: by 2002:a05:6e02:1a08:b0:35f:eceb:f845 with SMTP id s8-20020a056e021a0800b0035fecebf845mr4107785ild.8.1703618532594; Tue, 26 Dec 2023 11:22:12 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:12 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 12/24] arm64: dts: mediatek: mt8195: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:16 -0700 Message-ID: <20231226122113.v3.12.Iee33a7f1f991408cef372744199026f936bf54e2@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index bbdcd441c049d..2edb270d0bc2f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1149,6 +1149,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&cros_ec_int>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 keyboard-backlight { compatible =3D "google,cros-kbd-led-backlight"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-il1-f169.google.com (mail-il1-f169.google.com [209.85.166.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 462EA1427B for ; Tue, 26 Dec 2023 19:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PKFO3HT0" Received: by mail-il1-f169.google.com with SMTP id e9e14a558f8ab-35fd902c6b5so39598655ab.3 for ; Tue, 26 Dec 2023 11:22:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618533; x=1704223333; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kerU/WuqEcwbTh86F2qAMXgt8ltGJijA7xaRw4oFoNg=; b=PKFO3HT0npEb4BSRVzV0OXAQW/gBQ9NXVu60MjBgwz07ICB5jvLu7sWmWkWZr9cMw2 x9qnIFhv9e4PI+U9amLbSyosSshLZ7cBXGiR8SzymKt5lXCiH/02cAeotp26IvPJaTnf vHSR4yYonNbaR+YkfKmDwQLYO0IagD2ehChe4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618533; x=1704223333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kerU/WuqEcwbTh86F2qAMXgt8ltGJijA7xaRw4oFoNg=; b=kIdedhaOtuJDS71KEUK4RoWk8VVh2sbPDG+cWryeDfpk4pv0n5At/S/Qjc+45hmJi/ rAogJtfX2Let913D05lNGrMPJFN4+4L5PH4ubEYFn9vKqSzaRi9cdTJi1DQzc8I2fLaC XguX/fg5n1obTM541j/9oCsKE2gAPyC9/KnJsOPvR0nb5GXj0MU4PXJ8YJfiaADR27oU a7R+1EIlhxFNUUx+xXghodRCT/RvywcUHjCqqJAzFGjdTFnrtY+aNPaDeckG7WrxjsEq X+cb6BR9b7CNZj24ebO1X9mnvCs8QB22vMHBFx05KW4FWyAAkLJ5iyrUflcca8aRMnNA R01Q== X-Gm-Message-State: AOJu0YwtKrGm7QtcxN2L8LVdZmU2EztfZA51rdNxyABS7cu2cF0x56Hk M3zMmM4RT1xaY4yQSA3cWVP3GdPY7FLKXoK5/6TQ/nXYnY3G X-Google-Smtp-Source: AGHT+IGWPoS9hNB+cORRQA5bdZchS+AQ/9yExQ/zNcqX1Gy8dNr1XcWwi3k5mwg/23JTM3VYG90PnQ== X-Received: by 2002:a05:6e02:160a:b0:35d:6a77:64c9 with SMTP id t10-20020a056e02160a00b0035d6a7764c9mr14636626ilu.37.1703618533422; Tue, 26 Dec 2023 11:22:13 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:13 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring , Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 13/24] arm64: dts: tegra: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:17 -0700 Message-ID: <20231226122113.v3.13.Ic12bf13efe60f9ffaa444126c55a35fbf6c521cc@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/bo= ot/dts/nvidia/tegra132-norrin.dts index bbc2e9bef08da..14d58859bb55c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ ec: cros-ec@0 { interrupt-parent =3D <&gpio>; interrupts =3D ; reg =3D <0>; + wakeup-source; =20 google,cros-ec-spi-msg-delay =3D <2000>; =20 --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36001156C1 for ; Tue, 26 Dec 2023 19:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="lwH5ozb3" Received: by mail-io1-f46.google.com with SMTP id ca18e2360f4ac-7bade847536so84621239f.0 for ; Tue, 26 Dec 2023 11:22:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618534; x=1704223334; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fJeII5b51gSKYdx0OFHNNgnpr2euSDHg7QynlWWpDkw=; b=lwH5ozb3yLiy84322iyB6vejF0bjEUAPClt0LjlK6D6YdaOZrGoKWVHUMzvDHKr9kl SEhhJjGRTK+9DBvFoc7Isvpqi9dBtkN7aNTJzJteuu9H5/tSKRCAXheBHY6zwcNDbKRB FurQCAX0Nfbhc8OpEPUMpj4s9W/ATfdVSeNjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618534; x=1704223334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fJeII5b51gSKYdx0OFHNNgnpr2euSDHg7QynlWWpDkw=; b=wG0WE2fiFI1uEFQOUUvUYaw4VL2GmieOAjU4/qY3KlZh1BRjnerKqJW63beSLx8csz 0MsL/UO85zkHRJi8bwaHyXH3JIfiVnEnJjTHX8tK31lA7DaYJRpYe8rUcSSffgXEs7lc 4rm3eqBCE74j5Mdhp93WWM4QLi8GCdsiTNTPZ0cKq/KgLS7SPnnfn/CzRyTFR0pek303 kV2oEotXHkmQVBvVzU2hfrB9I3nHwRcEbV+Vtrw/bGqn/KJ99vnFk0OafSqCNt0eIyYQ avA3d1ygY3wQy1meHYljwO0RQSmqQrn7S6w2RuW/R0E0N0F+7nTuBR5rk6DMSJPDVRxH NuOA== X-Gm-Message-State: AOJu0Yy+VSw2zm1yJQVJzrQJwybYphfEnoai0D/87vsDXcKwumFf4pAH xBNzOuZ919w1QWyZStQtsWN+Xhn1sqcDoQBOk1Hav7TC9FJG X-Google-Smtp-Source: AGHT+IFW+l6vYtJ1wQeOu4xfaiQEthQFJVyQR2YUwsgACernOoQnKZ0+YPBF19sE1clzCmB/C9/JQw== X-Received: by 2002:a5d:974b:0:b0:7b7:4b32:7986 with SMTP id c11-20020a5d974b000000b007b74b327986mr10235601ioo.27.1703618534234; Tue, 26 Dec 2023 11:22:14 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:14 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 14/24] arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:18 -0700 Message-ID: <20231226122113.v3.14.I2ee94aede9e25932f656c2bdb832be3199fa1291@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index 46aaeba286047..f3a6da8b28901 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -649,6 +649,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD9EE16416 for ; Tue, 26 Dec 2023 19:22:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="mdI896Et" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7ba8e33dd0cso199196139f.0 for ; Tue, 26 Dec 2023 11:22:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618535; x=1704223335; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vAnFSzJDHfNnMpGVaHg6fCPRHIBad/we4YSkuQl5+SM=; b=mdI896EtZtzOvRkvTaOPQTqfohF6Fm12/2OpXEHXUmWE/sIJuXduG3gUqx5fkgLSqz JeEkExwLeZ5142v7EvSCs0Zd/O0MA7orhIsputPVgkj60oADhAUtC/H8XaICo1RcjX6t BVr0OqN6dMzC0n3rF3LMJfvOGxCHsBEvNfUgM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618535; x=1704223335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vAnFSzJDHfNnMpGVaHg6fCPRHIBad/we4YSkuQl5+SM=; b=wBxXUDMWLPsRBkbAZD1GimVFU1XqyoH5E4fsYbuVR7vQ1g81Nzhw+RE43obd6WaRZa 9tjiKX0S1k1HBdf9IepNFVRGUMb02c/6aiZVkdOwbKbw5Kb+fHBmUBVgsuEDlRMEv2Ba s2bNFcmsDAe5OjlUKibLhjg1MJtuP2q+MegkVpQMwtfe716qxOrTi6IHnzuVyEiDHSy8 pxaUKB9q7OiF3k+m9Mk1EWbWpkrK3DFYRe6cpXQ6bipevEEke3ZW13InjFNE0IM7tMO5 eXXf4wVwRBzrNW9rcroT0EcB6n8N/A5tkspnLK+7U+s/LfP1PN3oBc/a1TuyjEOzZaE/ E8fw== X-Gm-Message-State: AOJu0Yyv/PGGA0U83qM7fjvrSLBAM3F+S/nBR1FazAW5eZddoK4GS3Bq rBZ31k94OhvjonVRKCF11PlfzeXRXcvL4DgLpBA57GFOp2Rp X-Google-Smtp-Source: AGHT+IEzBIeiXFU4rn0iqW6wJdrynrvlyiLuDVC+E/J27rd0IXEV8/bD2oBhdXZGlp7zJi8p5eN5NA== X-Received: by 2002:a05:6602:5c8:b0:7ba:8314:cbee with SMTP id w8-20020a05660205c800b007ba8314cbeemr7588062iox.19.1703618535057; Tue, 26 Dec 2023 11:22:15 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:14 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 15/24] arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:19 -0700 Message-ID: <20231226122113.v3.15.I7ea3f53272c9b7cd77633adfd18058ba443eed96@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index 9ea6636125ad9..2ba4ea60cb147 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index ebae545c587c4..fbfac7534d3c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA52A1798E for ; Tue, 26 Dec 2023 19:22:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="MS6sJGkx" Received: by mail-io1-f42.google.com with SMTP id ca18e2360f4ac-7b3708b3eacso211668339f.2 for ; Tue, 26 Dec 2023 11:22:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618536; x=1704223336; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jqUYIaw9tUo9kdqHB2Dv3IsUt9S6YDu3MfPzCVXpIHY=; b=MS6sJGkxdkX0z7x2nxw0xkPNbqiOWCdIBhd26tonRLpr/51eXdzUTj/bhZu2e27vof o2T7mvqG1fV1Ca2kVvHIxLSdzUA/oABGzAXyyA1fMOcY32bHgVt5BwVo6lHbyCHeXelM ZyTij5OUkYf0Hp2bal67qE+yxghYTbSwmnAoM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618536; x=1704223336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jqUYIaw9tUo9kdqHB2Dv3IsUt9S6YDu3MfPzCVXpIHY=; b=X4yoR2SYiaNxixFzqIOVVao2rQwEfv40OAwg4+L8dp/ZtwEHBkMLxbzI+tJvxjpaGn a3/CK5BXJWhWWTqrzaAeyQCbd88G4/c2Pkl7YHFRGI91H1mfP0kXbGi7okj60jvngc2w fSmweUaDGuSmt7nAu246HQNW6a3iUiU39fjan1zs75aePQERF8Y7Jon9c9VcAFgtt0Ow Yw5zFFj0bICXgv3IX1LCql3pl1Hbb7PNg2oqwlnaS9WCTCXRWerFaGM+UglBy4gbesMk 8GYHVvBUejUvmEi4qoiKHNNUvtVa8wF5xmRTceA5zRPVTXyDNKw6PnCjmSE90gWjl6g6 WmNA== X-Gm-Message-State: AOJu0YwY/WQAiKqjIs/MBB/9Lbpn+XLTQAwVbEpYzVHQx8Sdh1uufDHi W6oM2NVNGvHWjrM371yEqxiP2lqVL56LaGSWSVuPiYxfPaZ6 X-Google-Smtp-Source: AGHT+IFj1KB5D+02jkLiHmvX5p2wx9e8GF6AOssDMMgP9jAk68kfSL3ub0MUuBke1AgTXDiucynj9A== X-Received: by 2002:a5d:9557:0:b0:7ba:f96f:8c76 with SMTP id a23-20020a5d9557000000b007baf96f8c76mr1245177ios.35.1703618535947; Tue, 26 Dec 2023 11:22:15 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:15 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Rob Herring , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v3 16/24] arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:20 -0700 Message-ID: <20231226122113.v3.16.I870e2c3490e7fc27a8f6bc41dba23b3dfacd2d13@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index 0ab5e8f53ac9f..e8276db9eabb2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -852,6 +852,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 cros_ec_pwm: pwm { compatible =3D "google,cros-ec-pwm"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f43.google.com (mail-io1-f43.google.com [209.85.166.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF37C1862D for ; Tue, 26 Dec 2023 19:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Tdy72+mN" Received: by mail-io1-f43.google.com with SMTP id ca18e2360f4ac-7bb0ab8e79fso5334739f.1 for ; Tue, 26 Dec 2023 11:22:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618537; x=1704223337; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JesGzUfVYG0N52lEpA2lp9jd0GztoHz5e+Bd1oSHbfw=; b=Tdy72+mNcqjluS9WcMC1i/EDk19WIdQij/W521KpvjXHDYVvZH+U7mctE8mUgRSKLS yE0qXAtT40SP7RQwhw8zFbuW0eNyjKIia45BnsXTtsZ9SxogRwwMsB26mGQzpD5u8SvY 6JgKQU7sZ4mzWdmd0m1oxa0OrTgrfjEQYLJS4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618537; x=1704223337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JesGzUfVYG0N52lEpA2lp9jd0GztoHz5e+Bd1oSHbfw=; b=w9ZA/0Xndw3t3dO65Fo7YjtRt5fkjzug1jpgO2ZgEjNjBjkM5WPOS0tasJh5s7oPXj S37rAZDQRHH/lW88/g1KG2CNd3L761UmaaEVJZulYOKAFvwNZKYq/j8jHSirxkM7/aA3 Cv45hRRTCRmTlMRjEAs71OToeDQkhfuMaBUQj86SP0UVyJu7ESVfznx4wrbay2ie1UXG vbGOuLXXrAJzZMlXZOSpWE0G24h8aD26Z4ppxvgfCzHmGUkCtOL11jxEGsCd/v8v8cOQ O8iTLpaSBsvEWJWkCoO/h+p4CVz5rBofCt/vNOl3EdKnBP/7IA6o39D8tRw5GjpWl1GT goWg== X-Gm-Message-State: AOJu0YwQHySSAK4cMtKZgbH66HU3HF4gzYi3AU35paEtLZyfLQegfJK/ NiBisDhcR5954+22qt3XVWnyJHkJVDdp/6Zpy3nbYqjXTlSW X-Google-Smtp-Source: AGHT+IFnfa01wzCJ7D5u8Art1oX5WIoaHFxESiLKFBDqaU10ovAtJY7dB+V8ZDbbIOFqYtTxSN7xWQ== X-Received: by 2002:a5d:9718:0:b0:7ba:b7da:3cd8 with SMTP id h24-20020a5d9718000000b007bab7da3cd8mr8956064iol.17.1703618536940; Tue, 26 Dec 2023 11:22:16 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:16 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Conor Dooley , Heiko Stuebner , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v3 17/24] arm64: dts: rockchip: rk3399: Enable cros-ec-spi as wake source Date: Tue, 26 Dec 2023 12:21:21 -0700 Message-ID: <20231226122113.v3.17.Ice617703aded22ad4c806459129e1ae693eb57af@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. -Commit-changes: 3 -Update commit message to provide details of the motivation behind the change Signed-off-by: Mark Hasemeyer --- (no changes since v2) Changes in v2: -Split by arch/soc arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 789fd0dcc88ba..b5734e056aef1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -603,6 +603,7 @@ cros_ec: ec@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; + wakeup-source; =20 i2c_tunnel: i2c-tunnel { compatible =3D "google,cros-ec-i2c-tunnel"; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B351618C3B for ; Tue, 26 Dec 2023 19:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="RWv8qcAs" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7b7fdde8b54so249164339f.1 for ; Tue, 26 Dec 2023 11:22:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618538; x=1704223338; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pxmhdaZ3UzecFQENHodwfGETPRP37VNTRDU74oHDCzk=; b=RWv8qcAs2uBHdnfNlufkkGBYghPrJw7pIP95YqvmnCsSj9ZAyAWarxzYnpCBXmFXbX h1MDQjxJ0jj61vXii4tPNSxKf6iZXuBfIsQdjnUP6h1YFAvTEECp2LxBDKCqxY0858at +n9Y3NMZCiH+aUDbdu6pOy918M9OHUaloCqkE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618538; x=1704223338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pxmhdaZ3UzecFQENHodwfGETPRP37VNTRDU74oHDCzk=; b=bvO2lf2eUpYoeEzKzMpVCqPgVHFINVDc5BYW6eXOqI/TrNyVlDd2F87Je7gcTPgQgl Sl9+OWVl7cVCUDG6bG0MPm+rpnzp+vuBMUifwnXB/7m5ZlLn1tqD/NNWZjryDM9hN8JO Q8WArxTbHCJnsPVUDwwKV/+z+tOaoCymrLVrWia1AviX+2t5gX2OxGYMJaOgeKCu9aNU TFtBTxjfxKha2a4swtJZjVkXgNgBZ+v0Aa4O0laKF2Ndq/o04OIiI0FZkL6GM66gFsHp o+8zb8pEEuswR6nNvW+SBltWHQRxcLnxa6lQ3rBdyqwzOHxnTIRehvtDq5w+i7GeSUAr yD2Q== X-Gm-Message-State: AOJu0Yy1t2qJ9aE7oI/B3Qjf1VXLm7XQ2WNAPY9Q8uachI3NTc1jG6eA SJURI25Ww23+TQuNLqrOkr3VzOmwOIJy7iNg7DW3B/RBAVht X-Google-Smtp-Source: AGHT+IEqSgC8hhnx7dR56hSUAn0xu8OJZ2XCJkAuVfhkLlOJtzedd7KZq8eCLrxJSgwWJ7fRF/1kIg== X-Received: by 2002:a05:6602:4908:b0:7ba:b173:502b with SMTP id ef8-20020a056602490800b007bab173502bmr10010919iob.24.1703618537789; Tue, 26 Dec 2023 11:22:17 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:17 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v3 18/24] of: irq: add wake capable bit to of_irq_resource() Date: Tue, 26 Dec 2023 12:21:22 -0700 Message-ID: <20231226122113.v3.18.I29b26a7f3b80fac0a618707446a10b6cc974fdaf@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add wake capability information to the IRQ resource. Wake capability is assumed based on conventions provided in the devicetree wakeup-source binding documentation. An interrupt is considered wake capable if the following are true: 1. A wakeup-source property exits in the same device node as the interrupt. 2. The IRQ is marked as dedicated by setting its interrupt-name to "wakeup". The wakeup-source documentation states that dedicated interrupts can use device specific interrupt names and device drivers are still welcome to use their own naming schemes. This API is provided as a helper if one is willing to conform to the above conventions. The ACPI subsystems already provides similar APIs that allow one to query the wake capability of an IRQ. This brings closer feature parity to the devicetree. Signed-off-by: Mark Hasemeyer Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring --- Changes in v3: -Use DEFINE_RES_IRQ_NAMED_FLAGS macro Changes in v2: -Update logic to return true only if wakeup-source property and "wakeup" interrupt-name are defined -irq->IRQ, api->API drivers/of/irq.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 174900072c18c..cdecdc3515f88 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -383,11 +383,39 @@ int of_irq_parse_one(struct device_node *device, int = index, struct of_phandle_ar } EXPORT_SYMBOL_GPL(of_irq_parse_one); =20 +/** + * __of_irq_wake_capable - Determine whether a given IRQ index is wake cap= able + * + * The IRQ is considered wake capable if the following are true: + * 1. wakeup-source property exists + * 2. provided IRQ index is labelled as a dedicated wakeirq + * + * This logic assumes the provided IRQ index is valid. + * + * @dev: pointer to device tree node + * @index: zero-based index of the IRQ + * Return: True if provided IRQ index for #dev is wake capable. False othe= rwise. + */ +static bool __of_irq_wake_capable(const struct device_node *dev, int index) +{ + int wakeindex; + + if (!of_property_read_bool(dev, "wakeup-source")) + return false; + + wakeindex =3D of_property_match_string(dev, "interrupt-names", "wakeup"); + return wakeindex >=3D 0 && wakeindex =3D=3D index; +} + /** * of_irq_to_resource - Decode a node's IRQ and return it as a resource * @dev: pointer to device tree node - * @index: zero-based index of the irq + * @index: zero-based index of the IRQ * @r: pointer to resource structure to return result into. + * + * Return: Linux IRQ number on success, or 0 on the IRQ mapping failure, or + * -EPROBE_DEFER if the IRQ domain is not yet created, or error code in ca= se + * of any other failure. */ int of_irq_to_resource(struct device_node *dev, int index, struct resource= *r) { @@ -399,6 +427,7 @@ int of_irq_to_resource(struct device_node *dev, int ind= ex, struct resource *r) /* Only dereference the resource if both the * resource and the irq are valid. */ if (r && irq) { + u32 irq_flags; const char *name =3D NULL; =20 memset(r, 0, sizeof(*r)); @@ -409,9 +438,11 @@ int of_irq_to_resource(struct device_node *dev, int in= dex, struct resource *r) of_property_read_string_index(dev, "interrupt-names", index, &name); =20 - r->start =3D r->end =3D irq; - r->flags =3D IORESOURCE_IRQ | irqd_get_trigger_type(irq_get_irq_data(irq= )); - r->name =3D name ? name : of_node_full_name(dev); + irq_flags =3D irqd_get_trigger_type(irq_get_irq_data(irq)); + if (__of_irq_wake_capable(dev, index)) + irq_flags |=3D IORESOURCE_IRQ_WAKECAPABLE; + + *r =3D DEFINE_RES_IRQ_NAMED_FLAGS(irq, name ?: of_node_full_name(dev), i= rq_flags); } =20 return irq; --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60FC018EAB for ; Tue, 26 Dec 2023 19:22:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="FO7BKyE9" Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7ba737ee9b5so363194539f.0 for ; Tue, 26 Dec 2023 11:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618538; x=1704223338; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dhThlCXf4PlI+V7Ie+OwgPGYRnxlVhq49B6FDf9+u+w=; b=FO7BKyE98Gq3AYO7PzsQI/wCt5Fz/LrbnBEKuzwakCl+pkyybFs7CUNCaGd3TF72oQ JiOazGyCpAzTT3+W1sbfFQZ08usWpnx/aon3JYjtPiGCUOx0AX7FI4ZjjIoU4zo0Nkeg TC46+hRik18wYf5firvJfO0CTQexqeO01Hqnk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618538; x=1704223338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dhThlCXf4PlI+V7Ie+OwgPGYRnxlVhq49B6FDf9+u+w=; b=c91oyDi8qAHL1owWhjyjVwGYoJqmvjns8WPkjK1faHkH3axW8TG+iQ0XVjj/dtksLc CTTw6DfeYJDbtSRlM5lZusYPSIb0HB444EKITgYEiZIcmoy1kJRDuByTdiNzz9PuHiFD lpk3kBAcvCnuD4KyGzl0Xdj/YFAbfyzz6WZjU5WQH96q5aIbz1DOfMSqqcUtU0nxfAFP oE/mrLnfbr5On27FgfnSRAw9zKS6fSCHPIjS03qS+MUwAARqKoR0feswkPHoSaij5M78 DQWGfyvNRNYi8jhSnU8VNyKZuZ75FGDgucfqZy8w2W/YcS9TI59YmTSDglFnTirQ9Q6N bzVA== X-Gm-Message-State: AOJu0Yxp4fLoG0+dZvb1ZO90F1B7BM0qSRr46ulUujliz6ZIJuqXWnnl BgMoC0E/l2eMrpg86rk1V5aFVGqOs3+hwWUl+iitpykKwu10 X-Google-Smtp-Source: AGHT+IG+oBvf736p4CYnXNTAe9f7VKS0Qra4N66ekMcdhT2xg9kaGf/7l7hmK3fXMidgrhCoUTrIkQ== X-Received: by 2002:a6b:e80d:0:b0:7b3:9356:665 with SMTP id f13-20020a6be80d000000b007b393560665mr10502815ioh.4.1703618538568; Tue, 26 Dec 2023 11:22:18 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:18 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v3 19/24] of: irq: Add default implementation for of_irq_to_resource() Date: Tue, 26 Dec 2023 12:21:23 -0700 Message-ID: <20231226122113.v3.19.I31d4dd6a7e5a3e5eee05c87b358e63cd1aa0e467@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to of_irq_to_resource_table(), add a default implementation of of_irq_to_resource() for systems that don't have CONFIG_OF_IRQ defined. Signed-off-by: Mark Hasemeyer Acked-by: Rob Herring --- (no changes since v2) Changes in v2: -None include/linux/of_irq.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index d6d3eae2f1452..0d73b2ca92d31 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -34,8 +34,6 @@ static inline int of_irq_parse_oldworld(const struct devi= ce_node *device, int in =20 extern int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *ou= t_irq); extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data= ); -extern int of_irq_to_resource(struct device_node *dev, int index, - struct resource *r); =20 #ifdef CONFIG_OF_IRQ extern void of_irq_init(const struct of_device_id *matches); @@ -44,6 +42,7 @@ extern int of_irq_parse_one(struct device_node *device, i= nt index, extern int of_irq_count(struct device_node *dev); extern int of_irq_get(struct device_node *dev, int index); extern int of_irq_get_byname(struct device_node *dev, const char *name); +extern int of_irq_to_resource(struct device_node *dev, int index, struct r= esource *r); extern int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs); extern struct device_node *of_irq_find_parent(struct device_node *child); @@ -76,6 +75,11 @@ static inline int of_irq_get_byname(struct device_node *= dev, const char *name) { return 0; } +static inline int of_irq_to_resource(struct device_node *dev, int index, + struct resource *r) +{ + return 0; +} static inline int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs) { --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4572718EDA for ; Tue, 26 Dec 2023 19:22:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="fCnWs/2R" Received: by mail-io1-f52.google.com with SMTP id ca18e2360f4ac-7b7fe0ae57bso282940339f.0 for ; Tue, 26 Dec 2023 11:22:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618539; x=1704223339; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WGEOA7VnVi81L2sEgap1qKk2oI4GW7FWt/PKKqipwFA=; b=fCnWs/2RPcwyS4r+8mm40SUREOvOYuS/hgHs9WpcYGgE4tILMBxqFZOHCUfFGmgH6e w5qyDxkpcAaDNhixYqLnFqBdEVug3YZaAgU+FS4j+ckG0UZqSJR7L9F42PnvQzlyLdk9 E2iSsyTZxGk+YyqkX/vaCWu0U3VPmwz/r4hLs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618539; x=1704223339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WGEOA7VnVi81L2sEgap1qKk2oI4GW7FWt/PKKqipwFA=; b=wwxbMHWX0+Z6IujyVBBS+QlGwClEo9XjOQcvDSDL5AeKy/JCGBYSj/j+bjZO3nLTJ5 61rA59qutvB9DRgzlF1QY/oGTJOJekYLHDJf+03rOT99Fd6DnDVAZGd/jhlfkxgSi3lM qIpDc77UgWYWxvtZu/8w4e01SSVn1uJMkVIP+VOAOZitQJcgoaLzkBvQiLr6CakleiLU 9sHSnhredBapwLLioyKFMJm+fMU+zoQfUJOj8BT8ZDi9265xHo0Q/lScyk1PdVMpEQ+U Fb8S1deIu0pnzDPPSS8zVkVRAKvusk7GhX+GIWBT1r8KXroJQcBBgbFdcC/AdoroovjG HK3g== X-Gm-Message-State: AOJu0Yy0wDgjw8eRlN0uBLU4Wyegg4JFc0CQXX2Twx2d1pUWcSdy1PmF Ke2fcrA9OydO4aNowJxfkC62SPvpBqDbq1cTu/3AgW5ecM+l X-Google-Smtp-Source: AGHT+IGwo5chhqjsS60uLPxsZz7Aue5NMBmLwETHgxYW043SgR4k4mm2O7+bTWAEs3KDxRW8UynYJQ== X-Received: by 2002:a05:6602:1492:b0:7ba:9707:67ad with SMTP id a18-20020a056602149200b007ba970767admr14464146iow.28.1703618539365; Tue, 26 Dec 2023 11:22:19 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:19 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Frank Rowand , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v3 20/24] of: irq: Remove extern from function declarations Date: Tue, 26 Dec 2023 12:21:24 -0700 Message-ID: <20231226122113.v3.20.I319e781c11e6352eb5b6c408dc20bd54a720edbf@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The extern keyword is implicit for function declarations. Remove it where possible and adjust the line wrapping accordingly. Signed-off-by: Mark Hasemeyer Acked-by: Rob Herring --- (no changes since v2) Changes in v2: -New patch include/linux/of_irq.h | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index 0d73b2ca92d31..a130dcbc4bb45 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -32,27 +32,26 @@ static inline int of_irq_parse_oldworld(const struct de= vice_node *device, int in } #endif /* CONFIG_PPC32 && CONFIG_PPC_PMAC */ =20 -extern int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *ou= t_irq); -extern unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data= ); +int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq); +unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data); =20 #ifdef CONFIG_OF_IRQ -extern void of_irq_init(const struct of_device_id *matches); -extern int of_irq_parse_one(struct device_node *device, int index, - struct of_phandle_args *out_irq); -extern int of_irq_count(struct device_node *dev); -extern int of_irq_get(struct device_node *dev, int index); -extern int of_irq_get_byname(struct device_node *dev, const char *name); -extern int of_irq_to_resource(struct device_node *dev, int index, struct r= esource *r); -extern int of_irq_to_resource_table(struct device_node *dev, - struct resource *res, int nr_irqs); -extern struct device_node *of_irq_find_parent(struct device_node *child); -extern struct irq_domain *of_msi_get_domain(struct device *dev, +void of_irq_init(const struct of_device_id *matches); +int of_irq_parse_one(struct device_node *device, int index, + struct of_phandle_args *out_irq); +int of_irq_count(struct device_node *dev); +int of_irq_get(struct device_node *dev, int index); +int of_irq_get_byname(struct device_node *dev, const char *name); +int of_irq_to_resource(struct device_node *dev, int index, struct resource= *r); +int of_irq_to_resource_table(struct device_node *dev, struct resource *res, + int nr_irqs); +struct device_node *of_irq_find_parent(struct device_node *child); +struct irq_domain *of_msi_get_domain(struct device *dev, struct device_node *np, enum irq_domain_bus_token token); -extern struct irq_domain *of_msi_map_get_device_domain(struct device *dev, - u32 id, - u32 bus_token); -extern void of_msi_configure(struct device *dev, struct device_node *np); +struct irq_domain *of_msi_map_get_device_domain(struct device *dev, u32 id, + u32 bus_token); +void of_msi_configure(struct device *dev, struct device_node *np); u32 of_msi_map_id(struct device *dev, struct device_node *msi_np, u32 id_i= n); #else static inline void of_irq_init(const struct of_device_id *matches) @@ -117,7 +116,7 @@ static inline u32 of_msi_map_id(struct device *dev, * implements it differently. However, the prototype is the same for all, * so declare it here regardless of the CONFIG_OF_IRQ setting. */ -extern unsigned int irq_of_parse_and_map(struct device_node *node, int ind= ex); +unsigned int irq_of_parse_and_map(struct device_node *node, int index); =20 #else /* !CONFIG_OF && !CONFIG_SPARC */ static inline unsigned int irq_of_parse_and_map(struct device_node *dev, --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25834199CB for ; Tue, 26 Dec 2023 19:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="hNDoIHpw" Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7bb0af58166so2864239f.1 for ; Tue, 26 Dec 2023 11:22:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618540; x=1704223340; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X62kSUMdAd2TsFVgmakpOFBG3rZ/IiZ8YTHPEgONzYQ=; b=hNDoIHpwFE5bZVAbjzQfmsTmFtUMZrVxHmdYD8J6ZIRE/HSu63C+OGq+pNIuci8MIg uI4VGzx/OpA7RffB2fNi4aA2fxhFA/jeAX2BmSLa6v9NMVxhEKuYyn8EcqhKdGwE6eqk prbRv1TFM1k/PB7IxzLoGLKKyCUMm7Jk/4uGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618540; x=1704223340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X62kSUMdAd2TsFVgmakpOFBG3rZ/IiZ8YTHPEgONzYQ=; b=c2uv0mFLh0tKNR7UbuPNtQqpK2YjAWLmy/ITXRO6OZSqJ88WbmBm5M26XGKQ7Ht4Uu paswjcd33bsbM7M42OKJh6Yo0ABqiAT50MuCXSeXjX4SIphGHtxAj00Z/kwO7R+6shrv A+UkkOVxA8Z/mkBq5TykVJjHGwkP1iu4nKhqXII8XszvVz56gV0ccs2GiGy4lzT+YFwM +I66LMMhvMGYGhRKpzgY2vg8RxOBkaYf9ifB6ABNEqDlWfnLT2j7Bx6a6/hS26fgj1fJ 33hiHC8Lk3qk/cJDtn2BNPlivIEFfUIdTeNxLfdTqVka6O74pNdFUJEaol4Ov4d1atHR 4W6w== X-Gm-Message-State: AOJu0Yy0ppWtlqXtuPMQf+Id//zNvh9JNO+9qgD/mGm1+t4t5I9cMyPn APGSFFs3A9b5VGnbMWIbmh7yuH+SAepfpp9eeeNj5dO0ABnW X-Google-Smtp-Source: AGHT+IFcEJNCoiiMo8Qg++YCcAfKZRPQPBres6GJ9EPuoiGHGo0ZyDEn4ctqFj/q1mAJJoPuqiqTBg== X-Received: by 2002:a05:6602:1b86:b0:7ba:bd87:5404 with SMTP id dq6-20020a0566021b8600b007babd875404mr3390061iob.14.1703618540260; Tue, 26 Dec 2023 11:22:20 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:20 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Andy Shevchenko , Daniel Scally , Frank Rowand , Greg Kroah-Hartman , Heikki Krogerus , Len Brown , "Rafael J. Wysocki" , Rob Herring , Sakari Ailus , devicetree@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH v3 21/24] device property: Modify fwnode irq_get() to use resource Date: Tue, 26 Dec 2023 12:21:25 -0700 Message-ID: <20231226122113.v3.21.I38ac58ab04985a404ed6551eb5813fa7841ef410@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The underlying ACPI and OF subsystems provide their own APIs which provide IRQ information as a struct resource. This allows callers to get more information about the IRQ by looking at the resource flags. For example, whether or not an IRQ is wake capable. Suggested-by: Andy Shevchenko Signed-off-by: Mark Hasemeyer --- Changes in v3: -Add Suggested-by tag -Initialize struct resource to 0 on stack -EXPORT_SYMBOL()->EXPORT_SYMBOL_GPL() -Remove extra space in commit message -Reformat fwnode_irq_get_resource() declaration Changes in v2: -New patch drivers/acpi/property.c | 11 +++++------ drivers/base/property.c | 24 +++++++++++++++++++++--- drivers/of/property.c | 8 ++++---- include/linux/fwnode.h | 8 +++++--- include/linux/property.h | 2 ++ 5 files changed, 37 insertions(+), 16 deletions(-) diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index a6ead5204046b..891fff5a16797 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -1627,17 +1627,16 @@ static int acpi_fwnode_graph_parse_endpoint(const s= truct fwnode_handle *fwnode, return 0; } =20 -static int acpi_fwnode_irq_get(const struct fwnode_handle *fwnode, - unsigned int index) +static int acpi_fwnode_irq_get_resource(const struct fwnode_handle *fwnode= , unsigned int index, + struct resource *r) { - struct resource res; int ret; =20 - ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, &res); + ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), index, r); if (ret) return ret; =20 - return res.start; + return r->start; } =20 #define DECLARE_ACPI_FWNODE_OPS(ops) \ @@ -1664,7 +1663,7 @@ static int acpi_fwnode_irq_get(const struct fwnode_ha= ndle *fwnode, acpi_graph_get_remote_endpoint, \ .graph_get_port_parent =3D acpi_fwnode_get_parent, \ .graph_parse_endpoint =3D acpi_fwnode_graph_parse_endpoint, \ - .irq_get =3D acpi_fwnode_irq_get, \ + .irq_get_resource =3D acpi_fwnode_irq_get_resource, \ }; \ EXPORT_SYMBOL_GPL(ops) =20 diff --git a/drivers/base/property.c b/drivers/base/property.c index a1b01ab420528..441899171d19d 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -1047,23 +1047,41 @@ void __iomem *fwnode_iomap(struct fwnode_handle *fw= node, int index) EXPORT_SYMBOL(fwnode_iomap); =20 /** - * fwnode_irq_get - Get IRQ directly from a fwnode + * fwnode_irq_get_resource - Get IRQ directly from a fwnode and populate + * the resource struct * @fwnode: Pointer to the firmware node * @index: Zero-based index of the IRQ + * @r: Pointer to resource to populate with IRQ information. * * Return: Linux IRQ number on success. Negative errno on failure. */ -int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index) +int fwnode_irq_get_resource(const struct fwnode_handle *fwnode, unsigned i= nt index, + struct resource *r) { int ret; =20 - ret =3D fwnode_call_int_op(fwnode, irq_get, index); + ret =3D fwnode_call_int_op(fwnode, irq_get_resource, index, r); /* We treat mapping errors as invalid case */ if (ret =3D=3D 0) return -EINVAL; =20 return ret; } +EXPORT_SYMBOL_GPL(fwnode_irq_get_resource); + +/** + * fwnode_irq_get - Get IRQ directly from a fwnode + * @fwnode: Pointer to the firmware node + * @index: Zero-based index of the IRQ + * + * Return: Linux IRQ number on success. Negative errno on failure. + */ +int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index) +{ + struct resource r =3D {}; + + return fwnode_irq_get_resource(fwnode, index, &r); +} EXPORT_SYMBOL(fwnode_irq_get); =20 /** diff --git a/drivers/of/property.c b/drivers/of/property.c index afdaefbd03f61..864ea5fa5702b 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1425,10 +1425,10 @@ static void __iomem *of_fwnode_iomap(struct fwnode_= handle *fwnode, int index) #endif } =20 -static int of_fwnode_irq_get(const struct fwnode_handle *fwnode, - unsigned int index) +static int of_fwnode_irq_get_resource(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r) { - return of_irq_get(to_of_node(fwnode), index); + return of_irq_to_resource(to_of_node(fwnode), index, r); } =20 static int of_fwnode_add_links(struct fwnode_handle *fwnode) @@ -1469,7 +1469,7 @@ const struct fwnode_operations of_fwnode_ops =3D { .graph_get_port_parent =3D of_fwnode_graph_get_port_parent, .graph_parse_endpoint =3D of_fwnode_graph_parse_endpoint, .iomap =3D of_fwnode_iomap, - .irq_get =3D of_fwnode_irq_get, + .irq_get_resource =3D of_fwnode_irq_get_resource, .add_links =3D of_fwnode_add_links, }; EXPORT_SYMBOL_GPL(of_fwnode_ops); diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h index 2a72f55d26eb8..716ed863acde0 100644 --- a/include/linux/fwnode.h +++ b/include/linux/fwnode.h @@ -9,10 +9,11 @@ #ifndef _LINUX_FWNODE_H_ #define _LINUX_FWNODE_H_ =20 -#include -#include #include #include +#include +#include +#include =20 struct fwnode_operations; struct device; @@ -164,7 +165,8 @@ struct fwnode_operations { int (*graph_parse_endpoint)(const struct fwnode_handle *fwnode, struct fwnode_endpoint *endpoint); void __iomem *(*iomap)(struct fwnode_handle *fwnode, int index); - int (*irq_get)(const struct fwnode_handle *fwnode, unsigned int index); + int (*irq_get_resource)(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r); int (*add_links)(struct fwnode_handle *fwnode); }; =20 diff --git a/include/linux/property.h b/include/linux/property.h index e6516d0b7d52a..685ba72a8ce9e 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -190,6 +190,8 @@ struct fwnode_handle *fwnode_handle_get(struct fwnode_h= andle *fwnode); void fwnode_handle_put(struct fwnode_handle *fwnode); =20 int fwnode_irq_get(const struct fwnode_handle *fwnode, unsigned int index); +int fwnode_irq_get_resource(const struct fwnode_handle *fwnode, + unsigned int index, struct resource *r); int fwnode_irq_get_byname(const struct fwnode_handle *fwnode, const char *= name); =20 unsigned int device_get_child_node_count(const struct device *dev); --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 042D31A5B6 for ; Tue, 26 Dec 2023 19:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; 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[71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:20 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Sakari Ailus , Andy Shevchenko , Daniel Scally , Greg Kroah-Hartman , Heikki Krogerus , "Rafael J. Wysocki" , linux-acpi@vger.kernel.org Subject: [PATCH v3 22/24] device property: Update functions to use EXPORT_SYMBOL_GPL Date: Tue, 26 Dec 2023 12:21:26 -0700 Message-ID: <20231226122113.v3.22.I186bc5737c5ac4c3a5a7a91e9ec75645e723ca7b@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the exported functions use EXPORT_SYMBOL instead of EXPORT_SYMBOL_GPL and are inconsistent with the other exported functions in the module. The underlying APCI/OF struct fwnode_operations implementations are also exported via EXPORT_SYMBOL_GPL. Update them to use the EXPORT_SYMBOL_GPL macro. Suggested-by: Sakari Ailus Signed-off-by: Mark Hasemeyer Reviewed-by: Andy Shevchenko --- Changes in v3: -New patch drivers/base/property.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/base/property.c b/drivers/base/property.c index 441899171d19d..4f686516cac82 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -1044,7 +1044,7 @@ void __iomem *fwnode_iomap(struct fwnode_handle *fwno= de, int index) { return fwnode_call_ptr_op(fwnode, iomap, index); } -EXPORT_SYMBOL(fwnode_iomap); +EXPORT_SYMBOL_GPL(fwnode_iomap); =20 /** * fwnode_irq_get_resource - Get IRQ directly from a fwnode and populate @@ -1082,7 +1082,7 @@ int fwnode_irq_get(const struct fwnode_handle *fwnode= , unsigned int index) =20 return fwnode_irq_get_resource(fwnode, index, &r); } -EXPORT_SYMBOL(fwnode_irq_get); +EXPORT_SYMBOL_GPL(fwnode_irq_get); =20 /** * fwnode_irq_get_byname - Get IRQ from a fwnode using its name @@ -1110,7 +1110,7 @@ int fwnode_irq_get_byname(const struct fwnode_handle = *fwnode, const char *name) =20 return fwnode_irq_get(fwnode, index); } -EXPORT_SYMBOL(fwnode_irq_get_byname); +EXPORT_SYMBOL_GPL(fwnode_irq_get_byname); =20 /** * fwnode_graph_get_next_endpoint - Get next endpoint firmware node @@ -1355,7 +1355,7 @@ int fwnode_graph_parse_endpoint(const struct fwnode_h= andle *fwnode, =20 return fwnode_call_int_op(fwnode, graph_parse_endpoint, endpoint); } -EXPORT_SYMBOL(fwnode_graph_parse_endpoint); +EXPORT_SYMBOL_GPL(fwnode_graph_parse_endpoint); =20 const void *device_get_match_data(const struct device *dev) { --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E63E51C2B3 for ; Tue, 26 Dec 2023 19:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="bHItEUsm" Received: by mail-io1-f50.google.com with SMTP id ca18e2360f4ac-7ba8e33dd0cso199200339f.0 for ; Tue, 26 Dec 2023 11:22:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618542; x=1704223342; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K6tsT/7sNyFm2KzBYrGyHG8VbifTdBXO1YqorM6Zb+w=; b=bHItEUsmLdLELfxu2a7Vav32ZUZKFGm/r2pKp6NddrvcTDMD3tUiN6xgdz9R+y0EOG 9mKwOb6vsMh/rGTBpfcAa0V1Z1YVYUvUJd8ORvZJJazCURZhu+NpdsN4IRKwXRZ/wA2h 77xCpoxKFfUUdwBxSQe4jk7WoRyn2g8hWI6Zo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618542; x=1704223342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K6tsT/7sNyFm2KzBYrGyHG8VbifTdBXO1YqorM6Zb+w=; b=NQSZym0Ox+lOFwcZsYEd4+Rp2ly61X0Jt73xCCu6wv9DNL5C/auAV06YVJkGz2Iumw Ydrxkas3DnpZaoyGYee+T08w7yk3FwUOItC0qqcez/61R5ZzHaIA6A6af/hbcgHT3y3O GS+T2pPyQaJu6iZ9lIF8SdInGcMm4BTV5wJBWklvB2UWkb4niiUEeVQefZsR0YBhHgES KfME+hSKl8u/yutS8rExZvbkIgdI9A9R/qdlhS+xf5ZjNUjm8QAIcLXfk3HG8KnTAa5/ fvUp876GRmqvNRZ/xZI7n7FHeAOijI4XRyCmPwfXPPKm8LIjKog8V33jEyvxTrDJWwJB kO6Q== X-Gm-Message-State: AOJu0YwaEVNLluhovCW5/bBn8REuEmBJq6KGEgWmN7IHiQIhB24CHfMS XbiDwbsZWs0NDOZXE9m26paMecvHkEURkwh3BEQ0d8nJRSx5 X-Google-Smtp-Source: AGHT+IERechMaC3iD6M6tDF0p2jDjZ84jAh0OVsFAvat03jaAmnhahDwtdIVJI6dxXkg63oXuGThoA== X-Received: by 2002:a05:6602:181a:b0:7ba:9ac4:3a49 with SMTP id t26-20020a056602181a00b007ba9ac43a49mr8155131ioh.17.1703618541957; Tue, 26 Dec 2023 11:22:21 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:21 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , David Gow , Greg Kroah-Hartman , Mark Brown , "Rafael J. Wysocki" , Takashi Iwai , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Subject: [PATCH v3 23/24] platform: Modify platform_get_irq_optional() to use resource Date: Tue, 26 Dec 2023 12:21:27 -0700 Message-ID: <20231226122113.v3.23.Ife9ebad2bbfbab3a05e90040f344d750aa0aac7e@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unify handling of ACPI, GPIO, devictree, and platform resource interrupts in platform_get_irq_optional(). Each of these subsystems provide their own APIs which provide IRQ information as a struct resource. This simplifies the logic of the function and allows callers to get more information about the IRQ by looking at the resource flags. For example, whether or not an IRQ is wake capable. Signed-off-by: Mark Hasemeyer Reviewed-by: Andy Shevchenko --- Changes in v3: -Remove PTR_ERR check -Move platform_res assignment -Check for irq =3D=3D 0 to trigger WARN msg -Refactor error handling of acpi_dev_get_gpio_irq_resource() to be consistent with fwnode_irq_get_resource() -Remove extra blank lines -Initialize struct resource on stack Changes in v2: -irq->IRQ -Remove cast to struct resource -Conform to get_optional() function naming -Revert move of irq_get_irq_data() -Add NULL check on struct resource* -Use fwnode to retrieve IRQ for DT/ACPI drivers/base/platform.c | 70 ++++++++++++++++++++++----------- include/linux/platform_device.h | 3 ++ 2 files changed, 51 insertions(+), 22 deletions(-) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 10c5779634182..bb6ece1303746 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -151,9 +151,11 @@ EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource_bynam= e); #endif /* CONFIG_HAS_IOMEM */ =20 /** - * platform_get_irq_optional - get an optional IRQ for a device + * platform_get_irq_resource_optional - get an optional IRQ for a device a= nd + * populate the resource struct * @dev: platform device * @num: IRQ number index + * @r: pointer to resource to populate with IRQ information. * * Gets an IRQ for a platform device. Device drivers should check the retu= rn * value for errors so as to not pass a negative integer value to the @@ -162,39 +164,33 @@ EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource_byna= me); * * For example:: * - * int irq =3D platform_get_irq_optional(pdev, 0); + * int irq =3D platform_get_irq_resource_optional(pdev, 0, &res); * if (irq < 0) * return irq; * * Return: non-zero IRQ number on success, negative error number on failur= e. */ -int platform_get_irq_optional(struct platform_device *dev, unsigned int nu= m) +int platform_get_irq_resource_optional(struct platform_device *dev, + unsigned int num, struct resource *r) { int ret; + + if (!r) + return -EINVAL; #ifdef CONFIG_SPARC /* sparc does not have irqs represented as IORESOURCE_IRQ resources */ if (!dev || num >=3D dev->archdata.num_irqs) goto out_not_found; ret =3D dev->archdata.irqs[num]; + if (ret > 0) + *r =3D DEFINE_RES_IRQ(ret); goto out; #else struct fwnode_handle *fwnode =3D dev_fwnode(&dev->dev); - struct resource *r; - - if (is_of_node(fwnode)) { - ret =3D of_irq_get(to_of_node(fwnode), num); - if (ret > 0 || ret =3D=3D -EPROBE_DEFER) - goto out; - } =20 - r =3D platform_get_resource(dev, IORESOURCE_IRQ, num); - if (is_acpi_device_node(fwnode)) { - if (r && r->flags & IORESOURCE_DISABLED) { - ret =3D acpi_irq_get(ACPI_HANDLE_FWNODE(fwnode), num, r); - if (ret) - goto out; - } - } + ret =3D fwnode_irq_get_resource(fwnode, num, r); + if (ret >=3D 0 || ret =3D=3D -EPROBE_DEFER) + goto out; =20 /* * The resources may pass trigger flags to the irqs that need @@ -202,7 +198,9 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) * IORESOURCE_BITS correspond 1-to-1 to the IRQF_TRIGGER* * settings. */ - if (r && r->flags & IORESOURCE_BITS) { + struct resource *platform_res =3D platform_get_resource(dev, IORESOURCE_I= RQ, num); + + if (platform_res && platform_res->flags & IORESOURCE_BITS) { struct irq_data *irqd; =20 irqd =3D irq_get_irq_data(r->start); @@ -211,7 +209,8 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) irqd_set_trigger_type(irqd, r->flags & IORESOURCE_BITS); } =20 - if (r) { + if (platform_res) { + *r =3D *platform_res; ret =3D r->start; goto out; } @@ -224,7 +223,8 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) * allows a common code path across either kind of resource. */ if (num =3D=3D 0 && is_acpi_device_node(fwnode)) { - ret =3D acpi_dev_gpio_irq_get(to_acpi_device_node(fwnode), num); + ret =3D acpi_dev_get_gpio_irq_resource(to_acpi_device_node(fwnode), NULL= , num, r); + ret =3D ret ?: r->start; /* Our callers expect -ENXIO for missing IRQs. */ if (ret >=3D 0 || ret =3D=3D -EPROBE_DEFER) goto out; @@ -238,7 +238,7 @@ int platform_get_irq_optional(struct platform_device *d= ev, unsigned int num) return -EINVAL; return ret; } -EXPORT_SYMBOL_GPL(platform_get_irq_optional); +EXPORT_SYMBOL_GPL(platform_get_irq_resource_optional); =20 /** * platform_get_irq - get an IRQ for a device @@ -270,6 +270,32 @@ int platform_get_irq(struct platform_device *dev, unsi= gned int num) } EXPORT_SYMBOL_GPL(platform_get_irq); =20 +/** + * platform_get_irq_optional - get an optional IRQ for a device + * @dev: platform device + * @num: IRQ number index + * + * Gets an IRQ for a platform device. Device drivers should check the retu= rn + * value for errors so as to not pass a negative integer value to the + * request_irq() APIs. This is the same as platform_get_irq(), except that= it + * does not print an error message if an IRQ can not be obtained. + * + * For example:: + * + * int irq =3D platform_get_irq_optional(pdev, 0); + * if (irq < 0) + * return irq; + * + * Return: non-zero IRQ number on success, negative error number on failur= e. + */ +int platform_get_irq_optional(struct platform_device *dev, unsigned int nu= m) +{ + struct resource r =3D {}; + + return platform_get_irq_resource_optional(dev, num, &r); +} +EXPORT_SYMBOL_GPL(platform_get_irq_optional); + /** * platform_irq_count - Count the number of IRQs a platform device uses * @dev: platform device diff --git a/include/linux/platform_device.h b/include/linux/platform_devic= e.h index 7a41c72c19591..2117f817d9c9c 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -102,6 +102,9 @@ devm_platform_ioremap_resource_byname(struct platform_d= evice *pdev, =20 extern int platform_get_irq(struct platform_device *, unsigned int); extern int platform_get_irq_optional(struct platform_device *, unsigned in= t); +extern int platform_get_irq_resource_optional(struct platform_device *dev, + unsigned int num, + struct resource *r); extern int platform_irq_count(struct platform_device *); extern int devm_platform_get_irqs_affinity(struct platform_device *dev, struct irq_affinity *affd, --=20 2.43.0.472.g3155946c3a-goog From nobody Fri Sep 20 07:05:06 2024 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6D4E1D6A5 for ; Tue, 26 Dec 2023 19:22:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="cKG4U9Vs" Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7b7f9fdc14dso249565539f.0 for ; Tue, 26 Dec 2023 11:22:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1703618543; x=1704223343; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lq6leCeVHDoizV+5jTzWUcPBz0cSQ9yz5rfMqe3fQiU=; b=cKG4U9Vspxll8vSppHAOs8QbRnFeo4vLudDGfdK5eopkZ3PdgIhfu4aCgPC1xUQugR hyLTKsenx3UYsqAARjLTwt6PtBABMUype51BjK0AyisrfoKbGNuDb5hTwVIaK5q9NXMz kDX7iQ4W9Gr2BhVGipAAaeIj98afz9gZDJbIo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703618543; x=1704223343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lq6leCeVHDoizV+5jTzWUcPBz0cSQ9yz5rfMqe3fQiU=; b=fJazwsj2wuSANpkJEnTaoXpaDI4QcOAhI8GYoxBbftUg9DHpq2Iei0g8ITrHpGP2q0 4YyoPFYF4+NbuVGgh1TdL0tpFK8q891DnWOVRugkJnoyX8FCgBCQWNUJPPfCrxmeVgNF J4PvmyHLl50nFbgk7U3Xttt2sVOuyx8jCG1fZBpFvVMb1vXUlMNZwz/Inf3iaICgYm2v 0y8sZz8u8Qrl0eX8NSbx4Gx3T+9sx7szf1V+aENbReMw0hmNdsBHoxdSIy4zwlamI79r tRsJ3q44h5qmTSPvVol79+qYIEKZIOcpxSF9Tq7/malQJvKH6x5lT/OKyp3wbPEUmwBf uiIA== X-Gm-Message-State: AOJu0YzxkXbwWNDuXdZ8BeGgD/7REPESBNl+ch6OHUf1ZQTbSS2hcedt UBpClvZjt/YZ9UKtxOAPcUSFP0+9x5mL+4LAJl0UIbKXDJL+ X-Google-Smtp-Source: AGHT+IE+AubZc2XCmkW2Mp+4HDp57Gr1Y6IjtCRiri9AnK/aj422MHw+/OVYLgAtH+r5DjZMc/DDTQ== X-Received: by 2002:a6b:e60e:0:b0:7b7:fb0e:952a with SMTP id g14-20020a6be60e000000b007b7fb0e952amr5562983ioh.37.1703618542902; Tue, 26 Dec 2023 11:22:22 -0800 (PST) Received: from markhas1.lan (71-218-50-136.hlrn.qwest.net. [71.218.50.136]) by smtp.gmail.com with ESMTPSA id gw3-20020a0566381ee300b0046b692e719esm3207609jab.150.2023.12.26.11.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Dec 2023 11:22:22 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: AngeloGioacchino Del Regno , Krzysztof Kozlowski , Rob Herring , Konrad Dybcio , Sudeep Holla , Andy Shevchenko , Raul Rangel , Tzung-Bi Shih , Mark Hasemeyer , Benson Leung , Bhanu Prakash Maiya , Chen-Yu Tsai , Guenter Roeck , Lee Jones , Prashant Malani , Rob Barnes , Stephen Boyd , chrome-platform@lists.linux.dev Subject: [PATCH v3 24/24] platform/chrome: cros_ec: Use PM subsystem to manage wakeirq Date: Tue, 26 Dec 2023 12:21:28 -0700 Message-ID: <20231226122113.v3.24.Ieee574a0e94fbaae01fd6883ffe2ceeb98d7df28@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231226192149.1830592-1-markhas@chromium.org> References: <20231226192149.1830592-1-markhas@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cros ec driver is manually managing the wake IRQ by calling enable_irq_wake()/disable_irq_wake() during suspend/resume. Modify the driver to use the power management subsystem to manage the wakeirq. Rather than assuming that the IRQ is wake capable, use the underlying firmware/device tree to determine whether or not to enable it as a wake source. Some Chromebooks rely solely on the ec_sync pin to wake the AP but do not specify the interrupt as wake capable in the ACPI _CRS. For LPC/ACPI based systems a DMI quirk is introduced listing boards whose firmware should not be trusted to provide correct wake capable values. For device tree base systems, it is not an issue as the relevant device tree entries have been updated and DTS is built from source for each ChromeOS update. Signed-off-by: Mark Hasemeyer Acked-by: Tzung-Bi Shih --- Changes in v3: -Rebase on linux-next -See each patch for patch specific changes -Remove MODULE_DEVICE_TABLE -Drop "cros_ec _" prefix from should_force_irq_wake_capable() -Drop use of dev_err_probe() to be consistent with existing conventions in the driver -Drop *spi argument from cros_ec_spi_dt_probe() -Drop null device_node check from cros_ec_spi_dt_probe() -Add trailing commas to DMI table -Drop redundant "!=3D NULL" in should_force_irq_wake_capable() -Use str_yes_no() to print irq wake capability -Move irqwake handling from the interface specific modules to cros_ec.c Changes in v2: -Rebase on linux-next -Add cover letter -See each patch for patch specific changes -Look for 'wakeup-source' property in cros_ec_spi.c drivers/platform/chrome/cros_ec.c | 48 +++++++++++++++++---- drivers/platform/chrome/cros_ec_lpc.c | 32 ++++++++++++-- drivers/platform/chrome/cros_ec_spi.c | 15 ++++--- drivers/platform/chrome/cros_ec_uart.c | 22 +++++++--- include/linux/platform_data/cros_ec_proto.h | 4 +- 5 files changed, 97 insertions(+), 24 deletions(-) diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cr= os_ec.c index badc68bbae8cc..080b479f39a94 100644 --- a/drivers/platform/chrome/cros_ec.c +++ b/drivers/platform/chrome/cros_ec.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 @@ -168,6 +169,35 @@ static int cros_ec_ready_event(struct notifier_block *= nb, return NOTIFY_DONE; } =20 +static int enable_irq_for_wake(struct cros_ec_device *ec_dev) +{ + struct device *dev =3D ec_dev->dev; + int ret =3D device_init_wakeup(dev, true); + + if (ret) { + dev_err(dev, "Failed to enable device for wakeup"); + return ret; + } + ret =3D dev_pm_set_wake_irq(dev, ec_dev->irq); + if (ret) + device_init_wakeup(dev, false); + + return ret; +} + +static int disable_irq_for_wake(struct cros_ec_device *ec_dev) +{ + int ret; + struct device *dev =3D ec_dev->dev; + + dev_pm_clear_wake_irq(dev); + ret =3D device_init_wakeup(dev, false); + if (ret) + dev_err(dev, "Failed to disable device for wakeup"); + + return ret; +} + /** * cros_ec_register() - Register a new ChromeOS EC, using the provided inf= o. * @ec_dev: Device to register. @@ -221,6 +251,13 @@ int cros_ec_register(struct cros_ec_device *ec_dev) ec_dev->irq, err); goto exit; } + dev_dbg(dev, "IRQ: %i, wake_capable: %s\n", ec_dev->irq, + str_yes_no(ec_dev->irq_wake)); + if (ec_dev->irq_wake) { + err =3D enable_irq_for_wake(ec_dev); + if (err) + goto exit; + } } =20 /* Register a platform device for the main EC instance */ @@ -313,6 +350,8 @@ EXPORT_SYMBOL(cros_ec_register); */ void cros_ec_unregister(struct cros_ec_device *ec_dev) { + if (ec_dev->irq_wake) + disable_irq_for_wake(ec_dev); platform_device_unregister(ec_dev->pd); platform_device_unregister(ec_dev->ec); mutex_destroy(&ec_dev->lock); @@ -353,12 +392,6 @@ EXPORT_SYMBOL(cros_ec_suspend_prepare); =20 static void cros_ec_disable_irq(struct cros_ec_device *ec_dev) { - struct device *dev =3D ec_dev->dev; - if (device_may_wakeup(dev)) - ec_dev->wake_enabled =3D !enable_irq_wake(ec_dev->irq); - else - ec_dev->wake_enabled =3D false; - disable_irq(ec_dev->irq); ec_dev->suspended =3D true; } @@ -440,9 +473,6 @@ static void cros_ec_enable_irq(struct cros_ec_device *e= c_dev) ec_dev->suspended =3D false; enable_irq(ec_dev->irq); =20 - if (ec_dev->wake_enabled) - disable_irq_wake(ec_dev->irq); - /* * Let the mfd devices know about events that occur during * suspend. This way the clients know what to do with them. diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrom= e/cros_ec_lpc.c index f0f3d3d561572..193a48e3f8f8e 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -48,6 +48,27 @@ struct lpc_driver_ops { =20 static struct lpc_driver_ops cros_ec_lpc_ops =3D { }; =20 +static const struct dmi_system_id untrusted_fw_irq_wake_capable[] =3D { + { + .ident =3D "Brya", + .matches =3D { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brya"), + }, + }, + { + .ident =3D "Brask", + .matches =3D { + DMI_MATCH(DMI_PRODUCT_FAMILY, "Google_Brask"), + }, + }, + { } +}; + +static bool should_force_irq_wake_capable(void) +{ + return dmi_first_match(untrusted_fw_irq_wake_capable); +} + /* * A generic instance of the read function of struct lpc_driver_ops, used = for * the LPC EC. @@ -353,6 +374,7 @@ static int cros_ec_lpc_probe(struct platform_device *pd= ev) struct acpi_device *adev; acpi_status status; struct cros_ec_device *ec_dev; + struct resource irqres; u8 buf[2] =3D {}; int irq, ret; =20 @@ -428,10 +450,14 @@ static int cros_ec_lpc_probe(struct platform_device *= pdev) * Some boards do not have an IRQ allotted for cros_ec_lpc, * which makes ENXIO an expected (and safe) scenario. */ - irq =3D platform_get_irq_optional(pdev, 0); - if (irq > 0) + irq =3D platform_get_irq_resource_optional(pdev, 0, &irqres); + if (irq > 0) { ec_dev->irq =3D irq; - else if (irq !=3D -ENXIO) { + if (should_force_irq_wake_capable()) + ec_dev->irq_wake =3D true; + else + ec_dev->irq_wake =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; + } else if (irq !=3D -ENXIO) { dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq); return irq; } diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrom= e/cros_ec_spi.c index 3e88cc92e8192..102cdc3d1956d 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -70,6 +71,7 @@ * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that * is sent when we want to turn off CS at the end of a transaction. * @high_pri_worker: Used to schedule high priority work. + * @irq_wake: Whether or not irq assertion should wake the system. */ struct cros_ec_spi { struct spi_device *spi; @@ -77,6 +79,7 @@ struct cros_ec_spi { unsigned int start_of_msg_delay; unsigned int end_of_msg_delay; struct kthread_worker *high_pri_worker; + bool irq_wake; }; =20 typedef int (*cros_ec_xfer_fn_t) (struct cros_ec_device *ec_dev, @@ -689,9 +692,10 @@ static int cros_ec_cmd_xfer_spi(struct cros_ec_device = *ec_dev, return cros_ec_xfer_high_pri(ec_dev, ec_msg, do_cros_ec_cmd_xfer_spi); } =20 -static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device= *dev) +static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi) { - struct device_node *np =3D dev->of_node; + struct spi_device *spi =3D ec_spi->spi; + struct device_node *np =3D spi->dev.of_node; u32 val; int ret; =20 @@ -702,6 +706,8 @@ static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec= _spi, struct device *dev) ret =3D of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val); if (!ret) ec_spi->end_of_msg_delay =3D val; + + ec_spi->irq_wake =3D spi->irq > 0 && of_property_present(np, "wakeup-sour= ce"); } =20 static void cros_ec_spi_high_pri_release(void *worker) @@ -754,12 +760,13 @@ static int cros_ec_spi_probe(struct spi_device *spi) return -ENOMEM; =20 /* Check for any DT properties */ - cros_ec_spi_dt_probe(ec_spi, dev); + cros_ec_spi_dt_probe(ec_spi); =20 spi_set_drvdata(spi, ec_dev); ec_dev->dev =3D dev; ec_dev->priv =3D ec_spi; ec_dev->irq =3D spi->irq; + ec_dev->irq_wake =3D ec_spi->irq_wake; ec_dev->cmd_xfer =3D cros_ec_cmd_xfer_spi; ec_dev->pkt_xfer =3D cros_ec_pkt_xfer_spi; ec_dev->phys_name =3D dev_name(&ec_spi->spi->dev); @@ -780,8 +787,6 @@ static int cros_ec_spi_probe(struct spi_device *spi) return err; } =20 - device_init_wakeup(&spi->dev, true); - return 0; } =20 diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chro= me/cros_ec_uart.c index 68d80559fddc2..5330ccdf9b35c 100644 --- a/drivers/platform/chrome/cros_ec_uart.c +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -69,6 +69,7 @@ struct response_info { * @serdev: serdev uart device we are connected to. * @baudrate: UART baudrate of attached EC device. * @flowcontrol: UART flowcontrol of attached device. + * @irq_wake: Whether or not irq assertion should wake the system. * @irq: Linux IRQ number of associated serial device. * @response: Response info passing between cros_ec_uart_pkt_xfer() * and cros_ec_uart_rx_bytes() @@ -77,6 +78,7 @@ struct cros_ec_uart { struct serdev_device *serdev; u32 baudrate; u8 flowcontrol; + bool irq_wake; u32 irq; struct response_info response; }; @@ -224,8 +226,10 @@ static int cros_ec_uart_resource(struct acpi_resource = *ares, void *data) static int cros_ec_uart_acpi_probe(struct cros_ec_uart *ec_uart) { int ret; + struct resource irqres; LIST_HEAD(resources); - struct acpi_device *adev =3D ACPI_COMPANION(&ec_uart->serdev->dev); + struct device *dev =3D &ec_uart->serdev->dev; + struct acpi_device *adev =3D ACPI_COMPANION(dev); =20 ret =3D acpi_dev_get_resources(adev, &resources, cros_ec_uart_resource, e= c_uart); if (ret < 0) @@ -234,12 +238,12 @@ static int cros_ec_uart_acpi_probe(struct cros_ec_uar= t *ec_uart) acpi_dev_free_resource_list(&resources); =20 /* Retrieve GpioInt and translate it to Linux IRQ number */ - ret =3D acpi_dev_gpio_irq_get(adev, 0); + ret =3D acpi_dev_get_gpio_irq_resource(adev, NULL, 0, &irqres); if (ret < 0) return ret; =20 - ec_uart->irq =3D ret; - dev_dbg(&ec_uart->serdev->dev, "IRQ number %d\n", ec_uart->irq); + ec_uart->irq =3D irqres.start; + ec_uart->irq_wake =3D irqres.flags & IORESOURCE_IRQ_WAKECAPABLE; =20 return 0; } @@ -293,6 +297,7 @@ static int cros_ec_uart_probe(struct serdev_device *ser= dev) ec_dev->dev =3D dev; ec_dev->priv =3D ec_uart; ec_dev->irq =3D ec_uart->irq; + ec_dev->irq_wake =3D ec_uart->irq_wake; ec_dev->cmd_xfer =3D NULL; ec_dev->pkt_xfer =3D cros_ec_uart_pkt_xfer; ec_dev->din_size =3D sizeof(struct ec_host_response) + @@ -301,7 +306,14 @@ static int cros_ec_uart_probe(struct serdev_device *se= rdev) =20 serdev_device_set_client_ops(serdev, &cros_ec_uart_client_ops); =20 - return cros_ec_register(ec_dev); + /* Register a new cros_ec device */ + ret =3D cros_ec_register(ec_dev); + if (ret) { + dev_err(dev, "Couldn't register ec_dev (%d)\n", ret); + return ret; + } + + return 0; } =20 static void cros_ec_uart_remove(struct serdev_device *serdev) diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/pl= atform_data/cros_ec_proto.h index 8865e350c12a5..0fb2781b602d6 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -100,6 +100,7 @@ struct cros_ec_command { * @proto_version: The protocol version used for this device. * @priv: Private data. * @irq: Interrupt to use. + * @irq_wake: Whether or not irq assertion should wake the system. * @id: Device id. * @din: Input buffer (for data from EC). This buffer will always be * dword-aligned and include enough space for up to 7 word-alignment @@ -115,7 +116,6 @@ struct cros_ec_command { * performance advantage to using dword. * @din_size: Size of din buffer to allocate (zero to use static din). * @dout_size: Size of dout buffer to allocate (zero to use static dout). - * @wake_enabled: True if this device can wake the system from sleep. * @suspended: True if this device had been suspended. * @cmd_xfer: Send command to EC and get response. * Returns the number of bytes received if the communication @@ -169,11 +169,11 @@ struct cros_ec_device { u16 proto_version; void *priv; int irq; + bool irq_wake; u8 *din; u8 *dout; int din_size; int dout_size; - bool wake_enabled; bool suspended; int (*cmd_xfer)(struct cros_ec_device *ec, struct cros_ec_command *msg); --=20 2.43.0.472.g3155946c3a-goog