From nobody Fri Dec 19 17:13:33 2025 Received: from mecka.net (mecka.net [159.69.159.214]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7053CDF4E; Sat, 23 Dec 2023 15:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mecka.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mecka.net Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mecka.net header.i=@mecka.net header.b="KmfjTpyi" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mecka.net; s=2016.11; t=1703344838; bh=eKk/DlnzPtMcPQxfNWOgU5Nu4ITnGNL+vBoe3BdXNpk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KmfjTpyirTuxzhN5kRBez0UKDeoEjWwsTPqJcC7UyM0Dbm2SsePYa0PdDCdwRQa7t HbmDD+u3sGyw933zqnKQPS5iIeq1iOYNH/nycrjrqVFrCpFM2aQifwDEJ/xhUBlYy3 Vv2InnjAmQ33kf7A+5Fhxks+crunKFtDd3xKQbVXGLjXq4sP7QGf8H53ttuzS/21NS 6LbWAPEXsbGEahhdeLE2gOA0Na+Orhs4S9EZ2s4eJ0MxL7IyBnmUO507W4ZX4N9i2l gQ1ZfqqJQbDiUz2r6pCsQKsR2ALANPlt6jGZXjGznRWcqVGGym8It2XtH3z6XdS7A2 D6nWj6rgRqamg== Received: from arthur.fritz.box (unknown [185.147.11.134]) by mecka.net (Postfix) with ESMTPSA id BD3B6371959; Sat, 23 Dec 2023 16:20:37 +0100 (CET) From: Manuel Traut Date: Sat, 23 Dec 2023 16:20:15 +0100 Subject: [PATCH v2 1/4] dt-bindings: display: panel: Add BOE TH101MB31IG002-28A panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231223-pinetab2-v2-1-ec1856d0030e@mecka.net> References: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> In-Reply-To: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sandy Huang , Mark Yao , Diederik de Haas , Segfault , Arnaud Ferraris , Danct12 Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Manuel Traut X-Mailer: b4 0.12.4 Add bindings for the BOE TH101MB31IG002-28A LCD panel. It is used e.g. in the Pine64 Pinetab2 and PinetabV. Signed-off-by: Manuel Traut Reviewed-by: Krzysztof Kozlowski Tested-By: Diederik de Haas --- .../display/panel/boe,th101mb31ig002-28a.yaml | 58 ++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,th101mb31i= g002-28a.yaml b/Documentation/devicetree/bindings/display/panel/boe,th101mb= 31ig002-28a.yaml new file mode 100644 index 000000000000..32df26cbfeed --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,th101mb31ig002-28= a.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE TH101MB31IG002-28A WXGA DSI Display Panel + +maintainers: + - Manuel Traut + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel + - boe,th101mb31ig002-28a + + reg: true + backlight: true + enable-gpios: true + power-supply: true + port: true + rotation: true + +required: + - compatible + - reg + - enable-gpios + - power-supply + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel@0 { + compatible =3D "boe,th101mb31ig002-28a"; + reg =3D <0>; + backlight =3D <&backlight_lcd0>; + enable-gpios =3D <&gpio 45 GPIO_ACTIVE_HIGH>; + rotation =3D <90>; + power-supply =3D <&vcc_3v3>; + port { + panel_in_dsi: endpoint { + remote-endpoint =3D <&dsi_out_con>; + }; + }; + }; + }; + +... --=20 2.43.0 From nobody Fri Dec 19 17:13:33 2025 Received: from mecka.net (mecka.net [159.69.159.214]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 24085DF5E; Sat, 23 Dec 2023 15:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mecka.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mecka.net Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mecka.net header.i=@mecka.net header.b="B1BiY9JR" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mecka.net; s=2016.11; t=1703344839; bh=Sx/xib13yuKmYj+IRpkKXwgyt5bGd2EJeEkjfHseN7k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=B1BiY9JRLQU+N7szO0gJNOJw0QNTKHBCuH/NLbmmKDMUAG20CqxFncJ+IG+NI0Uw3 +az4eM2Hjh12m6/hQFQ9ADHH3igUc3KPl9c/nAx7d5o9AD8SS/qhWeBTXcZM8dhJph zV8reuAa8sScClrsiQydMtgYnrLcgo/RAF5EMO3nnBOs+KKkbejujz2/8oGo1j02am kymRf9DhyWxDAzv4czO9J55QlIxP0yBQgpQ+kXvvJbI6eWLpgqfFiJ5xGdcHWBsX1N hvl/L9t+H61nmXV2w6ZV7IVY3CaOyX32C1hjZ2/jIsfu70uMJtOZjHM7VbnQ5B8Hgj sS1ey+8uSMlBQ== Received: from arthur.fritz.box (unknown [185.147.11.134]) by mecka.net (Postfix) with ESMTPSA id 6D54237195A; Sat, 23 Dec 2023 16:20:38 +0100 (CET) From: Manuel Traut Date: Sat, 23 Dec 2023 16:20:16 +0100 Subject: [PATCH v2 2/4] drm/panel: Add driver for BOE TH101MB31IG002-28A panel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231223-pinetab2-v2-2-ec1856d0030e@mecka.net> References: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> In-Reply-To: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sandy Huang , Mark Yao , Diederik de Haas , Segfault , Arnaud Ferraris , Danct12 Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Manuel Traut X-Mailer: b4 0.12.4 From: Alexander Warnecke The BOE TH101MB31IG002-28A panel is a WXGA panel. It is used in Pine64 Pinetab2 and PinetabV. Signed-off-by: Alexander Warnecke Signed-off-by: Manuel Traut Tested-By: Diederik de Haas --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-boe-th101mb31ig002-28a.c | 348 +++++++++++++++++= ++++ 3 files changed, 360 insertions(+) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 99e14dc212ec..927ddd10e688 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -67,6 +67,17 @@ config DRM_PANEL_BOE_HIMAX8279D 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. =20 +config DRM_PANEL_BOE_TH101MB31UIG002_28A + tristate "Boe TH101MB31UIG002-28A panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Boe + TH101MB31UIG002-28A TFT-LCD modules. The panel has a 800x1280 + resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI + interface to the host and has a built-in LED backlight. + config DRM_PANEL_BOE_TV101WUM_NL6 tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d10c3de51c6d..dd6e1ac9d0a2 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596) +=3D panel-= asus-z00t-tm5p5-n35596. obj-$(CONFIG_DRM_PANEL_AUO_A030JTN01) +=3D panel-auo-a030jtn01.o obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) +=3D panel-boe-bf060y8m-aj0.o obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) +=3D panel-boe-himax8279d.o +obj-$(CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A) +=3D panel-boe-th101mb31ig= 002-28a.o obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) +=3D panel-boe-tv101wum-nl6.o obj-$(CONFIG_DRM_PANEL_DSI_CM) +=3D panel-dsi-cm.o obj-$(CONFIG_DRM_PANEL_LVDS) +=3D panel-lvds.o diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers= /gpu/drm/panel/panel-boe-th101mb31ig002-28a.c new file mode 100644 index 000000000000..ffe4047b7434 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Alexander Warnecke + * Copyright (c) 2023 Manuel Traut + * Copyright (c) 2023 Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct boe_th101mb31ig002 { + struct drm_panel panel; + bool enabled; + bool prepared; + + struct mipi_dsi_device *dsi; + + struct regulator *power; + struct gpio_desc *enable; + struct gpio_desc *reset; + + enum drm_panel_orientation orientation; +}; + +static void boe_th101mb31ig002_reset(struct boe_th101mb31ig002 *ctx) +{ + gpiod_direction_output(ctx->reset, 0); + usleep_range(10, 100); + gpiod_direction_output(ctx->reset, 1); + usleep_range(10, 100); + gpiod_direction_output(ctx->reset, 0); + usleep_range(5000, 6000); +} + +static int boe_th101mb31ig002_enable(struct drm_panel *panel) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + if (ctx->enabled) + return 0; + + mipi_dsi_dcs_write_seq(dsi, 0xE0, 0xAB, 0xBA); + mipi_dsi_dcs_write_seq(dsi, 0xE1, 0xBA, 0xAB); + mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x10, 0x01, 0x47, 0xFF); + mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x0C, 0x14, 0x04, 0x50, 0x50, 0x14); + mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x56, 0x53, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x33, 0x30, 0x04); + mipi_dsi_dcs_write_seq(dsi, 0xB6, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x10, + 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, + 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x7C, 0x65, 0x55, 0x49, 0x46, 0x36, + 0x3B, 0x24, 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, + 0x55, 0x47, 0x46, 0x39, 0x26, 0x06, 0x7C, + 0x65, 0x55, 0x49, 0x46, 0x36, 0x3B, 0x24, + 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, 0x55, 0x47, + 0x46, 0x39, 0x26, 0x06); + mipi_dsi_dcs_write_seq(dsi, 0x00, 0xFF, 0x87, 0x12, 0x34, 0x44, 0x44, + 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0F, + 0x00, 0x00, 0xC1); + mipi_dsi_dcs_write_seq(dsi, 0xC1, 0x54, 0x94, 0x02, 0x85, 0x9F, 0x00, + 0x7F, 0x00, 0x54, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xC2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11, + 0x22, 0x20, 0x44, 0xFF, 0x18, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xC3, 0x86, 0x46, 0x05, 0x05, 0x1C, 0x1C, + 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, + 0x0F, 0x0F, 0x0D, 0x0D, 0x13, 0x13, 0x11, + 0x11, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xC4, 0x07, 0x07, 0x04, 0x04, 0x1C, 0x1C, + 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, + 0x0E, 0x0E, 0x0C, 0x0C, 0x12, 0x12, 0x10, + 0x10, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xC6, 0x2A, 0x2A); + mipi_dsi_dcs_write_seq(dsi, 0xC8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16); + mipi_dsi_dcs_write_seq(dsi, 0xCA, 0xCB, 0x43); + mipi_dsi_dcs_write_seq(dsi, 0xCD, 0x0E, 0x4B, 0x4B, 0x20, 0x19, 0x6B, + 0x06, 0xB3); + mipi_dsi_dcs_write_seq(dsi, 0xD2, 0xE3, 0x2B, 0x38, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xD4, 0x00, 0x01, 0x00, 0x0E, 0x04, 0x44, + 0x08, 0x10, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xE6, 0x80, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF); + mipi_dsi_dcs_write_seq(dsi, 0xF0, 0x12, 0x03, 0x20, 0x00, 0xFF); + mipi_dsi_dcs_write_seq(dsi, 0xF3, 0x00); + + ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + + msleep(120); + + ret =3D mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set panel on: %d\n", ret); + return ret; + } + + ctx->enabled =3D true; + + return 0; +} + +static int boe_th101mb31ig002_disable(struct drm_panel *panel) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + struct mipi_dsi_device *dsi =3D ctx->dsi; + struct device *dev =3D &dsi->dev; + int ret; + + if (!ctx->enabled) + return 0; + + ret =3D mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) + dev_err(dev, "Failed to set panel off: %d\n", ret); + + msleep(120); + + ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + + ctx->enabled =3D false; + + return 0; +} + +static int boe_th101mb31ig002_unprepare(struct drm_panel *panel) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + + if (!ctx->prepared) + return 0; + + gpiod_set_value_cansleep(ctx->reset, 1); + gpiod_set_value_cansleep(ctx->enable, 0); + regulator_disable(ctx->power); + + ctx->prepared =3D false; + + return 0; +} + +static int boe_th101mb31ig002_prepare(struct drm_panel *panel) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + struct device *dev =3D &ctx->dsi->dev; + int ret; + + if (ctx->prepared) + return 0; + + ret =3D regulator_enable(ctx->power); + if (ret) { + dev_err(dev, "Failed to enable power supply: %d\n", ret); + return ret; + } + + gpiod_set_value_cansleep(ctx->enable, 1); + msleep(50); + boe_th101mb31ig002_reset(ctx); + boe_th101mb31ig002_enable(panel); + + ctx->prepared =3D true; + + return 0; +} + +static const struct drm_display_mode boe_th101mb31ig002_default_mode =3D { + .clock =3D 73500, + .hdisplay =3D 800, + .hsync_start =3D 800 + 64, + .hsync_end =3D 800 + 64 + 16, + .htotal =3D 800 + 64 + 16 + 64, + .vdisplay =3D 1280, + .vsync_start =3D 1280 + 2, + .vsync_end =3D 1280 + 2 + 4, + .vtotal =3D 1280 + 2 + 4 + 12, + .width_mm =3D 135, + .height_mm =3D 216, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static int boe_th101mb31ig002_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + struct drm_display_mode *mode; + + mode =3D drm_mode_duplicate(connector->dev, + &boe_th101mb31ig002_default_mode); + if (!mode) { + dev_err(panel->dev, "Failed to add mode %ux%u@%u\n", + boe_th101mb31ig002_default_mode.hdisplay, + boe_th101mb31ig002_default_mode.vdisplay, + drm_mode_vrefresh(&boe_th101mb31ig002_default_mode)); + return -ENOMEM; + } + + drm_mode_set_name(mode); + + connector->display_info.bpc =3D 8; + connector->display_info.width_mm =3D mode->width_mm; + connector->display_info.height_mm =3D mode->height_mm; + + /* + * TODO: Remove once all drm drivers call + * drm_connector_set_orientation_from_panel() + */ + drm_connector_set_panel_orientation(connector, ctx->orientation); + + drm_mode_probed_add(connector, mode); + + return 1; +} + +static enum drm_panel_orientation +boe_th101mb31ig002_get_orientation(struct drm_panel *panel) +{ + struct boe_th101mb31ig002 *ctx =3D container_of(panel, + struct boe_th101mb31ig002, + panel); + + return ctx->orientation; +} + +static const struct drm_panel_funcs boe_th101mb31ig002_funcs =3D { + .prepare =3D boe_th101mb31ig002_prepare, + .unprepare =3D boe_th101mb31ig002_unprepare, + .enable =3D boe_th101mb31ig002_enable, + .disable =3D boe_th101mb31ig002_disable, + .get_modes =3D boe_th101mb31ig002_get_modes, + .get_orientation =3D boe_th101mb31ig002_get_orientation, +}; + +static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct boe_th101mb31ig002 *ctx; + int ret; + + ctx =3D devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->enabled =3D false; + ctx->prepared =3D false; + + mipi_dsi_set_drvdata(dsi, ctx); + ctx->dsi =3D dsi; + + dsi->lanes =3D 4; + dsi->format =3D MIPI_DSI_FMT_RGB888; + dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_MODE_LPM; + + ctx->power =3D devm_regulator_get(&dsi->dev, "power"); + if (IS_ERR(ctx->power)) + return dev_err_probe(&dsi->dev, PTR_ERR(ctx->power), + "Failed to get power regulator\n"); + + ctx->enable =3D devm_gpiod_get(&dsi->dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(ctx->enable)) + return dev_err_probe(&dsi->dev, PTR_ERR(ctx->enable), + "Failed to get enable GPIO\n"); + + ctx->reset =3D devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset)) + return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset), + "Failed to get reset GPIO\n"); + + ret =3D of_drm_get_panel_orientation(dsi->dev.of_node, + &ctx->orientation); + if (ret) + return dev_err_probe(&dsi->dev, ret, + "Failed to get orientation\n"); + + drm_panel_init(&ctx->panel, &dsi->dev, &boe_th101mb31ig002_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret =3D drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + ret =3D mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err_probe(&dsi->dev, ret, + "Failed to attach panel to DSI host\n"); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void boe_th101mb31ig002_dsi_remove(struct mipi_dsi_device *dsi) +{ + struct boe_th101mb31ig002 *ctx =3D mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id boe_th101mb31ig002_of_match[] =3D { + { .compatible =3D "boe,th101mb31ig002-28a", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, boe_th101mb31ig002_of_match); + +static struct mipi_dsi_driver boe_th101mb31ig002_driver =3D { + .driver =3D { + .name =3D "boe-th101mb31ig002-28a", + .of_match_table =3D boe_th101mb31ig002_of_match, + }, + .probe =3D boe_th101mb31ig002_dsi_probe, + .remove =3D boe_th101mb31ig002_dsi_remove, +}; +module_mipi_dsi_driver(boe_th101mb31ig002_driver); + +MODULE_AUTHOR("Alexander Warnecke "); +MODULE_DESCRIPTION("BOE TH101MB31IG002-28A MIPI-DSI LCD panel"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Fri Dec 19 17:13:33 2025 Received: from mecka.net (mecka.net [159.69.159.214]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C2F45DF60; Sat, 23 Dec 2023 15:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mecka.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mecka.net Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mecka.net header.i=@mecka.net header.b="ZINjSLDV" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mecka.net; s=2016.11; t=1703344839; bh=vgxRANyqwlVPMwtKO8SOOWvi4Qkx3vypc5+xq1xEr0U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZINjSLDVY0OoHXbxsj9YVKlz0LOOm9CBTp/aoSExKjl06wgL0kU4GkIObtM7RUXki S3/p5U8JKktj5a4hl9yv7EfH5KGQCEhlKjqk/RMKqWE0bsOH2rZ3Xudn270WM8lU64 mUNga7cCa7tXazKqjHKYP0A2a38TLB7xq8/jQlqVju6i+6+eHAe3gnPYdoKTAYzqra JIakXUHd5/plWKjpuF1pZSm21uFpLCDMmOX2dSu1xL7I5zg5bUnGBGkZ8LVj5sjcwO 3VuFw3d7BgvSblpUof1N3XK3ifq1tM99pnH7xhpZ4s5hdpc7yJjWB6lqyuzKOjRPsu mSdCy6tV9075w== Received: from arthur.fritz.box (unknown [185.147.11.134]) by mecka.net (Postfix) with ESMTPSA id 1F08237195B; Sat, 23 Dec 2023 16:20:39 +0100 (CET) From: Manuel Traut Date: Sat, 23 Dec 2023 16:20:17 +0100 Subject: [PATCH v2 3/4] dt-bindings: arm64: rockchip: Add Pine64 Pinetab2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231223-pinetab2-v2-3-ec1856d0030e@mecka.net> References: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> In-Reply-To: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sandy Huang , Mark Yao , Diederik de Haas , Segfault , Arnaud Ferraris , Danct12 Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Manuel Traut , Krzysztof Kozlowski X-Mailer: b4 0.12.4 Add devicvetree binding documentation for Pine64 Pinetab2 which uses the Rockchip RK3566 SoC. Signed-off-by: Manuel Traut Acked-by: Krzysztof Kozlowski Tested-By: Diederik de Haas --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 5f7c6c4aad8f..96d54b0587ab 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -635,6 +635,14 @@ properties: - const: pine64,pinenote - const: rockchip,rk3566 =20 + - description: Pine64 PineTab2 + items: + - enum: + - pine64,pinetab2-v0.1 + - pine64,pinetab2-v2.0 + - const: pine64,pinetab2 + - const: rockchip,rk3566 + - description: Pine64 PinePhonePro items: - const: pine64,pinephone-pro --=20 2.43.0 From nobody Fri Dec 19 17:13:33 2025 Received: from mecka.net (mecka.net [159.69.159.214]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 83392E56C; Sat, 23 Dec 2023 15:20:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mecka.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mecka.net Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mecka.net header.i=@mecka.net header.b="de6RYi3A" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mecka.net; s=2016.11; t=1703344840; bh=H1Aw0hGzGeZk0bKfMugFbTpRPGo2rixE5v8m0ozC0gU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=de6RYi3AwoSGtu2cYLoDEUc7pOVOgPhaY93SWDiV2kfBwV252JbVWPOBYF3GoYBpf qoUJbaDPxxnBudTUECipr7OotFMO4u4M8E+UYsMR+aCM230oO4x7u/vgqH729vIKvs 8Fqu6W+yF55afgdVzN1rWDPP15BI4kSdAemFb1FeqQPeVqXhz7A7y/ZFPZj+nkVb49 c5DfZ0j9lkVPB+usQfHpVGNiOvoZYyGSfoaRa2JpSKgCS8O9ORNjhS5RWvP85sw+aE FGsPfciYd2pflBcjoWPeO70J1/uab2ABNwqqU9zwl6/rRlmE3M+S/5T5aOj5gasNdr vjH6rFQxW1fjA== Received: from arthur.fritz.box (unknown [185.147.11.134]) by mecka.net (Postfix) with ESMTPSA id C868637195D; Sat, 23 Dec 2023 16:20:39 +0100 (CET) From: Manuel Traut Date: Sat, 23 Dec 2023 16:20:18 +0100 Subject: [PATCH v2 4/4] arm64: dts: rockchip: Add devicetree for Pine64 Pinetab2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231223-pinetab2-v2-4-ec1856d0030e@mecka.net> References: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> In-Reply-To: <20231223-pinetab2-v2-0-ec1856d0030e@mecka.net> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sandy Huang , Mark Yao , Diederik de Haas , Segfault , Arnaud Ferraris , Danct12 Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Manuel Traut X-Mailer: b4 0.12.4 From: Alexander Warnecke This includes support for both the v0.1 units that were sent to developers = and the v2.0 units from production. v1.0 is not included as no units are known to exist. Working/Tested: - SDMMC - UART - Buttons - Charging/Battery/PMIC - Audio - USB - Display WiFi is not added, since the driver is not ready for mainline. Signed-off-by: Alexander Warnecke Signed-off-by: Manuel Traut Tested-By: Diederik de Haas --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3566-pinetab2-v0.1.dts | 26 + .../boot/dts/rockchip/rk3566-pinetab2-v2.0.dts | 46 + arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi | 979 +++++++++++++++++= ++++ 4 files changed, 1053 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index a18f33bf0c0e..ef66c0937a9b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -77,6 +77,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg353vs.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-anbernic-rg503.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinetab2-v0.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinetab2-v2.0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-powkiddy-rgb30.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v0.1.dts b/arch/a= rm64/boot/dts/rockchip/rk3566-pinetab2-v0.1.dts new file mode 100644 index 000000000000..8b110186a3eb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model =3D "Pine64 PineTab2 v0.1"; + compatible =3D "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk356= 6"; +}; + +&lcd { + reset-gpios =3D <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply =3D <&vcc3v3_sys>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v2.0.dts b/arch/a= rm64/boot/dts/rockchip/rk3566-pinetab2-v2.0.dts new file mode 100644 index 000000000000..6f80446b5802 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model =3D "Pine64 PineTab2 v2.0"; + compatible =3D "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk356= 6"; +}; + +&gpio_keys { + pinctrl-0 =3D <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval =3D <20>; + gpios =3D <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label =3D "Hall Sensor"; + linux,code =3D ; + linux,input-type =3D ; + wakeup-event-action =3D ; + wakeup-source; + }; +}; + +&lcd { + reset-gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply =3D <&vcc_sys>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-pinetab2.dtsi new file mode 100644 index 000000000000..3ab7d8dbe1ec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + chassis-type =3D "tablet"; + + aliases { + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <25>; + + button-vol-up { + label =3D "Volume Up"; + linux,code =3D ; + press-threshold-microvolt =3D <297500>; + }; + + button-vol-down { + label =3D "Volume Down"; + linux,code =3D ; + press-threshold-microvolt =3D <1750>; + }; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm4 0 25000 0>; + brightness-levels =3D <20 220>; + num-interpolated-steps =3D <200>; + default-brightness-level =3D <100>; + power-supply =3D <&vcc_sys>; + }; + + battery: battery { + compatible =3D "simple-battery"; + charge-full-design-microamp-hours =3D <6000000>; + charge-term-current-microamp =3D <300000>; + constant-charge-current-max-microamp =3D <2000000>; + constant-charge-voltage-max-microvolt =3D <4300000>; + voltage-max-design-microvolt =3D <4350000>; + voltage-min-design-microvolt =3D <3400000>; + + ocv-capacity-celsius =3D <20>; + ocv-capacity-table-0 =3D <4322000 100>, <4250000 95>, <4192000 90>, <413= 6000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kb_id_det>; + + tablet-mode-switch { + debounce-interval =3D <20>; + gpios =3D <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label =3D "Tablet Mode"; + linux,input-type =3D ; + linux,code =3D ; + }; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&flash_led_en_h>; + + led-0 { + gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_FLASH; + }; + }; + + rk817-sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_det_l>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,name =3D "rk817_ext"; + simple-audio-card,mclk-fs =3D <256>; + + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing =3D + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio =3D <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs =3D <&speaker_amp>; + simple-audio-card,pin-switches =3D "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai =3D <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible =3D "simple-audio-amplifier"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spk_ctl>; + enable-gpios =3D <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix =3D "Speaker Amplifier"; + VCC-supply =3D <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_minipcie: vcc3v3-minipcie { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pwren_h>; + regulator-name =3D "vcc3v3_minipcie"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_pwren_l>; + regulator-name =3D "vcc3v3_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren1_h>; + regulator-name =3D "vcc5v0_usb_host0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v_midu>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren2_h>; + regulator-name =3D "vcc5v0_usb_host2"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v_midu>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_bat: vcc-bat { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd1v2_dvp"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_3v3>; + /*enable-supply =3D <&vcc2v8_dvp>;*/ + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cru { + assigned-clocks =3D <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates =3D <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents =3D <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status =3D "okay"; +}; + +&dsi0 { + status =3D "okay"; + clock-master; + #address-cells =3D <1>; + #size-cells =3D <0>; + + lcd: panel@0 { + compatible =3D "boe,th101mb31ig002-28a"; + reg =3D <0>; + backlight =3D <&backlight>; + enable-gpios =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd_pwren_h &lcd0_rst_l>; + rotation =3D <90>; + power-supply =3D <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint =3D <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint =3D <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_npu>; + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdda_0v9_p>; + avdd-1v8-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status =3D "okay"; +}; + +&i2c0 { + clock-frequency =3D <400000>; + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible =3D "rockchip,rk817"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + assigned-clocks =3D <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents =3D <&cru CLK_I2S1_8CH_TX>; + clock-names =3D "mclk"; + clocks =3D <&cru I2S1_MCLKOUT_TX>; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells =3D <0>; + wakeup-source; + + vcc1-supply =3D <&vcc_sys>; + vcc2-supply =3D <&vcc_sys>; + vcc3-supply =3D <&vcc_sys>; + vcc4-supply =3D <&vcc_sys>; + vcc5-supply =3D <&vcc_sys>; + vcc6-supply =3D <&vcc_sys>; + vcc7-supply =3D <&vcc_sys>; + vcc8-supply =3D <&vcc_sys>; + vcc9-supply =3D <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery =3D <&battery>; + rockchip,resistor-sense-micro-ohms =3D <10000>; + rockchip,sleep-enter-current-microamp =3D <300000>; + rockchip,sleep-filter-current-microamp =3D <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + status =3D "okay"; + + touchscreen@5d { + compatible =3D "goodix,gt911"; + reg =3D <0x5d>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply =3D <&vcc3v3_pmu>; + VDDIO-supply =3D <&vcca1v8_pmu>; + irq-gpios =3D <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "okay"; + + vcm@c { + compatible =3D "dongwoon,dw9714"; + reg =3D <0x0c>; + vcc-supply =3D <&vcc1v8_dvp>; + }; + + camera@36 { + compatible =3D "ovti,ov5648"; + reg =3D <0x36>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&camerab_pdn_l &camerab_rst_l>; + + clocks =3D <&cru CLK_CIF_OUT>; + assigned-clocks =3D <&cru CLK_CIF_OUT>; + assigned-clock-rates =3D <24000000>; + + avdd-supply =3D <&vcc2v8_dvp>; + dvdd-supply =3D <&vdd1v2_dvp>; + dovdd-supply =3D <&vcc1v8_dvp>; + powerdown-gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <0>; + link-frequencies =3D /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency =3D <400000>; + status =3D "okay"; + + accelerometer@18 { + compatible =3D "silan,sc7a20"; + reg =3D <0x18>; + interrupt-parent =3D <&gpio3>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gsensor_int_l>; + st,drdy-int-pin =3D <1>; + vdd-supply =3D <&vcc_1v8>; + vddio-supply =3D <&vcc_1v8>; + mount-matrix =3D "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status =3D "okay"; +}; + +&i2s1_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status =3D "okay"; +}; + +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_h>; + reset-gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_minipcie>; + status =3D "okay"; +}; + +&pinctrl { + bt { + bt_wake_host_h: bt-wake-host-h { + rockchip,pins =3D <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins =3D <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins =3D <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins =3D <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins =3D <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins =3D + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins =3D <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins =3D <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins =3D <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins =3D <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins =3D <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins =3D <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins =3D <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_pwren: wifi-pwren { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcca1v8_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_1v8>; + vccio6-supply =3D <&vcc1v8_dvp>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + no-sdio; + no-sd; + non-removable; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply =3D <&vcca1v8_pmu>; + status =3D "okay"; +}; + +&sfc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&fspi_dual_io_pins>; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <24000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer + &uart1m0_ctsn + &uart1m0_rtsn>; + status =3D "okay"; + uart-has-rtscts; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb_host0>; + status =3D "okay"; +}; + +&usb2phy0_otg { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb_host2>; + status =3D "okay"; +}; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg =3D ; + remote-endpoint =3D <&dsi0_in_vp1>; + }; +}; --=20 2.43.0