From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C799D35F08 for ; Fri, 22 Dec 2023 23:52:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E247KAxb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289142; x=1734825142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VcwND0aWDeRwkDNfEVxfZaxd9Qm+T3IoGFMgIHh0GwE=; b=E247KAxbN6ojYJIxWVF16O2i2vK+heqfgVjXZZvlx06eXERdJ7lO3SEo ZxC09BJqp+RxvF930wlYYYJnxGmA565r39+o9Z41xUgzxuxckNNOnk+i4 icCvixieFpaXqFRguNMqim4oTalEpNGfbJYqxB/7bnZplIv7zIRXjTcs4 01L9D21czNsO3GjpTi8X+95AbxmqGz0mMzCByv2gc7D8YnYo6FbzU1ska +slIQZpEvtEIRn+fH6OoK4fVNYjYkGKwUNvk+hJvpdZetEAHmQJ4VVFUU TVl2EGhjWOo7mJ5FcqPvTPhCyX+3h39auEo+hYjG2AGPstX9IxWVUXbPI Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063286" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063286" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900622985" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900622985" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:14 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id D83B410A452; Sat, 23 Dec 2023 02:52:11 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 01/16] x86/acpi: Extract ACPI MADT wakeup code into a separate file Date: Sat, 23 Dec 2023 02:51:53 +0300 Message-ID: <20231222235209.32143-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to prepare for the expansion of support for the ACPI MADT wakeup method, move the relevant code into a separate file. Introduce a new configuration option to clearly indicate dependencies without the use of ifdefs. There have been no functional changes. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Kai Huang --- arch/x86/Kconfig | 7 +++ arch/x86/include/asm/acpi.h | 5 ++ arch/x86/kernel/acpi/Makefile | 11 ++-- arch/x86/kernel/acpi/boot.c | 86 +----------------------------- arch/x86/kernel/acpi/madt_wakeup.c | 82 ++++++++++++++++++++++++++++ 5 files changed, 101 insertions(+), 90 deletions(-) create mode 100644 arch/x86/kernel/acpi/madt_wakeup.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 536586d5ef00..983959c7ec33 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1104,6 +1104,13 @@ config X86_LOCAL_APIC depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY =20 +config X86_ACPI_MADT_WAKEUP + def_bool y + depends on X86_64 + depends on ACPI + depends on SMP + depends on X86_LOCAL_APIC + config X86_IO_APIC def_bool y depends on X86_LOCAL_APIC || X86_UP_IOAPIC diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index f896eed4516c..2625b915ae7f 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -76,6 +76,11 @@ static inline bool acpi_skip_set_wakeup_address(void) =20 #define acpi_skip_set_wakeup_address acpi_skip_set_wakeup_address =20 +union acpi_subtable_headers; + +int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, + const unsigned long end); + /* * Check if the CPU can handle C2 and deeper */ diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile index fc17b3f136fe..8c7329c88a75 100644 --- a/arch/x86/kernel/acpi/Makefile +++ b/arch/x86/kernel/acpi/Makefile @@ -1,11 +1,12 @@ # SPDX-License-Identifier: GPL-2.0 =20 -obj-$(CONFIG_ACPI) +=3D boot.o -obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o -obj-$(CONFIG_ACPI_APEI) +=3D apei.o -obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o +obj-$(CONFIG_ACPI) +=3D boot.o +obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o +obj-$(CONFIG_ACPI_APEI) +=3D apei.o +obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o +obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o =20 ifneq ($(CONFIG_ACPI_PROCESSOR),) -obj-y +=3D cstate.o +obj-y +=3D cstate.o endif =20 diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 1a0dd80d81ac..171d86fe71ef 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -67,13 +67,6 @@ static bool has_lapic_cpus __initdata; static bool acpi_support_online_capable; #endif =20 -#ifdef CONFIG_X86_64 -/* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr; -/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; -#endif - #ifdef CONFIG_X86_IO_APIC /* * Locks related to IOAPIC hotplug @@ -369,60 +362,6 @@ acpi_parse_lapic_nmi(union acpi_subtable_headers * hea= der, const unsigned long e =20 return 0; } - -#ifdef CONFIG_X86_64 -static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) -{ - /* - * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). - * - * Wakeup of secondary CPUs is fully serialized in the core code. - * No need to protect acpi_mp_wake_mailbox from concurrent accesses. - */ - if (!acpi_mp_wake_mailbox) { - acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, - sizeof(*acpi_mp_wake_mailbox), - MEMREMAP_WB); - } - - /* - * Mailbox memory is shared between the firmware and OS. Firmware will - * listen on mailbox command address, and once it receives the wakeup - * command, the CPU associated with the given apicid will be booted. - * - * The value of 'apic_id' and 'wakeup_vector' must be visible to the - * firmware before the wakeup command is visible. smp_store_release() - * ensures ordering and visibility. - */ - acpi_mp_wake_mailbox->apic_id =3D apicid; - acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; - smp_store_release(&acpi_mp_wake_mailbox->command, - ACPI_MP_WAKE_COMMAND_WAKEUP); - - /* - * Wait for the CPU to wake up. - * - * The CPU being woken up is essentially in a spin loop waiting to be - * woken up. It should not take long for it wake up and acknowledge by - * zeroing out ->command. - * - * ACPI specification doesn't provide any guidance on how long kernel - * has to wait for a wake up acknowledgement. It also doesn't provide - * a way to cancel a wake up request if it takes too long. - * - * In TDX environment, the VMM has control over how long it takes to - * wake up secondary. It can postpone scheduling secondary vCPU - * indefinitely. Giving up on wake up request and reporting error opens - * possible attack vector for VMM: it can wake up a secondary CPU when - * kernel doesn't expect it. Wait until positive result of the wake up - * request. - */ - while (READ_ONCE(acpi_mp_wake_mailbox->command)) - cpu_relax(); - - return 0; -} -#endif /* CONFIG_X86_64 */ #endif /* CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1159,29 +1098,6 @@ static int __init acpi_parse_madt_lapic_entries(void) } return 0; } - -#ifdef CONFIG_X86_64 -static int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, - const unsigned long end) -{ - struct acpi_madt_multiproc_wakeup *mp_wake; - - if (!IS_ENABLED(CONFIG_SMP)) - return -ENODEV; - - mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; - if (BAD_MADT_ENTRY(mp_wake, end)) - return -EINVAL; - - acpi_table_print_madt_entry(&header->common); - - acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; - - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); - - return 0; -} -#endif /* CONFIG_X86_64 */ #endif /* CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1378,7 +1294,7 @@ static void __init acpi_process_madt(void) smp_found_config =3D 1; } =20 -#ifdef CONFIG_X86_64 +#ifdef CONFIG_X86_ACPI_MADT_WAKEUP /* * Parse MADT MP Wake entry. */ diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c new file mode 100644 index 000000000000..7f164d38bd0b --- /dev/null +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include +#include + +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr; + +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; + +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) +{ + /* + * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). + * + * Wakeup of secondary CPUs is fully serialized in the core code. + * No need to protect acpi_mp_wake_mailbox from concurrent accesses. + */ + if (!acpi_mp_wake_mailbox) { + acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * Mailbox memory is shared between the firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, the CPU associated with the given apicid will be booted. + * + * The value of 'apic_id' and 'wakeup_vector' must be visible to the + * firmware before the wakeup command is visible. smp_store_release() + * ensures ordering and visibility. + */ + acpi_mp_wake_mailbox->apic_id =3D apicid; + acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * Wait for the CPU to wake up. + * + * The CPU being woken up is essentially in a spin loop waiting to be + * woken up. It should not take long for it wake up and acknowledge by + * zeroing out ->command. + * + * ACPI specification doesn't provide any guidance on how long kernel + * has to wait for a wake up acknowledgment. It also doesn't provide + * a way to cancel a wake up request if it takes too long. + * + * In TDX environment, the VMM has control over how long it takes to + * wake up secondary. It can postpone scheduling secondary vCPU + * indefinitely. Giving up on wake up request and reporting error opens + * possible attack vector for VMM: it can wake up a secondary CPU when + * kernel doesn't expect it. Wait until positive result of the wake up + * request. + */ + while (READ_ONCE(acpi_mp_wake_mailbox->command)) + cpu_relax(); + + return 0; +} + +int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_multiproc_wakeup *mp_wake; + + mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; + if (BAD_MADT_ENTRY(mp_wake, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; + + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); + + return 0; +} --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E6D335EF5 for ; Fri, 22 Dec 2023 23:52:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P+QPByX3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289142; x=1734825142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZmHTzPhpj3spFr7sD+uYe+dYLZez9U51K7ihV5uRElk=; b=P+QPByX37oS1hVqjFrhhCMqMj1AcOO27obyldbmlD4/vDwyaqwvmH1CY ahn4W2WTLBF96CRYYZ78lxS0Urwnd41/4xE7W2cSNRu6tp0jbVWy7dIKJ 40ERqLGxOF3TZwayvVCIgOzRpVXzXtq+w86lUw2exArtDydYdhgcaburZ VHv8Q2m5tWPxfTSth33rPMCTtEXdDnT5rcyVHnEG/ntiUghK4n32cNeMQ mtv+kyFVJMfJNfAXo3sYB3LFppdwHfZBhWUhHoid5ZPMWqW/Bfqmw9PgH 4VRATHQoypjpmisddzehqQuX3pHOWjRIbqetEWq0ib09vtWac3bzn169I A==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063279" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063279" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900622983" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900622983" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:14 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id E1CBA10A465; Sat, 23 Dec 2023 02:52:11 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 02/16] x86/apic: Mark acpi_mp_wake_* variables as __ro_after_init Date: Sat, 23 Dec 2023 02:51:54 +0300 Message-ID: <20231222235209.32143-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" acpi_mp_wake_mailbox_paddr and acpi_mp_wake_mailbox initialized once during ACPI MADT init and never changed. Signed-off-by: Kirill A. Shutemov Acked-by: Kai Huang --- arch/x86/kernel/acpi/madt_wakeup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 7f164d38bd0b..cf79ea6f3007 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -6,10 +6,10 @@ #include =20 /* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr; +static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; =20 /* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox __r= o_after_init; =20 static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C8F135EF0 for ; Fri, 22 Dec 2023 23:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K2Rn8i19" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289140; x=1734825140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T8BKWP6fuDFLYxqPc0eo/JEZQ8dEYm6Dve4qyWl3al0=; b=K2Rn8i19WO6hEZQUiA3JlXhUxI8jnP1GhZLQZ485rRECWuyVNwDIzIQW Y/7KdzcnfwELsrKPZxgYJ5PK0Hv/MozAaolq0JIE4NyZKQEgVM/Dz4qf5 lU8powm1nId3rloo0qc0r8LkpIw9rUXOJfo5b7Nzs3+3oxak5shjn041W docULPa975WoQ6Mf+MWfhVhArFOX/i10Ko5vf07Q9t6Wbed9jp0lmAeCz kaDHMy+j3QLKC0bZY8luKSFv/1XeFru1eUpYUl57JkVIGlCkJZhyW0cES /jaOuKvZnhY4ZwY7rpWH3eMKq7jz86YCoiHdIGlHuF1ghYSdDeZ6sYEjX A==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063268" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063268" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900622981" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900622981" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:14 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id EC65710A471; Sat, 23 Dec 2023 02:52:11 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 03/16] cpu/hotplug: Add support for declaring CPU offlining not supported Date: Sat, 23 Dec 2023 02:51:55 +0300 Message-ID: <20231222235209.32143-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ACPI MADT mailbox wakeup method doesn't allow to offline CPU after it got woke up. Currently offlining hotplug is prevented based on the confidential computing attribute which is set for Intel TDX. But TDX is not the only possible user of the wake up method. The MADT wakeup can be implemented outside of a confidential computing environment. Offline support is a property of the wakeup method, not the CoCo implementation. Introduce cpu_hotplug_disable_offlining() that can be called to indicate that CPU offlining should be disabled. This function is going to replace CC_ATTR_HOTPLUG_DISABLED for ACPI MADT wakeup method. Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner --- include/linux/cpu.h | 2 ++ kernel/cpu.c | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/linux/cpu.h b/include/linux/cpu.h index fc8094419084..46f2e34a0c5e 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -134,6 +134,7 @@ extern void cpus_read_lock(void); extern void cpus_read_unlock(void); extern int cpus_read_trylock(void); extern void lockdep_assert_cpus_held(void); +extern void cpu_hotplug_disable_offlining(void); extern void cpu_hotplug_disable(void); extern void cpu_hotplug_enable(void); void clear_tasks_mm_cpumask(int cpu); @@ -149,6 +150,7 @@ static inline void cpus_read_lock(void) { } static inline void cpus_read_unlock(void) { } static inline int cpus_read_trylock(void) { return true; } static inline void lockdep_assert_cpus_held(void) { } +static inline void cpu_hotplug_disable_offlining(void) { } static inline void cpu_hotplug_disable(void) { } static inline void cpu_hotplug_enable(void) { } static inline int remove_cpu(unsigned int cpu) { return -EPERM; } diff --git a/kernel/cpu.c b/kernel/cpu.c index a86972a91991..a2e17f085079 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -484,6 +484,8 @@ static int cpu_hotplug_disabled; =20 DEFINE_STATIC_PERCPU_RWSEM(cpu_hotplug_lock); =20 +static bool cpu_hotplug_offline_disabled __ro_after_init; + void cpus_read_lock(void) { percpu_down_read(&cpu_hotplug_lock); @@ -543,6 +545,14 @@ static void lockdep_release_cpus_lock(void) rwsem_release(&cpu_hotplug_lock.dep_map, _THIS_IP_); } =20 +/* Declare CPU offlining not supported */ +void cpu_hotplug_disable_offlining(void) +{ + cpu_maps_update_begin(); + cpu_hotplug_offline_disabled =3D true; + cpu_maps_update_done(); +} + /* * Wait for currently running CPU hotplug operations to complete (if any) = and * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' prot= ects @@ -1522,7 +1532,8 @@ static int cpu_down_maps_locked(unsigned int cpu, enu= m cpuhp_state target) * If the platform does not support hotplug, report it explicitly to * differentiate it from a transient offlining failure. */ - if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED)) + if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED) || + cpu_hotplug_offline_disabled) return -EOPNOTSUPP; if (cpu_hotplug_disabled) return -EBUSY; --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97C3F35EEC for ; Fri, 22 Dec 2023 23:52:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Xbo/8kjW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289141; x=1734825141; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VJQoaMr9pR2fhfjF3fTtKOF3w92bT2zKgTwlCgP2JIM=; b=Xbo/8kjWDGmWccLyZ5KMJpCZgQJnYIJASOGBCWWwcC3wJKMWXxSu/A4c XcqVukOspmXrlRb7gfwbjXbpGKrhDxTY42+8UR21sKSjggS6ssXLBKCvT sskVkdRWuGkGOR8rGPAmIQoZJILQmrmkQToSmIoVjwzjr0/4OZQ/+yNre wLWg0+HwROuO2GmsK+amHPJ0NtSF1Hc00CrG1OtxsghhiQdd6bB9Dq4le K/8+8rax2gJfCNTj+RG9YCpK5MHbgnHHZF2gGyjhQT16/Ffo+NSiG4gAV lZI6xxpVO8g1LENDJjg7z30OXHnYtwn4yRZP1HTwO0Oo/YUC697KyMOdo A==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414328" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414328" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961474" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961474" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:14 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 0353E10A472; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 04/16] cpu/hotplug, x86/acpi: Disable CPU offlining for ACPI MADT wakeup Date: Sat, 23 Dec 2023 02:51:56 +0300 Message-ID: <20231222235209.32143-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT doesn't allow to offline CPU after it got woke up. Currently CPU hotplug is prevented based on the confidential computing attribute which is set for Intel TDX. But TDX is not the only possible user of the wake up method. Disable CPU offlining on ACPI MADT wakeup enumeration. Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner --- arch/x86/coco/core.c | 1 - arch/x86/kernel/acpi/madt_wakeup.c | 3 +++ include/linux/cc_platform.h | 10 ---------- kernel/cpu.c | 3 +-- 4 files changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index eeec9986570e..f07c3bb7deab 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -20,7 +20,6 @@ static bool noinstr intel_cc_platform_has(enum cc_attr at= tr) { switch (attr) { case CC_ATTR_GUEST_UNROLL_STRING_IO: - case CC_ATTR_HOTPLUG_DISABLED: case CC_ATTR_GUEST_MEM_ENCRYPT: case CC_ATTR_MEM_ENCRYPT: return true; diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index cf79ea6f3007..d222be8d7a07 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include +#include #include #include #include @@ -76,6 +77,8 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers= *header, =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; =20 + cpu_hotplug_disable_offlining(); + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 return 0; diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index cb0d6cd1c12f..d08dd65b5c43 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -80,16 +80,6 @@ enum cc_attr { * using AMD SEV-SNP features. */ CC_ATTR_GUEST_SEV_SNP, - - /** - * @CC_ATTR_HOTPLUG_DISABLED: Hotplug is not supported or disabled. - * - * The platform/OS is running as a guest/virtual machine does not - * support CPU hotplug feature. - * - * Examples include TDX Guest. - */ - CC_ATTR_HOTPLUG_DISABLED, }; =20 #ifdef CONFIG_ARCH_HAS_CC_PLATFORM diff --git a/kernel/cpu.c b/kernel/cpu.c index a2e17f085079..a81475d2a5c0 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -1532,8 +1532,7 @@ static int cpu_down_maps_locked(unsigned int cpu, enu= m cpuhp_state target) * If the platform does not support hotplug, report it explicitly to * differentiate it from a transient offlining failure. */ - if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED) || - cpu_hotplug_offline_disabled) + if (cpu_hotplug_offline_disabled) return -EOPNOTSUPP; if (cpu_hotplug_disabled) return -EBUSY; --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B428939FCF for ; Fri, 22 Dec 2023 23:52:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WvvP83FV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289150; x=1734825150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=baddqEIghmkFajP6rpIfXbNavqQAwsBb4c0/kd75gPA=; b=WvvP83FVCGF8+E/4L+Ug5+oWBK3o6AcE/Qd8PEs9qx2LRsrPcx/WU4hN wwbRxS/nhQDBxzgrXmxKMqGrxT1JYMCXq8+DooqVIuNXLSNeEMdftwHwp 8kbZwGzPGg2btMEESmwA8vHuJ9/HofnzYxdr3gNyCulCozPQJ8KdwdJ01 4xz8p74IzH0p7AWUi+BCW5pWfN6mUyjrFawl5Dp1HJ6IHI4L6ZdwZ3ek2 yWZNq0emLk0PumUSUznLLlkL6Q6ZKU4JugMamnVGO4mgj6GpC3Qy4QdtI IrW8ofZfrlh0wuHfHxeoDMA7Qet/yi6x4SiEXdOGJNEJM0dpxmS33uxCS g==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414377" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414377" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961497" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961497" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:21 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 0DB1E10A47A; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Vitaly Kuznetsov , Paolo Bonzini , Wanpeng Li Subject: [PATCHv5 05/16] x86/kvm: Do not try to disable kvmclock if it was not enabled Date: Sat, 23 Dec 2023 02:51:57 +0300 Message-ID: <20231222235209.32143-6-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kvm_guest_cpu_offline() tries to disable kvmclock regardless if it is present in the VM. It leads to write to a MSR that doesn't exist on some configurations, namely in TDX guest: unchecked MSR access error: WRMSR to 0x12 (tried to write 0x00000000000000= 00) at rIP: 0xffffffff8110687c (kvmclock_disable+0x1c/0x30) kvmclock enabling is gated by CLOCKSOURCE and CLOCKSOURCE2 KVM paravirt features. Do not disable kvmclock if it was not enabled. Signed-off-by: Kirill A. Shutemov Fixes: c02027b5742b ("x86/kvm: Disable kvmclock on all CPUs on shutdown") Reviewed-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov Cc: Paolo Bonzini Cc: Wanpeng Li --- arch/x86/kernel/kvmclock.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index fb8f52149be9..f2fff625576d 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -24,8 +24,8 @@ =20 static int kvmclock __initdata =3D 1; static int kvmclock_vsyscall __initdata =3D 1; -static int msr_kvm_system_time __ro_after_init =3D MSR_KVM_SYSTEM_TIME; -static int msr_kvm_wall_clock __ro_after_init =3D MSR_KVM_WALL_CLOCK; +static int msr_kvm_system_time __ro_after_init; +static int msr_kvm_wall_clock __ro_after_init; static u64 kvm_sched_clock_offset __ro_after_init; =20 static int __init parse_no_kvmclock(char *arg) @@ -195,7 +195,8 @@ static void kvm_setup_secondary_clock(void) =20 void kvmclock_disable(void) { - native_write_msr(msr_kvm_system_time, 0, 0); + if (msr_kvm_system_time) + native_write_msr(msr_kvm_system_time, 0, 0); } =20 static void __init kvmclock_init_mem(void) @@ -294,7 +295,10 @@ void __init kvmclock_init(void) if (kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE2)) { msr_kvm_system_time =3D MSR_KVM_SYSTEM_TIME_NEW; msr_kvm_wall_clock =3D MSR_KVM_WALL_CLOCK_NEW; - } else if (!kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE)) { + } else if (kvm_para_has_feature(KVM_FEATURE_CLOCKSOURCE)) { + msr_kvm_system_time =3D MSR_KVM_SYSTEM_TIME; + msr_kvm_wall_clock =3D MSR_KVM_WALL_CLOCK; + } else { return; } =20 --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B8D33A8EF for ; Fri, 22 Dec 2023 23:52:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZEn83f7G" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289148; x=1734825148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UdMMN4IJNx6JOqv+X+Ro6Zem59We9MEOFQRlHnVxlYc=; b=ZEn83f7Gmp117zxkDgsZIZcz1178pC6eWBlFjE/LScQ5AjCW5jcSyQEM TJEX7S5nbZOj3e6GqUmP83KwEJXuKpcjUrpyI05AuayYSktsOwBTDfmO/ 1M3PtAwF0mGQ3JexYbNlYcAVI/nbgb195NXpfn10QvzX/XKXYrTHIoHFF Ygb9eSyPcNJ34H/soTN0dQ5ASHpZRICX2Mql8+dcrjQxSWKkzWnba3Tfw rWtaRA1xbSZpaXKjR26pxShEPls6rN/3xHeT2A2T3ZC/m3VX1m7QsHzxR JnIv0SE949D8FW2/hN68b+ROOmlhc0Z9cF3YXrFePFJo2sxpvVbb4HZsQ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414336" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414336" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961489" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961489" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:21 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 17EA210A48A; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 06/16] x86/kexec: Keep CR4.MCE set during kexec for TDX guest Date: Sat, 23 Dec 2023 02:51:58 +0300 Message-ID: <20231222235209.32143-7-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX guests are not allowed to clear CR4.MCE. Attempt to clear it leads to #VE. Use alternatives to keep the flag during kexec for TDX guests. The change doesn't affect non-TDX-guest environments. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang --- arch/x86/kernel/relocate_kernel_64.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocat= e_kernel_64.S index 56cab1bb25f5..e144bcf60cbe 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -5,6 +5,8 @@ */ =20 #include +#include +#include #include #include #include @@ -145,12 +147,15 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) * Set cr4 to a known state: * - physical address extension enabled * - 5-level paging, if it was enabled before + * - Machine check exception on TDX guest. Clearing MCE is not allowed + * in TDX guests. */ movl $X86_CR4_PAE, %eax testq $X86_CR4_LA57, %r13 jz 1f orl $X86_CR4_LA57, %eax 1: + ALTERNATIVE "", __stringify(orl $X86_CR4_MCE, %eax), X86_FEATURE_TDX_GUEST movq %rax, %cr4 =20 jmp 1f --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39E7035EF9 for ; Fri, 22 Dec 2023 23:52:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GSL8kPkh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289149; x=1734825149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nv/WnNoq1dHu8FVNX2PneDS0em00Xk7L6O5tg9HvJVs=; b=GSL8kPkhw3zS1GshaAyG6gSJBwlMtNY1XXJPioaOkRe9ZY6qSZHYGX60 8/Hm2978pKenpP+eD5RIQBfMEPw2DY22KgssDE5sZfVksUfBclGIKbMu/ fsolJ9s/HkeXTfRWLUtHTX/Jqh6zf8vcxH5+mfcoOKMcGFzz96shy7EsP ah+nnS2bEfHAkpi7dvBNgdpOSxv+qh6CXCVpS1spl3DHbjJBjVzmdPANP d4ToKSoa79TzO7908c3q7fTmGyRzSlbk7V2ZkM4s0r4pLHxqsijIGSPdF A3sDb3QeYZLVYvCC1r6JuAtUXYJ0EgOxY+FzgRR4zPh9G4XTkdAQNXMd2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414367" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414367" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961495" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961495" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:21 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 22CCE10A490; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 07/16] x86/mm: Make x86_platform.guest.enc_status_change_*() return errno Date: Sat, 23 Dec 2023 02:51:59 +0300 Message-ID: <20231222235209.32143-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX is going to have more than one reason to fail enc_status_change_prepare(). Change the callback to return errno instead of assuming -EIO; enc_status_change_finish() changed too to keep the interface symmetric. Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx/tdx.c | 20 +++++++++++--------- arch/x86/hyperv/ivm.c | 9 +++------ arch/x86/include/asm/x86_init.h | 4 ++-- arch/x86/kernel/x86_init.c | 4 ++-- arch/x86/mm/mem_encrypt_amd.c | 8 ++++---- arch/x86/mm/pat/set_memory.c | 9 +++++---- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index cf1f13c82175..4397a6b2b04c 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -798,28 +798,30 @@ static bool tdx_enc_status_changed(unsigned long vadd= r, int numpages, bool enc) return true; } =20 -static bool tdx_enc_status_change_prepare(unsigned long vaddr, int numpage= s, - bool enc) +static int tdx_enc_status_change_prepare(unsigned long vaddr, int numpages, + bool enc) { /* * Only handle shared->private conversion here. * See the comment in tdx_early_init(). */ - if (enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } =20 -static bool tdx_enc_status_change_finish(unsigned long vaddr, int numpages, +static int tdx_enc_status_change_finish(unsigned long vaddr, int numpages, bool enc) { /* * Only handle private->shared conversion here. * See the comment in tdx_early_init(). */ - if (!enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } =20 void __init tdx_early_init(void) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 02e55237d919..2e1be1afeebe 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -510,13 +510,12 @@ static int hv_mark_gpa_visibility(u16 count, const u6= 4 pfn[], * with host. This function works as wrap of hv_mark_gpa_visibility() * with memory base and size. */ -static bool hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecou= nt, bool enc) +static int hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecoun= t, bool enc) { enum hv_mem_host_visibility visibility =3D enc ? VMBUS_PAGE_NOT_VISIBLE : VMBUS_PAGE_VISIBLE_READ_WRITE; u64 *pfn_array; int ret =3D 0; - bool result =3D true; int i, pfn; =20 pfn_array =3D kmalloc(HV_HYP_PAGE_SIZE, GFP_KERNEL); @@ -530,17 +529,15 @@ static bool hv_vtom_set_host_visibility(unsigned long= kbuffer, int pagecount, bo if (pfn =3D=3D HV_MAX_MODIFY_GPA_REP_COUNT || i =3D=3D pagecount - 1) { ret =3D hv_mark_gpa_visibility(pfn, pfn_array, visibility); - if (ret) { - result =3D false; + if (ret) goto err_free_pfn_array; - } pfn =3D 0; } } =20 err_free_pfn_array: kfree(pfn_array); - return result; + return ret; } =20 static bool hv_vtom_tlb_flush_required(bool private) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index c878616a18b8..c9503fe2d13a 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -150,8 +150,8 @@ struct x86_init_acpi { * @enc_cache_flush_required Returns true if a cache flush is needed befor= e changing page encryption status */ struct x86_guest { - bool (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool e= nc); - bool (*enc_status_change_finish)(unsigned long vaddr, int npages, bool en= c); + int (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool en= c); + int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc= ); bool (*enc_tlb_flush_required)(bool enc); bool (*enc_cache_flush_required)(void); }; diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index a37ebd3b4773..f0f54e109eb9 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -131,8 +131,8 @@ struct x86_cpuinit_ops x86_cpuinit =3D { =20 static void default_nmi_init(void) { }; =20 -static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages= , bool enc) { return true; } -static bool enc_status_change_finish_noop(unsigned long vaddr, int npages,= bool enc) { return true; } +static int enc_status_change_prepare_noop(unsigned long vaddr, int npages,= bool enc) { return 0; } +static int enc_status_change_finish_noop(unsigned long vaddr, int npages, = bool enc) { return 0; } static bool enc_tlb_flush_required_noop(bool enc) { return false; } static bool enc_cache_flush_required_noop(void) { return false; } static bool is_private_mmio_noop(u64 addr) {return false; } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 70b91de2e053..d314e577836d 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -283,7 +283,7 @@ static void enc_dec_hypercall(unsigned long vaddr, unsi= gned long size, bool enc) #endif } =20 -static bool amd_enc_status_change_prepare(unsigned long vaddr, int npages,= bool enc) +static int amd_enc_status_change_prepare(unsigned long vaddr, int npages, = bool enc) { /* * To maintain the security guarantees of SEV-SNP guests, make sure @@ -292,11 +292,11 @@ static bool amd_enc_status_change_prepare(unsigned lo= ng vaddr, int npages, bool if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && !enc) snp_set_memory_shared(vaddr, npages); =20 - return true; + return 0; } =20 /* Return true unconditionally: return value doesn't matter for the SEV si= de */ -static bool amd_enc_status_change_finish(unsigned long vaddr, int npages, = bool enc) +static int amd_enc_status_change_finish(unsigned long vaddr, int npages, b= ool enc) { /* * After memory is mapped encrypted in the page table, validate it @@ -308,7 +308,7 @@ static bool amd_enc_status_change_finish(unsigned long = vaddr, int npages, bool e if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) enc_dec_hypercall(vaddr, npages << PAGE_SHIFT, enc); =20 - return true; + return 0; } =20 static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc) diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index bda9f129835e..6fbf22d5fa56 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2152,8 +2152,9 @@ static int __set_memory_enc_pgtable(unsigned long add= r, int numpages, bool enc) cpa_flush(&cpa, x86_platform.guest.enc_cache_flush_required()); =20 /* Notify hypervisor that we are about to set/clr encryption attribute. */ - if (!x86_platform.guest.enc_status_change_prepare(addr, numpages, enc)) - return -EIO; + ret =3D x86_platform.guest.enc_status_change_prepare(addr, numpages, enc); + if (ret) + return ret; =20 ret =3D __change_page_attr_set_clr(&cpa, 1); =20 @@ -2168,8 +2169,8 @@ static int __set_memory_enc_pgtable(unsigned long add= r, int numpages, bool enc) =20 /* Notify hypervisor that we have successfully set/clr encryption attribu= te. */ if (!ret) { - if (!x86_platform.guest.enc_status_change_finish(addr, numpages, enc)) - ret =3D -EIO; + ret =3D x86_platform.guest.enc_status_change_finish(addr, + numpages, enc); } =20 return ret; --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A962D3B796 for ; Fri, 22 Dec 2023 23:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dDsZjT6T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289148; x=1734825148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7MgS2tz+eXb3t+LyzYLE/xkq/zAhJTq68EvRtEFLASY=; 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Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 08/16] x86/mm: Return correct level from lookup_address() if pte is none Date: Sat, 23 Dec 2023 02:52:00 +0300 Message-ID: <20231222235209.32143-9-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" lookup_address() only returns correct page table level for the entry if the entry is not none. Make the helper to always return correct 'level'. It allows to implement iterator over kernel page tables using lookup_address(). Add one more entry into enum pg_level to indicate size of VA covered by one PGD entry in 5-level paging mode. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe --- arch/x86/include/asm/pgtable_types.h | 1 + arch/x86/mm/pat/set_memory.c | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pg= table_types.h index 0b748ee16b3d..3f648ffdfbe5 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -548,6 +548,7 @@ enum pg_level { PG_LEVEL_2M, PG_LEVEL_1G, PG_LEVEL_512G, + PG_LEVEL_256T, PG_LEVEL_NUM }; =20 diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 6fbf22d5fa56..01f827eb8e80 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -666,32 +666,32 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned lon= g address, pud_t *pud; pmd_t *pmd; =20 - *level =3D PG_LEVEL_NONE; + *level =3D PG_LEVEL_256T; =20 if (pgd_none(*pgd)) return NULL; =20 + *level =3D PG_LEVEL_512G; p4d =3D p4d_offset(pgd, address); if (p4d_none(*p4d)) return NULL; =20 - *level =3D PG_LEVEL_512G; if (p4d_large(*p4d) || !p4d_present(*p4d)) return (pte_t *)p4d; =20 + *level =3D PG_LEVEL_1G; pud =3D pud_offset(p4d, address); if (pud_none(*pud)) return NULL; =20 - *level =3D PG_LEVEL_1G; if (pud_large(*pud) || !pud_present(*pud)) return (pte_t *)pud; =20 + *level =3D PG_LEVEL_2M; pmd =3D pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; =20 - *level =3D PG_LEVEL_2M; if (pmd_large(*pmd) || !pmd_present(*pmd)) return (pte_t *)pmd; =20 --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30E233B19D for ; Fri, 22 Dec 2023 23:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WuGeY3jL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289148; x=1734825148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JV7Vomm3hL/vDYDiUsjcPKFfbqW2xkr31p+WaTWWLWA=; b=WuGeY3jLHxg6Cn3fG2lMkuIx2wt8J48/9lc8yXrXM5yZQEvidEP5Kgjv LKlxfCYbUleZmrXNipBKAmvEIk0s0gBVJgVxeL7Ukn5NEcuxEwt8HpwhV wVqtCVXLUqaB4DG7QX4ldJUSjbKboSBhUcGaYcHsI8rIoPRGtX5q/ZgVI wW0FX4kJoa/FwNOyjNJ2cgp0jCnezErHOr21G8fhahLlRXBTxsjy9nf9m OLiK5ci3YlBDxTbsDkWyQ8LI7M9DK5ZtdKPgfQDA86LrFk+BFtO5NtjEo 5hR+Q4tMZhgOQQjx54yygV2RsIe+6QIxh1LE08wXAWhKdNYgN/p5MdnFm Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414346" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414346" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961491" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961491" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:21 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 387D010A4D9; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 09/16] x86/tdx: Account shared memory Date: Sat, 23 Dec 2023 02:52:01 +0300 Message-ID: <20231222235209.32143-10-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel will convert all shared memory back to private during kexec. The direct mapping page tables will provide information on which memory is shared. It is extremely important to convert all shared memory. If a page is missed, it will cause the second kernel to crash when it accesses it. Keep track of the number of shared pages. This will allow for cross-checking against the shared information in the direct mapping and reporting if the shared bit is lost. Include a debugfs interface that allows for the check to be performed at any point. Signed-off-by: Kirill A. Shutemov --- arch/x86/coco/tdx/tdx.c | 69 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 4397a6b2b04c..8a49484a2917 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "tdx: " fmt =20 #include +#include #include #include #include @@ -38,6 +39,13 @@ =20 #define TDREPORT_SUBTYPE_0 0 =20 +static atomic_long_t nr_shared; + +static inline bool pte_decrypted(pte_t pte) +{ + return cc_mkdec(pte_val(pte)) =3D=3D pte_val(pte); +} + /* Called from __tdx_hypercall() for unrecoverable failure */ noinstr void __noreturn __tdx_hypercall_failed(void) { @@ -821,6 +829,11 @@ static int tdx_enc_status_change_finish(unsigned long = vaddr, int numpages, if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) return -EIO; =20 + if (enc) + atomic_long_sub(numpages, &nr_shared); + else + atomic_long_add(numpages, &nr_shared); + return 0; } =20 @@ -896,3 +909,59 @@ void __init tdx_early_init(void) =20 pr_info("Guest detected\n"); } + +#ifdef CONFIG_DEBUG_FS +static int tdx_shared_memory_show(struct seq_file *m, void *p) +{ + unsigned long addr, end; + unsigned long found =3D 0; + + addr =3D PAGE_OFFSET; + end =3D PAGE_OFFSET + get_max_mapped(); + + while (addr < end) { + unsigned long size; + unsigned int level; + pte_t *pte; + + pte =3D lookup_address(addr, &level); + size =3D page_level_size(level); + + if (pte && pte_decrypted(*pte)) + found +=3D size / PAGE_SIZE; + + addr +=3D size; + + cond_resched(); + } + + seq_printf(m, "Number of shared pages in kernel page tables: %16lu\n", + found); + seq_printf(m, "Number of pages accounted as shared: %16ld\n", + atomic_long_read(&nr_shared)); + return 0; +} + +static int tdx_shared_memory_open(struct inode *inode, struct file *file) +{ + return single_open(file, tdx_shared_memory_show, NULL); +} + +static const struct file_operations tdx_shared_memory_fops =3D { + .open =3D tdx_shared_memory_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static __init int debug_tdx_shared_memory(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return 0; + + debugfs_create_file("tdx_shared_memory", 0400, arch_debugfs_dir, + NULL, &tdx_shared_memory_fops); + return 0; +} +fs_initcall(debug_tdx_shared_memory); +#endif --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B65E3D974 for ; Fri, 22 Dec 2023 23:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VbPuv1Xs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289150; x=1734825150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CPNyfIjhkN66pkeS9MLVNslXAiONe+c3JXdzZ/y2Vvo=; b=VbPuv1XsrqWvlNdXpr/U8j4W3U5WNs9TZ+Wpbs65hWHphgBLKd847NJ8 TrXPNdKcO++u8RDlJvGJSe8EQ1s/F5iDfYxPIhBuXTFI6e6RQFrDiShEu 78d2qzrDFbKMaoXszV+FujGezhucoFOPmLnzSIy9qYC/cDcjI5MJ1ipRj qwnAs90lxfuw/EW+lguIVN1hMIst+46JgU+dlXIhjBhaKHAk0cVlP54YR ieS0Qhe4hBf0oYraTX3t/tVkplQPb/3N+YNo6t3cGi/hzeUNBX0Rxezlc 8E+5+j85Rvg+I2SGzEDALYEaTCQoemFFkGXBSxLkkP9FpoOAQL6UN3Hwv g==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063322" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063322" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900623009" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900623009" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:22 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 43E9510A4DC; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 10/16] x86/tdx: Convert shared memory back to private on kexec Date: Sat, 23 Dec 2023 02:52:02 +0300 Message-ID: <20231222235209.32143-11-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX guests allocate shared buffers to perform I/O. It is done by allocating pages normally from the buddy allocator and converting them to shared with set_memory_decrypted(). The second kernel has no idea what memory is converted this way. It only sees E820_TYPE_RAM. Accessing shared memory via private mapping is fatal. It leads to unrecoverable TD exit. On kexec walk direct mapping and convert all shared memory back to private. It makes all RAM private again and second kernel may use it normally. The conversion occurs in two steps: stopping new conversions and unsharing all memory. In the case of normal kexec, the stopping of conversions takes place while scheduling is still functioning. This allows for waiting until any ongoing conversions are finished. The second step is carried out when all CPUs except one are inactive and interrupts are disabled. This prevents any conflicts with code that may access shared memory. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe --- arch/x86/coco/tdx/tdx.c | 119 +++++++++++++++++++++++++++++++- arch/x86/include/asm/x86_init.h | 2 + arch/x86/kernel/crash.c | 6 ++ arch/x86/kernel/reboot.c | 13 ++++ 4 files changed, 138 insertions(+), 2 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 8a49484a2917..5c64db168edd 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -6,8 +6,10 @@ =20 #include #include +#include #include #include +#include #include #include #include @@ -15,6 +17,7 @@ #include #include #include +#include =20 /* MMIO direction */ #define EPT_READ 0 @@ -41,6 +44,9 @@ =20 static atomic_long_t nr_shared; =20 +static atomic_t conversions_in_progress; +static bool conversion_allowed =3D true; + static inline bool pte_decrypted(pte_t pte) { return cc_mkdec(pte_val(pte)) =3D=3D pte_val(pte); @@ -726,6 +732,14 @@ static bool tdx_tlb_flush_required(bool private) =20 static bool tdx_cache_flush_required(void) { + /* + * Avoid issuing CLFLUSH on set_memory_decrypted() if conversions + * stopped. Otherwise it can race with unshare_all_memory() and trigger + * implicit conversion to shared. + */ + if (!conversion_allowed) + return false; + /* * AMD SME/SEV can avoid cache flushing if HW enforces cache coherence. * TDX doesn't have such capability. @@ -809,12 +823,25 @@ static bool tdx_enc_status_changed(unsigned long vadd= r, int numpages, bool enc) static int tdx_enc_status_change_prepare(unsigned long vaddr, int numpages, bool enc) { + atomic_inc(&conversions_in_progress); + + /* + * Check after bumping conversions_in_progress to serialize + * against tdx_shutdown(). + */ + if (!conversion_allowed) { + atomic_dec(&conversions_in_progress); + return -EBUSY; + } + /* * Only handle shared->private conversion here. * See the comment in tdx_early_init(). */ - if (enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + if (enc && !tdx_enc_status_changed(vaddr, numpages, enc)) { + atomic_dec(&conversions_in_progress); return -EIO; + } =20 return 0; } @@ -826,17 +853,102 @@ static int tdx_enc_status_change_finish(unsigned lon= g vaddr, int numpages, * Only handle private->shared conversion here. * See the comment in tdx_early_init(). */ - if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) { + atomic_dec(&conversions_in_progress); return -EIO; + } =20 if (enc) atomic_long_sub(numpages, &nr_shared); else atomic_long_add(numpages, &nr_shared); =20 + atomic_dec(&conversions_in_progress); + return 0; } =20 +static void tdx_kexec_stop_conversion(bool crash) +{ + /* Stop new private<->shared conversions */ + conversion_allowed =3D false; + barrier(); + + /* + * Crash kernel reaches here with interrupts disabled: can't wait for + * conversions to finish. + * + * If race happened, just report and proceed. + */ + if (!crash) { + unsigned long timeout; + + /* + * Wait for in-flight conversions to complete. + * + * Do not wait more than 30 seconds. + */ + timeout =3D 30 * USEC_PER_SEC; + while (atomic_read(&conversions_in_progress) && timeout--) + udelay(1); + } + + if (atomic_read(&conversions_in_progress)) + pr_warn("Failed to finish shared<->private conversions\n"); +} + +static void tdx_kexec_unshare_mem(void) +{ + unsigned long addr, end; + long found =3D 0, shared; + + /* + * Walk direct mapping and convert all shared memory back to private, + */ + + addr =3D PAGE_OFFSET; + end =3D PAGE_OFFSET + get_max_mapped(); + + while (addr < end) { + unsigned long size; + unsigned int level; + pte_t *pte; + + pte =3D lookup_address(addr, &level); + size =3D page_level_size(level); + + if (pte && pte_decrypted(*pte)) { + int pages =3D size / PAGE_SIZE; + + /* + * Touching memory with shared bit set triggers implicit + * conversion to shared. + * + * Make sure nobody touches the shared range from + * now on. + */ + set_pte(pte, __pte(0)); + + if (!tdx_enc_status_changed(addr, pages, true)) { + pr_err("Failed to unshare range %#lx-%#lx\n", + addr, addr + size); + } + + found +=3D pages; + } + + addr +=3D size; + } + + __flush_tlb_all(); + + shared =3D atomic_long_read(&nr_shared); + if (shared !=3D found) { + pr_err("shared page accounting is off\n"); + pr_err("nr_shared =3D %ld, nr_found =3D %ld\n", shared, found); + } +} + void __init tdx_early_init(void) { struct tdx_module_args args =3D { @@ -896,6 +1008,9 @@ void __init tdx_early_init(void) x86_platform.guest.enc_cache_flush_required =3D tdx_cache_flush_required; x86_platform.guest.enc_tlb_flush_required =3D tdx_tlb_flush_required; =20 + x86_platform.guest.enc_kexec_stop_conversion =3D tdx_kexec_stop_conversio= n; + x86_platform.guest.enc_kexec_unshare_mem =3D tdx_kexec_unshare_mem; + /* * TDX intercepts the RDMSR to read the X2APIC ID in the parallel * bringup low level code. That raises #VE which cannot be handled diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index c9503fe2d13a..3196ff20a29e 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -154,6 +154,8 @@ struct x86_guest { int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc= ); bool (*enc_tlb_flush_required)(bool enc); bool (*enc_cache_flush_required)(void); + void (*enc_kexec_stop_conversion)(bool crash); + void (*enc_kexec_unshare_mem)(void); }; =20 /** diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index c92d88680dbf..b99bd28ad22f 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -40,6 +40,7 @@ #include #include #include +#include =20 /* Used while preparing memory map entries for second kernel */ struct crash_memmap_data { @@ -107,6 +108,11 @@ void native_machine_crash_shutdown(struct pt_regs *reg= s) =20 crash_smp_send_stop(); =20 + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) { + x86_platform.guest.enc_kexec_stop_conversion(true); + x86_platform.guest.enc_kexec_unshare_mem(); + } + cpu_emergency_disable_virtualization(); =20 /* diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 830425e6d38e..16dde83df49a 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include #include +#include =20 /* * Power off function, if any @@ -716,6 +718,14 @@ static void native_machine_emergency_restart(void) =20 void native_machine_shutdown(void) { + /* + * Call enc_kexec_stop_conversion() while all CPUs are still active and + * interrupts are enabled. This will allow all in-flight memory + * conversions to finish cleanly. + */ + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) && kexec_in_progress) + x86_platform.guest.enc_kexec_stop_conversion(false); + /* Stop the cpus and apics */ #ifdef CONFIG_X86_IO_APIC /* @@ -752,6 +762,9 @@ void native_machine_shutdown(void) #ifdef CONFIG_X86_64 x86_platform.iommu_shutdown(); #endif + + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) && kexec_in_progress) + x86_platform.guest.enc_kexec_unshare_mem(); } =20 static void __machine_emergency_restart(int emergency) --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9445441206 for ; Fri, 22 Dec 2023 23:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JNvimOwO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289150; x=1734825150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YaJcwdfsbT/u6tJs5uRbj4NUFmy4HkVgm/EwY5jjC6U=; b=JNvimOwOEnMhGi4Kn6oPnmeIzsgVKtcYOcGPNQGYqycgVAeg8yxYlLAm HjjIZDqPyakJgy6ysV3eFeXv9n1mVpdQb/sQiTFd5YmYmPm+jSFh4fVB/ YqzNCkxY2A42TLu+i1GftVfaIdyloVoccxie0XmxU032g0NGPOSpt/P/n gF0dzqe9WCE4HOotfkYjUPIkYR9hMjeqRGH7Z4lsCqLkEgmGSw74IiwFL h1CjMzdYSoof7E/C0Rv7IYDY62/XObIcVt9sP2OrB1eSAiOd7u4Nokv7B HCsmdbCKXFXlSESlm9lJMVF0FUjmML2UWeEH53kFxstrdIeym4u2PhD9y w==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063331" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063331" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900623008" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900623008" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:22 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 4D67210A4DD; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 11/16] x86/mm: Make e820_end_ram_pfn() cover E820_TYPE_ACPI ranges Date: Sat, 23 Dec 2023 02:52:03 +0300 Message-ID: <20231222235209.32143-12-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" e820__end_of_ram_pfn() is used to calculate max_pfn which, among other things, guides where direct mapping ends. Any memory above max_pfn is not going to be present in the direct mapping. e820__end_of_ram_pfn() finds the end of the ram based on the highest E820_TYPE_RAM range. But it doesn't includes E820_TYPE_ACPI ranges into calculation. Despite the name, E820_TYPE_ACPI covers not only ACPI data, but also EFI tables and might be required by kernel to function properly. Usually the problem is hidden because there is some E820_TYPE_RAM memory above E820_TYPE_ACPI. But crashkernel only presents pre-allocated crash memory as E820_TYPE_RAM on boot. If the preallocated range is small, it can fit under the last E820_TYPE_ACPI range. Modify e820__end_of_ram_pfn() and e820__end_of_low_ram_pfn() to cover E820_TYPE_ACPI memory. The problem was discovered during debugging kexec for TDX guest. TDX guest uses E820_TYPE_ACPI to store the unaccepted memory bitmap and pass it between the kernels on kexec. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/e820.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index fb8cf953380d..99c80680dc9e 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -827,7 +827,7 @@ u64 __init e820__memblock_alloc_reserved(u64 size, u64 = align) /* * Find the highest page frame number we have available */ -static unsigned long __init e820_end_pfn(unsigned long limit_pfn, enum e82= 0_type type) +static unsigned long __init e820_end_ram_pfn(unsigned long limit_pfn) { int i; unsigned long last_pfn =3D 0; @@ -838,7 +838,8 @@ static unsigned long __init e820_end_pfn(unsigned long = limit_pfn, enum e820_type unsigned long start_pfn; unsigned long end_pfn; =20 - if (entry->type !=3D type) + if (entry->type !=3D E820_TYPE_RAM && + entry->type !=3D E820_TYPE_ACPI) continue; =20 start_pfn =3D entry->addr >> PAGE_SHIFT; @@ -864,12 +865,12 @@ static unsigned long __init e820_end_pfn(unsigned lon= g limit_pfn, enum e820_type =20 unsigned long __init e820__end_of_ram_pfn(void) { - return e820_end_pfn(MAX_ARCH_PFN, E820_TYPE_RAM); + return e820_end_ram_pfn(MAX_ARCH_PFN); } =20 unsigned long __init e820__end_of_low_ram_pfn(void) { - return e820_end_pfn(1UL << (32 - PAGE_SHIFT), E820_TYPE_RAM); + return e820_end_ram_pfn(1UL << (32 - PAGE_SHIFT)); } =20 static void __init early_panic(char *msg) --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE533BB36 for ; Fri, 22 Dec 2023 23:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="oJCYMgt+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289149; x=1734825149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7FoFTq51uBWBc/7DP/gCY8Z9wa/4rlsw9x9epfDBOIM=; b=oJCYMgt+q5OJv8QpE0UO2YCyc9fBPZB7G9qnW5CObkEk+43/RrZXKi6v YAcDE8WPV/yQl1n3l5b/pRstSQhudrFG+1+4nT2/FRyIDD+TDKiodu7JO qv3SIm0cz9iDJKOtRR6khYErX48U0mxAM7LiV5s8ELXTplVPOS47+FRzN dZ+GyqPJUOWY3+i+4DEbjw9RlumkkAmzvFzA83TQVYN/yDPtk9ILTwHQV ojcbC6CG9M7PzI1akPs4QU4y1ZE7TxBqRGMaNdnB/9UdHjcrJ7FFNhJ2a kPbOgokbEsG5lRlLezVwsqatxkCxrmtjBSOSIZTCtgtolOKViJ1irx3wf g==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414356" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414356" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961493" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961493" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:22 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 5570C10A4DE; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 12/16] x86/acpi: Rename fields in acpi_madt_multiproc_wakeup structure Date: Sat, 23 Dec 2023 02:52:04 +0300 Message-ID: <20231222235209.32143-13-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To prepare for the addition of support for MADT wakeup structure version 1, it is necessary to provide more appropriate names for the fields in the structure. The field 'mailbox_version' renamed as 'version'. This field signifies the version of the structure and the related protocols, rather than the version of the mailbox. This field has not been utilized in the code thus far. The field 'base_address' renamed as 'mailbox_address' to clarify the kind of address it represents. In version 1, the structure includes the reset vector address. Clear and distinct naming helps to prevent any confusion. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan --- arch/x86/kernel/acpi/madt_wakeup.c | 2 +- include/acpi/actbl2.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index d222be8d7a07..004801b9b151 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -75,7 +75,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers= *header, =20 acpi_table_print_madt_entry(&header->common); =20 - acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; + acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 cpu_hotplug_disable_offlining(); =20 diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 3751ae69432f..23b4cfb640fc 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1109,9 +1109,9 @@ struct acpi_madt_generic_translator { =20 struct acpi_madt_multiproc_wakeup { struct acpi_subtable_header header; - u16 mailbox_version; + u16 version; u32 reserved; /* reserved - must be zero */ - u64 base_address; + u64 mailbox_address; }; =20 #define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA0FF487BA for ; Fri, 22 Dec 2023 23:52:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZGY/77xH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289151; x=1734825151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YDQMXN0iVpU2YQf4aT9bqVrRqYEHM1UhuZnW8RhMhQ0=; b=ZGY/77xHyIgun13RT30RPGI6THMYQLMRaOla0YHlYDZop27HqK6Fm+zV 1chnGzYFUly2/LpR0WTfwmDJYoBXdh9KrMXZfY5dK904bVTGPTIEmqLMw 0idEyjXuEFDU0sA8d9G8eRqJdQU7Uoer8Sn+DuX2z3U+BwxgA0jwBeh6V TwbcmDYBOhsWGmz17mBKFARvVbsOKF/qIGl/lqND6bv+ljHPaMY03YVBg PaJ7AL8rXsNbNMogSDq9f63WrV8Ck9P1Fmnr3oA3NdXrqWu7ZH2GdifvB X2QNvWgf82VvMbsovH7PYXFp1VFgVtsOpT8CB5azxZMlncHgED0RtOSX2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063340" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063340" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900623013" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900623013" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:22 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 5EFCC10A4DF; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 13/16] x86/acpi: Do not attempt to bring up secondary CPUs in kexec case Date: Sat, 23 Dec 2023 02:52:05 +0300 Message-ID: <20231222235209.32143-14-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT doesn't allow to offline a CPU after it was onlined. This limits kexec: the second kernel won't be able to use more than one CPU. To prevent a kexec kernel from onlining secondary CPUs invalidate the mailbox address in the ACPI MADT wakeup structure which prevents a kexec kernel to use it. This is safe as the booting kernel has the mailbox address cached already and acpi_wakeup_cpu() uses the cached value to bring up the secondary CPUs. Note: This is a Linux specific convention and not covered by the ACPI specification. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan --- arch/x86/kernel/acpi/madt_wakeup.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 004801b9b151..30820f9de5af 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -14,6 +14,11 @@ static struct acpi_madt_multiproc_wakeup_mailbox *acpi_m= p_wake_mailbox __ro_afte =20 static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { + if (!acpi_mp_wake_mailbox_paddr) { + pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting wi= th kexec?\n"); + return -EOPNOTSUPP; + } + /* * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). * @@ -64,6 +69,28 @@ static int acpi_wakeup_cpu(u32 apicid, unsigned long sta= rt_ip) return 0; } =20 +static void acpi_mp_disable_offlining(struct acpi_madt_multiproc_wakeup *m= p_wake) +{ + cpu_hotplug_disable_offlining(); + + /* + * ACPI MADT doesn't allow to offline a CPU after it was onlined. This + * limits kexec: the second kernel won't be able to use more than one CPU. + * + * To prevent a kexec kernel from onlining secondary CPUs invalidate the + * mailbox address in the ACPI MADT wakeup structure which prevents a + * kexec kernel to use it. + * + * This is safe as the booting kernel has the mailbox address cached + * already and acpi_wakeup_cpu() uses the cached value to bring up the + * secondary CPUs. + * + * Note: This is a Linux specific convention and not covered by the + * ACPI specification. + */ + mp_wake->mailbox_address =3D 0; +} + int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, const unsigned long end) { @@ -77,7 +104,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_header= s *header, =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 - cpu_hotplug_disable_offlining(); + acpi_mp_disable_offlining(mp_wake); =20 apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2979548CE5 for ; Fri, 22 Dec 2023 23:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ToNfnQmv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289152; x=1734825152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RhnEAsovR1/on/ST7snqUo3geUenPPWRU+fc0vbg0rk=; b=ToNfnQmv693/wPJpgF6e6+MtJYG0hrOxPDPvzp7iyjtr4z3CzITutxeG cdSDiNklo9I91NAoc5Heux1RS0jYGxtdI45/dqf4zQl5XLPs39iRFoQNw B4+7ZEH/8Om2dGTv4UvVTMEqqjhUtx6Zalzirz7Z0u/P/THXlRLerBXfB q5qG8X3oe69sf3cECNiD9wM3nWcT4/JEN4RlI2MNJeZKP68rI4C33+mRu l7FA2xM1gbaYjDnBfpZKbLxN/J9Vh2s/VGNvbCuJF/rLJ7OZc1ggzFike O2Xwa/RDQiNXlqsFq4XTNNJou0O0/Owl8osl2+lND1W/OwSbz8WdYqc9v g==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="395063351" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="395063351" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="900623014" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="900623014" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:22 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 69FCD10A4E0; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 14/16] x86/smp: Add smp_ops.stop_this_cpu() callback Date: Sat, 23 Dec 2023 02:52:06 +0300 Message-ID: <20231222235209.32143-15-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the helper is defined, it is called instead of halt() to stop the CPU at the end of stop_this_cpu() and on crash CPU shutdown. ACPI MADT will use it to hand over the CPU to BIOS in order to be able to wake it up again after kexec. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/process.c | 20 +++++++++++++------- arch/x86/kernel/reboot.c | 12 ++++++++---- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 4fab2ed454f3..390d53fd34f9 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -38,6 +38,7 @@ struct smp_ops { int (*cpu_disable)(void); void (*cpu_die)(unsigned int cpu); void (*play_dead)(void); + void (*stop_this_cpu)(void); =20 void (*send_call_func_ipi)(const struct cpumask *mask); void (*send_call_func_single_ipi)(int cpu); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b6f4e8399fca..65c7971defd2 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -835,13 +835,19 @@ void __noreturn stop_this_cpu(void *dummy) */ cpumask_clear_cpu(cpu, &cpus_stop_mask); =20 - for (;;) { - /* - * Use native_halt() so that memory contents don't change - * (stack usage and variables) after possibly issuing the - * native_wbinvd() above. - */ - native_halt(); + if (smp_ops.stop_this_cpu) { + smp_ops.stop_this_cpu(); + unreachable(); + } else { + + for (;;) { + /* + * Use native_halt() so that memory contents don't + * change (stack usage and variables) after possibly + * issuing the native_wbinvd() above. + */ + native_halt(); + } } } =20 diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 16dde83df49a..738b3e810196 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -881,10 +881,14 @@ static int crash_nmi_callback(unsigned int val, struc= t pt_regs *regs) cpu_emergency_disable_virtualization(); =20 atomic_dec(&waiting_for_crash_ipi); - /* Assume hlt works */ - halt(); - for (;;) - cpu_relax(); + + if (smp_ops.stop_this_cpu) { + smp_ops.stop_this_cpu(); + } else { + halt(); + for (;;) + cpu_relax(); + } =20 return NMI_HANDLED; } --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E55C54C63A for ; Fri, 22 Dec 2023 23:52:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mCSP2jn9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289155; x=1734825155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H0KNXcx7kYiuLNhk2lubKN7E5oHJBEIlL2/mP4OOsUg=; b=mCSP2jn9kr4WoHyXb5ln9Tj0+CopPr6EAkE6svaPxvzArippZoBd1/90 5vyzyZq7q7dgYx2HgisuXWg/uN5ajLiH11TFNSmaYWfmUGc0K/0WolU85 lFqcuHAtzF6xnOcMTAgkFGX5kcHEptayo3SM+k+UUSuMja50qfv3XLgJi g2HHX4XxzQmSo9yQ/kz1KycJhJJoyzq4xs6X3eJmVN8IdKzboU/lZzLYW 8GNBf1vOFbTuvPSbLt3oHHCI9iFQhwbBCgF5HffTRrsAsU/HsZM1aGrwX DKToOnq5IRMoMUsMMbxFdBUE3xLkurp9ZKoTkx521gBLwgqdVb6RaA1xS w==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414396" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414396" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961507" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961507" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:29 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 7502410A4E1; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 15/16] x86/mm: Introduce kernel_ident_mapping_free() Date: Sat, 23 Dec 2023 02:52:07 +0300 Message-ID: <20231222235209.32143-16-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The helper complements kernel_ident_mapping_init(): it frees the identity mapping that was previously allocated. It will be used in the error path to free a partially allocated mapping or if the mapping is no longer needed. The caller provides a struct x86_mapping_info with the free_pgd_page() callback hooked up and the pgd_t to free. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang --- arch/x86/include/asm/init.h | 3 ++ arch/x86/mm/ident_map.c | 73 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h index cc9ccf61b6bd..14d72727d7ee 100644 --- a/arch/x86/include/asm/init.h +++ b/arch/x86/include/asm/init.h @@ -6,6 +6,7 @@ =20 struct x86_mapping_info { void *(*alloc_pgt_page)(void *); /* allocate buf for page table */ + void (*free_pgt_page)(void *, void *); /* free buf for page table */ void *context; /* context for alloc_pgt_page */ unsigned long page_flag; /* page flag for PMD or PUD entry */ unsigned long offset; /* ident mapping offset */ @@ -16,4 +17,6 @@ struct x86_mapping_info { int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_pa= ge, unsigned long pstart, unsigned long pend); =20 +void kernel_ident_mapping_free(struct x86_mapping_info *info, pgd_t *pgd); + #endif /* _ASM_X86_INIT_H */ diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index 968d7005f4a7..3996af7b4abf 100644 --- a/arch/x86/mm/ident_map.c +++ b/arch/x86/mm/ident_map.c @@ -4,6 +4,79 @@ * included by both the compressed kernel and the regular kernel. */ =20 +static void free_pte(struct x86_mapping_info *info, pmd_t *pmd) +{ + pte_t *pte =3D pte_offset_kernel(pmd, 0); + + info->free_pgt_page(pte, info->context); +} + +static void free_pmd(struct x86_mapping_info *info, pud_t *pud) +{ + pmd_t *pmd =3D pmd_offset(pud, 0); + int i; + + for (i =3D 0; i < PTRS_PER_PMD; i++) { + if (!pmd_present(pmd[i])) + continue; + + if (pmd_leaf(pmd[i])) + continue; + + free_pte(info, &pmd[i]); + } + + info->free_pgt_page(pmd, info->context); +} + +static void free_pud(struct x86_mapping_info *info, p4d_t *p4d) +{ + pud_t *pud =3D pud_offset(p4d, 0); + int i; + + for (i =3D 0; i < PTRS_PER_PUD; i++) { + if (!pud_present(pud[i])) + continue; + + if (pud_leaf(pud[i])) + continue; + + free_pmd(info, &pud[i]); + } + + info->free_pgt_page(pud, info->context); +} + +static void free_p4d(struct x86_mapping_info *info, pgd_t *pgd) +{ + p4d_t *p4d =3D p4d_offset(pgd, 0); + int i; + + for (i =3D 0; i < PTRS_PER_P4D; i++) { + if (!p4d_present(p4d[i])) + continue; + + free_pud(info, &p4d[i]); + } + + if (pgtable_l5_enabled()) + info->free_pgt_page(pgd, info->context); +} + +void kernel_ident_mapping_free(struct x86_mapping_info *info, pgd_t *pgd) +{ + int i; + + for (i =3D 0; i < PTRS_PER_PGD; i++) { + if (!pgd_present(pgd[i])) + continue; + + free_p4d(info, &pgd[i]); + } + + info->free_pgt_page(pgd, info->context); +} + static void ident_pmd_init(struct x86_mapping_info *info, pmd_t *pmd_page, unsigned long addr, unsigned long end) { --=20 2.41.0 From nobody Sat Dec 27 05:12:26 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6594CB4A for ; Fri, 22 Dec 2023 23:52:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ar4JDL0W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703289155; x=1734825155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Dc0fn0cOYNmC+8faZxlk7oVgDvtAyOINKlu8wudYcPc=; b=Ar4JDL0WjUpqFQb/BnCXZDeNblQJUgljxtZwRua6pBz+FU/2gRMtVkRt PUF6SG79nBmhvFyG6kHp6vAc80Ya5s7Th6U6mGgHnSpLdpzupxpDkEl3C mpWNTPWUiq2F+EAnLNKI8Yx9Rypbp2oBVMivEj0lKYd5cNZxInF7ZUkwa nRSI5uycsvblB+oQ7bpJmldKTb88/9j1FlyssyGmEsbMDFdRD9ahXdzJF aiZ/LqnVUS5WQKdmTdVC+mi7vlOrXarU+U+J6rhcOYBv3a+1zqyYG3t+9 jfEgZiYZqhkcRvFrR1EMLLYOcLne5dCVEPieNRCjI42WPytIJAQtbhYIc w==; X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="3414404" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="3414404" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10932"; a="726961509" X-IronPort-AV: E=Sophos;i="6.04,297,1695711600"; d="scan'208";a="726961509" Received: from jeroenke-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.249.35.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Dec 2023 15:52:29 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id 809C110A4E3; Sat, 23 Dec 2023 02:52:12 +0300 (+03) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv5 16/16] x86/acpi: Add support for CPU offlining for ACPI MADT wakeup method Date: Sat, 23 Dec 2023 02:52:08 +0300 Message-ID: <20231222235209.32143-17-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> References: <20231222235209.32143-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MADT Multiprocessor Wakeup structure version 1 brings support of CPU offlining: BIOS provides a reset vector where the CPU has to jump to for offlining itself. The new TEST mailbox command can be used to test whether the CPU offlined itself which means the BIOS has control over the CPU and can online it again via the ACPI MADT wakeup method. Add CPU offling support for the ACPI MADT wakeup method by implementing custom cpu_die(), play_dead() and stop_this_cpu() SMP operations. CPU offlining makes is possible to hand over secondary CPUs over kexec, not limiting the second kernel to a single CPU. The change conforms to the approved ACPI spec change proposal. See the Link. Signed-off-by: Kirill A. Shutemov Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher --- arch/x86/include/asm/acpi.h | 2 + arch/x86/kernel/acpi/Makefile | 2 +- arch/x86/kernel/acpi/madt_playdead.S | 29 +++++ arch/x86/kernel/acpi/madt_wakeup.c | 184 ++++++++++++++++++++++++++- include/acpi/actbl2.h | 15 ++- 5 files changed, 228 insertions(+), 4 deletions(-) create mode 100644 arch/x86/kernel/acpi/madt_playdead.S diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 2625b915ae7f..021cafa214c2 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -81,6 +81,8 @@ union acpi_subtable_headers; int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, const unsigned long end); =20 +void asm_acpi_mp_play_dead(u64 reset_vector, u64 pgd_pa); + /* * Check if the CPU can handle C2 and deeper */ diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile index 8c7329c88a75..37b1f28846de 100644 --- a/arch/x86/kernel/acpi/Makefile +++ b/arch/x86/kernel/acpi/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_ACPI) +=3D boot.o obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o obj-$(CONFIG_ACPI_APEI) +=3D apei.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o -obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o +obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o madt_playdead.o =20 ifneq ($(CONFIG_ACPI_PROCESSOR),) obj-y +=3D cstate.o diff --git a/arch/x86/kernel/acpi/madt_playdead.S b/arch/x86/kernel/acpi/ma= dt_playdead.S new file mode 100644 index 000000000000..e48049959513 --- /dev/null +++ b/arch/x86/kernel/acpi/madt_playdead.S @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include + + .text + .align PAGE_SIZE + +/* + * asm_acpi_mp_play_dead() - Hand over control of the CPU to the BIOS + * + * rdi: Address of the ACPI MADT MPWK ResetVector + * rsi: PGD of the identity mapping + */ +SYM_FUNC_START(asm_acpi_mp_play_dead) + /* Turn off global entries. Following CR3 write will flush them. */ + movq %cr4, %rdx + andq $~(X86_CR4_PGE), %rdx + movq %rdx, %cr4 + + /* Switch to identity mapping */ + movq %rsi, %rax + movq %rax, %cr3 + + /* Jump to reset vector */ + ANNOTATE_RETPOLINE_SAFE + jmp *%rdi +SYM_FUNC_END(asm_acpi_mp_play_dead) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 30820f9de5af..9e984e2191ba 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -1,10 +1,19 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include #include +#include #include +#include +#include +#include +#include #include #include +#include +#include +#include #include +#include =20 /* Physical address of the Multiprocessor Wakeup Structure mailbox */ static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; @@ -12,6 +21,154 @@ static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; /* Virtual address of the Multiprocessor Wakeup Structure mailbox */ static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox __r= o_after_init; =20 +static u64 acpi_mp_pgd __ro_after_init; +static u64 acpi_mp_reset_vector_paddr __ro_after_init; + +static void acpi_mp_stop_this_cpu(void) +{ + asm_acpi_mp_play_dead(acpi_mp_reset_vector_paddr, acpi_mp_pgd); +} + +static void acpi_mp_play_dead(void) +{ + play_dead_common(); + asm_acpi_mp_play_dead(acpi_mp_reset_vector_paddr, acpi_mp_pgd); +} + +static void acpi_mp_cpu_die(unsigned int cpu) +{ + u32 apicid =3D per_cpu(x86_cpu_to_apicid, cpu); + unsigned long timeout; + + /* + * Use TEST mailbox command to prove that BIOS got control over + * the CPU before declaring it dead. + * + * BIOS has to clear 'command' field of the mailbox. + */ + acpi_mp_wake_mailbox->apic_id =3D apicid; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_TEST); + + /* Don't wait longer than a second. */ + timeout =3D USEC_PER_SEC; + while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + udelay(1); + + if (!timeout) + pr_err("Failed to hand over CPU %d to BIOS\n", cpu); +} + +/* The argument is required to match type of x86_mapping_info::alloc_pgt_p= age */ +static void __init *alloc_pgt_page(void *dummy) +{ + return memblock_alloc(PAGE_SIZE, PAGE_SIZE); +} + +static void __init free_pgt_page(void *pgt, void *dummy) +{ + return memblock_free(pgt, PAGE_SIZE); +} + +/* + * Make sure asm_acpi_mp_play_dead() is present in the identity mapping at + * the same place as in the kernel page tables. asm_acpi_mp_play_dead() sw= itches + * to the identity mapping and the function has be present at the same spo= t in + * the virtual address space before and after switching page tables. + */ +static int __init init_transition_pgtable(pgd_t *pgd) +{ + pgprot_t prot =3D PAGE_KERNEL_EXEC_NOENC; + unsigned long vaddr, paddr; + p4d_t *p4d; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + + vaddr =3D (unsigned long)asm_acpi_mp_play_dead; + pgd +=3D pgd_index(vaddr); + if (!pgd_present(*pgd)) { + p4d =3D (p4d_t *)alloc_pgt_page(NULL); + if (!p4d) + return -ENOMEM; + set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE)); + } + p4d =3D p4d_offset(pgd, vaddr); + if (!p4d_present(*p4d)) { + pud =3D (pud_t *)alloc_pgt_page(NULL); + if (!pud) + return -ENOMEM; + set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); + } + pud =3D pud_offset(p4d, vaddr); + if (!pud_present(*pud)) { + pmd =3D (pmd_t *)alloc_pgt_page(NULL); + if (!pmd) + return -ENOMEM; + set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); + } + pmd =3D pmd_offset(pud, vaddr); + if (!pmd_present(*pmd)) { + pte =3D (pte_t *)alloc_pgt_page(NULL); + if (!pte) + return -ENOMEM; + set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); + } + pte =3D pte_offset_kernel(pmd, vaddr); + + paddr =3D __pa(vaddr); + set_pte(pte, pfn_pte(paddr >> PAGE_SHIFT, prot)); + + return 0; +} + +static int __init acpi_mp_setup_reset(u64 reset_vector) +{ + pgd_t *pgd; + struct x86_mapping_info info =3D { + .alloc_pgt_page =3D alloc_pgt_page, + .free_pgt_page =3D free_pgt_page, + .page_flag =3D __PAGE_KERNEL_LARGE_EXEC, + .kernpg_flag =3D _KERNPG_TABLE_NOENC, + }; + + pgd =3D alloc_pgt_page(NULL); + if (!pgd) + return -ENOMEM; + + for (int i =3D 0; i < nr_pfn_mapped; i++) { + unsigned long mstart, mend; + + mstart =3D pfn_mapped[i].start << PAGE_SHIFT; + mend =3D pfn_mapped[i].end << PAGE_SHIFT; + if (kernel_ident_mapping_init(&info, pgd, mstart, mend)) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + } + + if (kernel_ident_mapping_init(&info, pgd, + PAGE_ALIGN_DOWN(reset_vector), + PAGE_ALIGN(reset_vector + 1))) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + + if (init_transition_pgtable(pgd)) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + + smp_ops.play_dead =3D acpi_mp_play_dead; + smp_ops.stop_this_cpu =3D acpi_mp_stop_this_cpu; + smp_ops.cpu_die =3D acpi_mp_cpu_die; + + acpi_mp_reset_vector_paddr =3D reset_vector; + acpi_mp_pgd =3D __pa(pgd); + + return 0; +} + static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { if (!acpi_mp_wake_mailbox_paddr) { @@ -97,14 +254,37 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, struct acpi_madt_multiproc_wakeup *mp_wake; =20 mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; - if (BAD_MADT_ENTRY(mp_wake, end)) + + /* + * Cannot use the standard BAD_MADT_ENTRY() to sanity check the @mp_wake + * entry. 'sizeof (struct acpi_madt_multiproc_wakeup)' can be larger + * than the actual size of the MP wakeup entry in ACPI table because the + * 'reset_vector' is only available in the V1 MP wakeup structure. + */ + if (!mp_wake) + return -EINVAL; + if (end - (unsigned long)mp_wake < ACPI_MADT_MP_WAKEUP_SIZE_V0) + return -EINVAL; + if (mp_wake->header.length < ACPI_MADT_MP_WAKEUP_SIZE_V0) return -EINVAL; =20 acpi_table_print_madt_entry(&header->common); =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 - acpi_mp_disable_offlining(mp_wake); + if (mp_wake->version >=3D ACPI_MADT_MP_WAKEUP_VERSION_V1 && + mp_wake->header.length >=3D ACPI_MADT_MP_WAKEUP_SIZE_V1) { + if (acpi_mp_setup_reset(mp_wake->reset_vector)) { + pr_warn("Failed to setup MADT reset vector\n"); + acpi_mp_disable_offlining(mp_wake); + } + } else { + /* + * CPU offlining requires version 1 of the ACPI MADT wakeup + * structure. + */ + acpi_mp_disable_offlining(mp_wake); + } =20 apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 23b4cfb640fc..8348bf46a648 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1112,8 +1112,20 @@ struct acpi_madt_multiproc_wakeup { u16 version; u32 reserved; /* reserved - must be zero */ u64 mailbox_address; + u64 reset_vector; }; =20 +/* Values for Version field above */ + +enum acpi_madt_multiproc_wakeup_version { + ACPI_MADT_MP_WAKEUP_VERSION_NONE =3D 0, + ACPI_MADT_MP_WAKEUP_VERSION_V1 =3D 1, + ACPI_MADT_MP_WAKEUP_VERSION_RESERVED =3D 2, /* 2 and greater are reserved= */ +}; + +#define ACPI_MADT_MP_WAKEUP_SIZE_V0 16 +#define ACPI_MADT_MP_WAKEUP_SIZE_V1 24 + #define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 #define ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048 =20 @@ -1126,7 +1138,8 @@ struct acpi_madt_multiproc_wakeup_mailbox { u8 reserved_firmware[ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE]; /* reserved= for firmware use */ }; =20 -#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_TEST 2 =20 /* 17: CPU Core Interrupt Controller (ACPI 6.5) */ =20 --=20 2.41.0