From nobody Fri Dec 19 20:14:42 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C815F6EB52; Thu, 21 Dec 2023 12:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="nZYdRje7" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BL8YIDr028789; Thu, 21 Dec 2023 13:29:46 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=xJ81R9NAdDJJiqPYazGrWf5dZ1/fmMyctvdLKM1z2P0=; b=nZ YdRje7xbq5Ki0glAOqYQP/3/+tMdRO0DbtczBILnRbAXC0z2G7xPGH9STomR2mW1 BbWeIJg98kI7bS17JjukNNt1/4sc6m4e1H/UonO+t2gFQkbsJR9kVG3R/ybHdsAn jklAGTUhgtprtp/ouBpwq8VYXqwAMuTycKvLnHh09Fg3Vty0NWucqnv0h9boR8ei GmStFt1VeHK37lbXBTRMqOP0Mh1/88Cdcczp8BVpKXndq7cEklqsATExnRf5vCFz evlzVlB4gJAVMmv4uCDuxMb2otZaV3zcS0KCXsrGA19NjgQMbl1i+yptS6vd3Mup k0YeQYSdiOI10EdwSpLQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v4hyh99k6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 13:29:45 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4B35110005F; Thu, 21 Dec 2023 13:29:44 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3EB8D208006; Thu, 21 Dec 2023 13:29:44 +0100 (CET) Received: from localhost (10.252.25.159) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Dec 2023 13:29:43 +0100 From: Raphael Gallais-Pou To: Laurent Pinchart , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , Philipp Zabel , Lad Prabhakar , Thierry Reding CC: , , , , Subject: [PATCH v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device Date: Thu, 21 Dec 2023 13:28:37 +0100 Message-ID: <20231221122843.418650-3-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231221122843.418650-1-raphael.gallais-pou@foss.st.com> References: <20231221122843.418650-1-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-21_05,2023-12-20_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Add dt-binding file for "st,stm32-lvds" compatible. Signed-off-by: Raphael Gallais-Pou --- .../bindings/display/st,stm32-lvds.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds= .yaml diff --git a/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml b= /Documentation/devicetree/bindings/display/st,stm32-lvds.yaml new file mode 100644 index 000000000000..d72c9088133c --- /dev/null +++ b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/st,stm32-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 LVDS Display Interface Transmitter + +maintainers: + - Raphael Gallais-Pou + - Yannick Fertre + +description: | + The STMicroelectronics STM32 LVDS Display Interface Transmitter handles = the + LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (= LTDC) + onto the LVDS PHY. + + It regroups three sub blocks: + - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its in= put + pixels onto the data lanes of the PHY + - LVDS PHY: parallelize the data and drives the LVDS data lanes + - LVDS wrapper: handles top-level settings + + The LVDS controller driver supports the following high-level features: + - FDP-Link-I and OpenLDI (v0.95) protocols + - Single-Link or Dual-Link operation + - Single-Display or Double-Display (with the same content duplicated o= n both) + - Flexible Bit-Mapping, including JEIDA and VESA + - RGB888 or RGB666 output + - Synchronous design, with one input pixel per clock cycle + +properties: + "#clock-cells": + const: 0 + + compatible: + const: st,stm32-lvds + + reg: + maxItems: 1 + + clocks: + items: + - description: APB peripheral clock + - description: Reference clock for the internal PLL + + clock-names: + items: + - const: pclk + - const: ref + + resets: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: | + LVDS input port node, connected to the LTDC RGB output port. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + LVDS output port node, connected to a panel or bridge input port. + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + - resets + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + lvds: lvds@48060000 { + #clock-cells =3D <0>; + compatible =3D "st,stm32-lvds"; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + lvds_in: endpoint { + remote-endpoint =3D <<dc_ep1_out>; + }; + }; + + port@1 { + reg =3D <1>; + lvds_out0: endpoint { + remote-endpoint =3D <&lvds_panel_in>; + }; + }; + }; + }; + +... --=20 2.25.1