From nobody Fri Sep 12 09:01:07 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA0E94B5A7; Wed, 20 Dec 2023 21:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="yz8SD++u" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1703107073; bh=N62km21T/WA812DJZg7FAQPI49dJTRMBzG/fnA558jA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=yz8SD++uw56ihkugPEE4P4jPLuGKHkRkCuxtrqCn4B+ZWcKhumEvdL8QV4hcZ3U93 ffolGpnHcA/CjUdLZehOi8jsPLEz2OYdvbNOYvKJcf+Xeiy68XoyiWtFPiZrATAxT9 3mHgB2qZvIgQnhzUooDt0TFDyzNH/bP5U/4dKFNp4zcsx/Kc1A7VQHnuUcyUy+IIb0 FTaX/nL9n+Ndm+oJHRisF8Srj01K18a+zlvsZE0bfZmhDI9BLUceGJg1AVUroC9pcE 7fQ8EQD2LikQ7nYpeEy/5OglYotRBs2FyK26qL4V7/7N3Z2k6zHvG9/uVV1pCwxZwt du0IX2fIQPEkA== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 06BF23781FF5; Wed, 20 Dec 2023 21:17:52 +0000 (UTC) From: Cristian Ciocaltea To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , Andrew Lunn , Jacob Keller Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, kernel@collabora.com, Emil Renner Berthing Subject: [PATCH v6 1/4] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Date: Wed, 20 Dec 2023 23:17:39 +0200 Message-ID: <20231220211743.2490518-2-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> References: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide the sysmain and gmac DT nodes supporting the DWMAC found on the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Reviewed-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index c216aaecac53..2ebdebe6a81c 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -204,6 +204,37 @@ sdio1: mmc@10010000 { status =3D "disabled"; }; =20 + gmac: ethernet@10020000 { + compatible =3D "starfive,jh7100-dwmac", "snps,dwmac"; + reg =3D <0x0 0x10020000 0x0 0x10000>; + clocks =3D <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_TX_INV>, + <&clkgen JH7100_CLK_GMAC_GTX>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; + resets =3D <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names =3D "ahb"; + interrupts =3D <6>, <7>; + interrupt-names =3D "macirq", "eth_wake_irq"; + max-frame-size =3D <9000>; + snps,multicast-filter-bins =3D <32>; + snps,perfect-filter-entries =3D <128>; + starfive,syscon =3D <&sysmain 0x70 0>; + rx-fifo-depth =3D <32768>; + tx-fifo-depth =3D <16384>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + status =3D "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <16>; + snps,rd_osr_lmt =3D <16>; + snps,blen =3D <256 128 64 32 0 0 0>; + }; + }; + clkgen: clock-controller@11800000 { compatible =3D "starfive,jh7100-clkgen"; reg =3D <0x0 0x11800000 0x0 0x10000>; @@ -218,6 +249,11 @@ rstgen: reset-controller@11840000 { #reset-cells =3D <1>; }; =20 + sysmain: syscon@11850000 { + compatible =3D "starfive,jh7100-sysmain", "syscon"; + reg =3D <0x0 0x11850000 0x0 0x10000>; + }; + i2c0: i2c@118b0000 { compatible =3D "snps,designware-i2c"; reg =3D <0x0 0x118b0000 0x0 0x10000>; --=20 2.43.0 From nobody Fri Sep 12 09:01:07 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27D11495D5; Wed, 20 Dec 2023 21:17:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="WQLSZXuD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1703107074; bh=xs6TIYSXHQI0In49A4/5cc954c7s8z1QQPzJQM1D+vg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WQLSZXuD9bQ3Aid8sl5ikYYAXwKMcp71zth2mQQnhv6+3UX7tjfmgCL9+v23ERUdm 4HFY9l3dmrnhKyLj/ywyZt0lu85Bi1BW9Oy+azKbcq0hpkdTfHSki/BkS3SBeI9pKJ PcPiLeezH+4S2NuHI1fGyIHwLEbUp2Jjn8YUt9vcFlFfDuR0+z0O7+bsRUlv0UzZxC ow520/mexsYB/4tKzRl4CtwfKroHQ02qYALz/ETQ4bIRgJ/Yc0Tn4JhIBL2bRl2SNx rEA+s7N7DetUzzJHcqqzFo4346lmo4MIUFb1gxr/EbYqXzUUPC9uhMMCvFTqhXJTse +bh5jMS8p5TmQ== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 36A403781FF7; Wed, 20 Dec 2023 21:17:54 +0000 (UTC) From: Cristian Ciocaltea To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , Andrew Lunn , Jacob Keller Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, kernel@collabora.com, Emil Renner Berthing Subject: [PATCH v6 2/4] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Date: Wed, 20 Dec 2023 23:17:40 +0200 Message-ID: <20231220211743.2490518-3-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> References: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinmux configuration for DWMAC found on the JH7100 based boards and enable the related DT node, providing a basic PHY configuration. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Reviewed-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-common.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7100-common.dtsi index 42fb61c36068..bcba08e5bdf2 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -72,7 +72,91 @@ wifi_pwrseq: wifi-pwrseq { }; }; =20 +&gmac { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac_pins>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + }; +}; + &gpio { + gmac_pins: gmac-0 { + gtxclk-pins { + pins =3D ; + bias-pull-up; + drive-strength =3D <35>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + miitxclk-pins { + pins =3D ; + bias-pull-up; + drive-strength =3D <14>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + tx-pins { + pins =3D , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength =3D <35>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + rxclk-pins { + pins =3D ; + bias-pull-up; + drive-strength =3D <14>; + input-enable; + input-schmitt-disable; + slew-rate =3D <6>; + }; + rxer-pins { + pins =3D ; + bias-pull-up; + drive-strength =3D <14>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + rx-pins { + pins =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength =3D <14>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =3D To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , Andrew Lunn , Jacob Keller Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, kernel@collabora.com, Emil Renner Berthing Subject: [PATCH v6 3/4] riscv: dts: starfive: visionfive-v1: Setup ethernet phy Date: Wed, 20 Dec 2023 23:17:41 +0200 Message-ID: <20231220211743.2490518-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> References: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires manual adjustment of the RX internal delay to work properly. The default RX delay provided by the driver is 1.95 ns, which proves to be too high. Applying a 50% reduction seems to mitigate the issue. Also note this adjustment is not necessary on BeagleV Starlight SBC, which uses a Microchip PHY. Hence, there is no indication of a misbehaviour on the GMAC side, but most likely the issue stems from the Motorcomm PHY. While at it, drop the redundant gpio include, which is already provided by jh7100-common.dtsi. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Reviewed-by: Andrew Lunn Reviewed-by: Emil Renner Berthing --- .../jh7100-starfive-visionfive-v1.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts= b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts index e82af72f1aaf..692c696e1ab4 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts +++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts @@ -6,7 +6,6 @@ =20 /dts-v1/; #include "jh7100-common.dtsi" -#include =20 / { model =3D "StarFive VisionFive V1"; @@ -18,3 +17,24 @@ gpio-restart { priority =3D <224>; }; }; + +&gmac { + phy-handle =3D <&phy>; +}; + +/* + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires + * manual adjustment of the RX internal delay to work properly. The defau= lt + * RX delay provided by the driver (1.95ns) is too high, but applying a 50% + * reduction seems to mitigate the issue. + * + * It is worth noting the adjustment is not necessary on BeagleV Starlight= SBC, + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is th= e one + * responsible for the misbehaviour, not the GMAC. + */ +&mdio { + phy: ethernet-phy@0 { + reg =3D <0>; + rx-internal-delay-ps =3D <900>; + }; +}; --=20 2.43.0 From nobody Fri Sep 12 09:01:07 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3545949F91; Wed, 20 Dec 2023 21:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Q/HcKx3K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1703107076; bh=37wq8EvaXAv6qpmVVQ0SX1h3lDNflSuVmabgoslzXDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/HcKx3KSSfIZx2jNlI9Jnvh+gK+4HmglWjlG2yRIfS5zpeXnoouGLXeAuHAMB/cZ M1REcYuMl4N7EX6EB/s59zUw+jfUpeggxKXl2kSIMS+RwzcdPWq2Wjz8r4DxlR+SPe vLJczZsC+5XNlEePfRW2MBp6i/NMHNhX9xILvywIKr87dg/BRIFqHfznMeeB6asjqq ViBzoWjWLmvdNW6Hd3xEC8xu9T2+e1iuTjw2oTc94hgUK7qbBeYyBxcQloQHCpyUC1 3jvgNVv5ZqWK6UgRDHywtK1jhaHYElSnEc8VO2DfdiZrZR6OoS6bbR4wldB4daEBee b/fHkSxP8Z+bQ== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 8A9093781FF6; Wed, 20 Dec 2023 21:17:56 +0000 (UTC) From: Cristian Ciocaltea To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , Andrew Lunn , Jacob Keller Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, kernel@collabora.com, Emil Renner Berthing Subject: [PATCH v6 4/4] riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio Date: Wed, 20 Dec 2023 23:17:42 +0200 Message-ID: <20231220211743.2490518-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> References: <20231220211743.2490518-1-cristian.ciocaltea@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting RGMII-ID which doesn't require any particular setup, other than defining a reset gpio, as opposed to VisionFive V1 for which the RX internal delay had to be adjusted. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Reviewed-by: Emil Renner Berthing --- .../boot/dts/starfive/jh7100-beaglev-starlight.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/ar= ch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts index 7cda3a89020a..168f5d9895a9 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts @@ -11,3 +11,14 @@ / { model =3D "BeagleV Starlight Beta"; compatible =3D "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; }; + +&gmac { + phy-handle =3D <&phy>; +}; + +&mdio { + phy: ethernet-phy@7 { + reg =3D <7>; + reset-gpios =3D <&gpio 63 GPIO_ACTIVE_LOW>; + }; +}; --=20 2.43.0