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([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:40 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 1/6] riscv: add ISA extension parsing for Ztso Date: Wed, 20 Dec 2023 16:57:17 +0100 Message-ID: <20231220155723.684081-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support to parse the Ztso string in the riscv,isa string. The bindings already supports it but not the ISA parsing code. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2438d4685da6..3b31efe2f716 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -84,6 +84,7 @@ #define RISCV_ISA_EXT_ZVFH 69 #define RISCV_ISA_EXT_ZVFHMIN 70 #define RISCV_ISA_EXT_ZFA 71 +#define RISCV_ISA_EXT_ZTSO 72 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dc0ab3e97cd2..3eb48a0eecb3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -279,6 +279,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), --=20 2.43.0 From nobody Fri Dec 19 14:07:42 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5BA74174F for ; Wed, 20 Dec 2023 15:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="RoYL/K3r" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40d08be5fdbso10635415e9.1 for ; Wed, 20 Dec 2023 07:57:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087862; x=1703692662; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fxiI83AWHviDA1K2goPpANE3T3h3Nt6zkBhZOZxUOr0=; b=RoYL/K3rrFgCrlnZqqBBy1WQKpn8tuoOwu/RMvWGGtEL4YHm4vdP89F6O/X+8lvnp+ kD/0IA7Wdx4CDGlQmKC0sIv261QA3AdEADsfkqCvFscesjtW3VxEeh/kZ9m0AHY1GzpJ s9No/LZfVBootxsNxi95SrEliVIGqaER+hK6y97eC7xDh7reraaEjnna3e0eXCzkEPfz Wzk5DbJ66vVDu9bYBan5EZ6F690HQ6+JlkzuKlPrvSvOBJYKa5iIGktBvFGnVFgT32eP gyqIibPfjuemvvJGzb0MiySImjHs8hUxPRdeRQ1H9Ohdyj24KxDpgVJTPoTyfIv0gV1t b8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087862; x=1703692662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fxiI83AWHviDA1K2goPpANE3T3h3Nt6zkBhZOZxUOr0=; b=C6/ww1brTjw2wH8F75HdspzzUxxiQtWn+3i1JMceZLjWyQlgIUR0i7ZVn3Yp7pmQTV LFuuLurreYcRPMney24EbiodJzQ1JgCZfRg3dbHdx14mGF6oyZyiyApvn9HyK7PW3fvR jA/ZqX72u9Y3633pJG+vkJtuexeGuIRy40GvGXAb5ywNCVCJ4w73y7/8qlURxy2vd6Uq Hq5tVWfZu0G8H7eNa13D++fYT4vO9A4dPwwh/tO6ISPZ/TDG96M1MBeSXGAAXe9wEMFI DfzJfPdQNuWDXkAeT+Z/dHPJVNF2XI4ZHM6r3yJTlDgCllUJduWTg4KJVb+Gd5rub+ZN QowQ== X-Gm-Message-State: AOJu0YzG16QWRMoixMXrGjAYruXrpAQLNLE+Oc3HS8dkAfYYOxRJkHCu 9RJPzf/0/ZRnI9LglvcOaMK/VA== X-Google-Smtp-Source: AGHT+IFJbjR0PbYZ8f2Ct75zHWOpr+wt21lqG0IGhwGx4TEjDmQ++1Z336t5tRomVVKE9Pyr/5CpGA== X-Received: by 2002:a05:600c:214c:b0:40d:35c9:7b86 with SMTP id v12-20020a05600c214c00b0040d35c97b86mr1498909wml.4.1703087861906; Wed, 20 Dec 2023 07:57:41 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:41 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 2/6] riscv: hwprobe: export Ztso ISA extension Date: Wed, 20 Dec 2023 16:57:18 +0100 Message-ID: <20231220155723.684081-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Export the Ztso extension to userspace. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 41463b932268..10bd7b170118 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -161,6 +161,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 91fbe1a7f2e2..01ac3dc196e5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -56,6 +56,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f0bd7b480b7f..6564fa9e7a7f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -174,6 +174,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); + EXT_KEY(ZTSO); =20 if (has_vector()) { EXT_KEY(ZVBB); --=20 2.43.0 From nobody Fri Dec 19 14:07:42 2025 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E9AC45C18 for ; Wed, 20 Dec 2023 15:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="vAPPsmdx" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-50e3803643cso880006e87.1 for ; Wed, 20 Dec 2023 07:57:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087863; x=1703692663; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=szFuFOaVPRcoa/3KGK9k9VHnKNMXDyjWXMloTHpkWuA=; b=vAPPsmdxmpPkKNHR7Q6UiwoHoIUub4UZ2JgBahZHAT3mql7Ys/tWKMdaxz5nZo8A8t +L1ssKIjhyYgBuZm3ArJmPa217f7sO2MvsTwuiVhtTLVVh/cPvmb5gDhDgrTtKb7IEmh yZSUxK3+Q2XeYJVW31c0Jl/hWok0zkAjukQ3W46MwgMku8e0qze69tJsIf/5iKOaaJDq jC3mvFsQNnydzz7UPE2u2AZzhpxdpeqZBVcrrDrZ/5kvAhbNjsdOk/fK/mEXINd5uEoR whQvqSDnDfhptCyx4xUUtuw6jXL15GVPfjw/CVVk9i0ooPb9kDFMbUhU5xbYXtneGHV/ q7tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087863; x=1703692663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=szFuFOaVPRcoa/3KGK9k9VHnKNMXDyjWXMloTHpkWuA=; b=RyWWne1mfXO6J9k8h89AnE8b3W43eDEiZCDzHPHXQdoVtYk1tM4VlZXPVGRJUA2qNl F04TM3Meq9qYDRrmXCGM5DamMu0fwVxs2tNlTuxugBiDX80ShoHycXH3Z8bf8hqoDlsG oH1BMG9tm8qmK/WvF9C/NbC1fnEMj7tnKN8Z7zhWZXpVZbpkS6IFYDmCog6oYC27sCfY SUdMk4Gm0oMpSV5XNwRbnBM6Pcuxkgl7Ec0volMnBp1tO/DuTfey8X79/CHhOgXOxaq3 OWST+dUUErEscShepe1cweU1WpMPKtwO904Y7+fqTwrx+pfilEqRbici7a8IARI6VT7O FWZg== X-Gm-Message-State: AOJu0YwDKakO+GnZ4EqhswjQN1z6HUObcwiOZLXws08l+4c1lUaCVm23 Km9XOsZ5WBe8abHqMLX2wojBiQ== X-Google-Smtp-Source: AGHT+IEMopGLd13u7V/5vIZqrC6QZYkg9U757Xi60NRR7tKxLQz11Pc5U0+SfTyL2OoD9i8imBIJRw== X-Received: by 2002:a05:6512:1592:b0:50e:4ec1:7d2e with SMTP id bp18-20020a056512159200b0050e4ec17d2emr2327025lfb.2.1703087863205; Wed, 20 Dec 2023 07:57:43 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:42 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida , Conor Dooley Subject: [PATCH v2 3/6] dt-bindings: riscv: add Zacas ISA extension description Date: Wed, 20 Dec 2023 16:57:19 +0100 Message-ID: <20231220155723.684081-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add description for the Zacas ISA extension which was ratified recently. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 3574a0b70be4..27beedb98198 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,12 @@ properties: memory types as ratified in the 20191213 version of the privil= eged ISA specification. =20 + - const: zacas + description: | + The Zacas extension for Atomic Compare-and-Swap (CAS) instruct= ions + is supported as ratified at commit 5059e0ca641c ("update to + ratified") of the riscv-zacas. + - const: zba description: | The standard Zba bit-manipulation extension for address genera= tion --=20 2.43.0 From nobody Fri Dec 19 14:07:42 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E1A14653F for ; Wed, 20 Dec 2023 15:57:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Z6iYwN3I" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3367659c42aso56509f8f.0 for ; Wed, 20 Dec 2023 07:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087864; x=1703692664; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oZT3AkmSaqumQ97ecuZBaz7B+rLb1J+xdw7pERlw1ck=; b=Z6iYwN3I37Qg/yMkxLLrsXU9Lc6aPdB6HSwmf6Sj+FcrCaOyiRLYpRlSyzDWEit8GD PfKcIJ4IIXvs2Kt/TvtH/u0xhg7dkXkvnqV98aSqRY02e40zClOqAIIw0klXQB13Hjh/ /4tYyNCyfrq1IgHA6E8+G8dLUH/dIDySzFVYNKW48hxXNaRIK/R5jvph7qASCEJduP0W 4hgHwPb6C/z2yy7SoOKw5iSdfXjxTg8Ev+p0M2BxrrDc0tFV/4EAJk4/csXZBCH0Tjmt iaMLIGKxwYXrh0JPQk4+Xm7BL7DZgOQYgvHWAd2dj9xKhkzopmF/CwGVlF8CBiyQj0/X KNUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087864; x=1703692664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZT3AkmSaqumQ97ecuZBaz7B+rLb1J+xdw7pERlw1ck=; b=qd1sY2tuyzG1y5aI7ZlUgJUrS6seiLd3I4eXGgLKdeYWGu0/INIQLpTWuEgy1Xy2uP byLs5D1xyCAoDTuzjuAzbZPcwWP1oV/8B7LefWRj9wiJGYPMDDtKeLghPfmo8AKoUQpU bunh9QTjlotqLV9Z1psrmfXWpg7dQUGl0ceUcoqkCByKBgkZrkq6slGvhsjDoaw42zyC TYOi25v+2KXU6pSXuCpC6LylfLcqWdOZPZ1YxdgueBSx0cM0qDegKLVSk0LsXLo0ZXLy Is1x7CLXjOf87ipYvLp8QNCRoKI+QpHROCaEZn136OnLxaOqoiTJi97ey8rSB0brUHu/ +oTg== X-Gm-Message-State: AOJu0YxvmvCb9r9qJ4IwI/PYuwjvd0lPnz2sLngAhnQ75I0otaFeJNiP 3hdqu/Nx69QF0r4K+PVDbxEP/VUXZUUlI7urSeB2DQ== X-Google-Smtp-Source: AGHT+IEAqrHN3Za66t0NZjui8EhChki4mQcTMIh6RZgm58ClLt3lfkny0M8iVRzoKzGcB9ZORNH4uw== X-Received: by 2002:a05:6000:18c9:b0:336:5c96:a3c7 with SMTP id w9-20020a05600018c900b003365c96a3c7mr7715482wrq.0.1703087864600; Wed, 20 Dec 2023 07:57:44 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:43 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 4/6] riscv: add ISA extension parsing for Zacas Date: Wed, 20 Dec 2023 16:57:20 +0100 Message-ID: <20231220155723.684081-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add parsing for Zacas ISA extension which was ratified recently in the riscv-zacas manual. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 3b31efe2f716..34f86424d743 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -85,6 +85,7 @@ #define RISCV_ISA_EXT_ZVFHMIN 70 #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 +#define RISCV_ISA_EXT_ZACAS 73 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3eb48a0eecb3..9a9d915b5bb2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), --=20 2.43.0 From nobody Fri Dec 19 14:07:42 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F46B4778A for ; Wed, 20 Dec 2023 15:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="NzBKYKLU" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-40c32e205fcso9882035e9.1 for ; Wed, 20 Dec 2023 07:57:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087866; x=1703692666; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3BPMv24jdGVieLmHRP/43iA/a2qmOUrYJR1MkKgXts4=; b=NzBKYKLUmxix01P/sgfDv+lGEi7erCjcNxtG8VaOb3wwaYz9gHGcpvGc0elpDg1Cej G+lA/Xzo5MNGMS6vilbzv/5j8BgNg6dCs+ZDq+QlxHmHam+uwsvAtPvRt/38gqmh/Ede c+Bwmgxo+vEoHQEbC0sSeqEp8CFFFj3M6zVdc114YZoxhkcdw3yg/WTCUzXfR3uqT20e 7JSvv9GMYskaL1Q55bmcnh12izXxsS3L6YY1XBS4dyfa5Eda0kXRi+/Tksjee9g0Jwrs qvF/1oQxrfUyZ2K1Gr/mjMyNTfU1PkeiWf0logVke+NawHkUuc2LC83iyCLd8Lel0Sfy 038g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087866; x=1703692666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3BPMv24jdGVieLmHRP/43iA/a2qmOUrYJR1MkKgXts4=; b=VnwxSrgpIO/2f0YrzuBdvnMwxGjaBEA05KUW5veIp/h25Ymgx4UFhIkMDU7FYG5yZ6 ETWbvi8gtf3H+dms6MHnjiHKMmPMhwGznyDkYH5dXje3auCdNvU15evff5z7B34EIndZ bqzIcgv0HRWC81EYNjqkdRp+XAkevbuvqpdDCVkAanQeiONTLjCnq5dEEXt/5ABN0QLt 26YHtQlUMD5p1pCIzHUJ82/9hQ7JWVZRuxhXKcFGtPMvXh8qNEMW9Mma8/NwDgUQJguT 6qGb5wdF1xc5Way7p+NV/gNn0oq0V1TT6qz8v8VoEQNDNhHDsCg9/dW86A/Vv32ja1N4 dyOQ== X-Gm-Message-State: AOJu0YyZchUgKlC0HOWoMLByO8s1folWQqXUIZe1CkL3kNy8lq4CCYNo 5vrHdcniZAEhPHFRldsAZOo8sg== X-Google-Smtp-Source: AGHT+IHhRAXXz42/u2vdF2rRn+pcNPzJD+CGhaPX7dsedwK3pxf8bg5I86xeWYEngCYQhOlYz8+CIQ== X-Received: by 2002:a05:600c:3b98:b0:40d:3880:b046 with SMTP id n24-20020a05600c3b9800b0040d3880b046mr1065572wms.4.1703087865822; Wed, 20 Dec 2023 07:57:45 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:45 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 5/6] riscv: hwprobe: export Zacas ISA extension Date: Wed, 20 Dec 2023 16:57:21 +0100 Message-ID: <20231220155723.684081-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Export Zacas ISA extension through hwprobe. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 10bd7b170118..bff68004ad43 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -165,6 +165,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 5618fb5a216b ("Ztso is now ratified.") =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as + defined in the Atomic Compare-and-Swap (CAS) instructions manual st= arting + from commit 5059e0ca641c ("update to ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 01ac3dc196e5..ac65bb43c8e7 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -57,6 +57,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) +#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 6564fa9e7a7f..6c680c75ac0d 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -175,6 +175,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); EXT_KEY(ZTSO); + EXT_KEY(ZACAS); =20 if (has_vector()) { EXT_KEY(ZVBB); --=20 2.43.0 From nobody Fri Dec 19 14:07:42 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA5FA47A73 for ; Wed, 20 Dec 2023 15:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fDYzBUSL" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40d08be5fdbso10635695e9.1 for ; Wed, 20 Dec 2023 07:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087867; x=1703692667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TXiIygoI2xfoAtWyxNJaEZbhAX2C42esk/G1o5mFVH8=; b=fDYzBUSLvR2PzV2deSxttD8JpjEI3lHd1RYNM1OAnvZjSDm9fzRHOdb2RE3BnzbbVE nFmjtTmnynnCMZ0jGtXncqEff5/6dGf/CJLED1klg4ukqF5dLN7XfDZVG5CM+js2CwKY LmraTAcKYf2xmG0BN6OFgBi3l4Jaj5hRFF19Tr6SzplWuLJ2YJ+OY2xSjglqKOXud8Rz d5QURqcciZ34J8XoTfmMph6eiQTyOpag8YOLULbUGcWocG2edn15xvuzWYwHSWwS0CVh uSDnztPFX+UWcy+5k7cr3OjZgUHZAF3huqGAj4zFpKQVdPFHV8wojykglUyRNfkkxd4W 1DKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087867; x=1703692667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TXiIygoI2xfoAtWyxNJaEZbhAX2C42esk/G1o5mFVH8=; b=nB+VpdVLV5e73UdJEWiEeUJ2OMOaqv2iDJFBdvzezUbEipvGlfh69IJrswfJAboaRB 5Mzzzy3XX7Su9FhFPAKDiEygQlWqn8zQRbuRviqSNhe2i5AeC7xzBj4bxKEMb13IzfjB zonNsHjn0JgZO7BPN3CS9SfSXr3uoq9EGhlOlelyIwFhPM/32k4mBlFbhU4kFGb1zO4o N8IyF+KqJTUy8L8DmbKOyJltjelDhKnId1ofvPteuoZ50O3MNZdDWhgQhZM0VIrhqo6A c2oJA/HGBJoVPf/0m77SrqsLB6INI/nGk2NXmfDuTLHLAT3uuaJWhJhnD2m+rifmy70w icZg== X-Gm-Message-State: AOJu0YzJqD6nYsFjAOG1INmO+OgrjSfYQ3VKBtpfRUCpqe/9+ZLawOY/ 40WCtVTrHQir3duA5ya49+0rdA== X-Google-Smtp-Source: AGHT+IEpr+96oxZFiK4cxomHHqE/jg1PvdGozQiMvvlQ4NTHaFlfmPa9ipv0kbSLSizkLF3AkktCuw== X-Received: by 2002:adf:e2c4:0:b0:336:4a0e:4284 with SMTP id d4-20020adfe2c4000000b003364a0e4284mr12246378wrj.6.1703087867017; Wed, 20 Dec 2023 07:57:47 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:46 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 6/6] riscv: hwprobe: export Zicond extension Date: Wed, 20 Dec 2023 16:57:22 +0100 Message-ID: <20231220155723.684081-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Export the zicond extension to userspace using hwprobe. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 5 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 7 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index bff68004ad43..ee320fe7581b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -169,6 +169,11 @@ The following keys are defined: defined in the Atomic Compare-and-Swap (CAS) instructions manual st= arting from commit 5059e0ca641c ("update to ratified"). =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported= as + defined in the RISC-V Integer Conditional (Zicond) operations exten= sion + manual starting from commit 95cf1f9 ("Add changes requested by Ved + during signoff") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index ac65bb43c8e7..fd7af0dddb12 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -58,6 +58,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) +#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 6c680c75ac0d..cca9b1e35647 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIHINTNTL); EXT_KEY(ZTSO); EXT_KEY(ZACAS); + EXT_KEY(ZICOND); =20 if (has_vector()) { EXT_KEY(ZVBB); --=20 2.43.0